Datasheet ICS8530DY-01, ICS8530DY-01T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

GENERAL DESCRIPTION

,&6

HiPerClockS™

levels. The high gain differential amplifier accepts peak-to­peak input voltages as small as 150mV as long as the com­mon mode voltage is within the specified minimum and maxi­mum range.

Guaranteed output and part-to-part skew characteristics
make the ICS8530-01 ideal for those clock distribution appli­cations demanding well defined performance and repeatabil­ity.

The ICS8530-01 is a low skew, 1-to-16 Dif feren­tial-to-3.3V LVPECL Fanout Buffer and a mem­ber of the HiPerClockS™ family of High Perfor­mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input

FEATURES

• 16 differential 3.3V L VPECL outputs

• CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential input

levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL

• Maximum output frequency up to 500MHz

• Translates any single-ended input signal to 3.3V L VPECL

levels with a resistor bias on nCLK input

• Output skew: 75ps (maximum)

• Part-to-part skew: 250ps (maximum)

• 3.3V output operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM PIN ASSIGNMENT

nQ13

nQ12

CLK

nCLK

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

Q5

nQ5

Q6

nQ6

Q7

nQ7

Q15
nQ15

Q14
nQ14

Q13
nQ13

Q12
nQ12

Q11
nQ11

Q10
nQ10

Q9
nQ9

Q8
nQ8

VCCO

Q11

nQ11

Q10

nQ10

V

nQ9

nQ8

V

CCO

VCC

V

Q12

CCO

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6

Q9

Q8

EE

7
8
9
10
11
12

ICS8530-01

13 14 15 16 17 18 19 20 21 22 23 24

nQ7

Q7

V

VCC

CCO

48-Pin LQFP

7mm x 7mm x 1.4mm package body

nQ14

Q14

Q13

V

EE

Q5

VEEnQ6

Q6

Y Package

Top View

nQ15

nQ5

Q15

Q4

V

CCO

nQ4

nCLK

36
35
34
33
32
31
30
29
28
27
26
25

VCCO

CLK
VCCO
nQ0
Q0
nQ1
Q1
V

EE

nQ2
Q2
nQ3
Q3
Vcco

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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Integrated
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TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

,42,41,11,1

84,83,53,52

3,211Qn,11QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
5,401Qn,01QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

34,03,91,6V

8,79Qn,9QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

01,98Qn,8QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

31,21V
61,517Qn,7QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
81,716Qn,6QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
12,025Qn,5QtuptuO..slevelecafretniLCEPVL.riaptuptuolaitnereffiD
32,224Qn,4QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
72,623Qn,3QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

92,822Qn,2QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
63KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
73KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI

04,9351Qn,51QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

24,1441Qn,41QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

54,4431Qn,31QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

74,6421Qn,21QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

:ETON

pulluP

V

dna

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

OCC

EE

CC

nwodlluP

rewoP.V3.3ottcennoC.snipylppustuptuO

rewoP.dnuorgottcennoC.snipylppusevitageN

rewoP.V3.3ottcennoC.snipylppusevitisoP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

C

NI

R

PULLUP

R

NWODLLUP

ecnaticapaCtupnI

rotsiseRpulluPtupnI 15KΩ

KLCn,KLC

rotsiseRnwodlluPtupnI 15KΩ

4Fp

TABLE 3. FUNCTION TABLE

stupnIstuptuO

KLCKLCn51Qurht0Q51Qnurht0Qn

01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN

10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN

01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN

11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN

1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI

.sleveldedneelgnistpeccaottupni

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

2

edoMtuptuOottupnIytiraloP

laitnereffidehtgniriwsessucsidhcihw,8erugiF,7egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON

Integrated
Circuit
Systems, Inc.

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

ICS8530-01

LOW SKEW, 1-TO-16

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V
Inputs, V

I

Outputs, V
Package Thermal Impedance, θ

Storage T emperature, T

CCx

O

JA

STG

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics

or

AC Characteristics

ods may affect product reliability.

4.6V

-0.5V to VCC + 0.5V

-0.5V to V

CCO

+ 0.5V

47.9°C/W

-65°C to 150°C

is not implied. Exposure to absolute maximum rating conditions for extended peri-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

CC

V

OCC

I

EE

egatloVylppuSeroc/tupnI 531.33.3564.3V
egatloVylppuStuptuO 531.33.3564.3V
tnerruCylppuSrewoP 021Am

TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

KLCV

I

HI

I

LI

V

PP

V

RMC

2,1ETON

tnerruChgiHtupnI

tnerruCwoLtupnI

KLCnV

KLCV

KLCnV

egatloVtupnIkaeP-ot-kaeP 51.03.1V

;egatloVtupnIedoMnommoC

VsadenifedsiegatlovedomnommoC:2ETON

CC

= V

CC

= V

.

= 3.3V±5%, TA = 0°C TO 70°C

CCO

= 3.3V±5%, TA = 0°C TO 70°C

CCO

V=

CC

NI

V=

CC

NI

CC

CC

V564.3=051Aµ
V564.3=5Aµ

V,V564.3=

V0=5-Aµ

NI

V,V564.3=

V0=051-Aµ

NI

V

5.0+V

EE

VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON

CC

.V3.0+

CC

58.0-V

TABLE 4C. LVPECL DC CHARACTERISTICS, V

CC

= V

= 3.3V±5%, TA = 0°C TO 70°C

CCO

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HO

V

LO

V

GNIWS

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

1ETON;egatloVhgiHtuptuOV

1ETON;egatloVwoLtuptuOV

gniwSegatloVtuptuOkaeP-ot-kaeP 6.058.0V

05htiwdetanimretstuptuO:1ETON Ω Vot

.V2-

OCC

3

4.1-V

OCC

0.2-V

OCC

OCC

OCC

0.1-V

7.1-V

Integrated
Circuit
Systems, Inc.

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

f

XAM

t

DP

t

)o(ks4,2ETON;wekStuptuO 57sp

t

)pp(ks4,3ETON;wekStraP-ot-traP 88052sp

t

R

t

F

cdoelcyCytuDtuptuO740535%

= V

CC

emiTesiRtuptuOzHM05@%08ot%02003007sp

emiTllaFtuptuOzHM05@%08ot%02003007sp

.stniopssorclaitnereffidehtta

= 3.3V±5%, TA = 0°C TO 70°C

CCO

ycneuqerFtuptuOmumixaM 005zHM

1ETON;yaleDnoitagaporP IJ zHM0051 2sn

.esiwrehtodetonsselnuzHM052taderusaemsretemarapllA

.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

.stniopssorclaitnereffidtuptuoehttaderusaeM

segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON

derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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PARAMETER MEASUREMENT INFORMATION

V

CC

LVPECL

VCC = 2V ± 5%
V

CCO

V

CCO

= 2V ± 5%

VEE = -1.3V ± 0.135V

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

SCOPE

Qx

nQx

Qx

nQx

V

CLK

nCLK

V

FIGURE 1 - OUTPUT LOAD TEST CIRCUIT

CC

V

VPP

EE

Cross Points

CMR

FIGURE 2 - DIFFERENTIAL INPUT LEVEL

Qy

nQy

tsk(o)

FIGURE 3 - OUTPUT SKEW

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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Qx

PART 1

nQx

Qy

PART 2

nQy

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

tsk(pp)

FIGURE 4 - PART-TO-PART SKEW

ICS8530-01

LOW SKEW, 1-TO-16

Clock Inputs
and Outputs

CLK

nCLK

Q0 - Q15

nQ0 - nQ15

80%

20%

t

R

t

F

FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME

t

PD

FIGURE 6 - PROPAGATION DELAY

80%

20%

V

SWING

CLK, Qx

nCLK, nQx

Pulse Width

t

PERIOD

t

odc =

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

PW

t

PERIOD

FIGURE 7 - odc & t

6

PERIOD

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D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

APPLICA TION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

ICS8530-01

LOW SKEW, 1-TO-16

Figure 8

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.

shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is

CLK_IN

C1

0.1uF

FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

R1
1K

V_REF

R2
1K

VCC

+

-

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D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

ICS8530-01

LOW SKEW, 1-TO-16

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8530-01.
Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

= 3.3V + 5% = 3.465V , which gives worst case results.

CC

• Power (core)

• Power (outputs)

If all outputs are loaded, the total power is 16 * 30.2mW = 483.2mW

T otal Power

2. Junction T emperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS

The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature

θJA = junction-to-ambient thermal resistance

Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T

= Ambient T emperature

A

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.9°C/W per T able 6 below .

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.899W * 47.9°C/W = 1 13.1°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).

MAX

= V

MAX

_MAX

* I

CC_MAX

= 30.2mW/Loaded Output pair

= 3.465V * 120mA = 415.8mW

EE_MAX

(3.465V , with all outputs switching) = 415.8mW + 483.2mW = 899mW

TM

devices is 125°C.

* Pd_total + T

JA

A

JA

must be used . Assuming a

Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection

q

by Velocity (Linear Feet per Minute)

JA

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

ICS8530-01

LOW SKEW, 1-TO-16

LVPECL output driver circuit and termination are shown in

Figure 9.

V

CCO

Q1

V

OUT

RL

50

V

- 2V

CCO

FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of VCC- 2V .
Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low .

Pd_H = [(V
Pd_L = [(V

• For logic high, V
Using V

• For logic low , V
Using V

OH_MAX

OL_MAX

– (V

– (V

CC_MAX

CC_MAX

- 2V))/RL]*(V

CC_MAX

- 2V))/RL]*(V

CC_MAX

= V

OUT

OH_MAX

= 2.625, this results in V

= V

OUT

OL_MAX

= 2.625, this results in V

= V

= V

CC_MAX

CC_MAX

CC_MAX

CC_MAX

- V

- V

OL_MAX

– 1.0V

OH_MAX

– 1.7V

OL_MAX

OH_MAX

= 1.625V

= 0.925V

)

)

Pd_H = [(1.625V - (2.625V - 2V))/50 Ω]*(1V) = 20mW
Pd_L = [(0.925V - (2.625V - 2V))/50 Ω]*(1.7) = 10.2mW

T otal Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

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D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

RELIABILITY INFORMATION

ICS8530-01

LOW SKEW, 1-TO-16

TABLE 7. θ

TRANSISTOR COUNT

The transistor count for ICS8530-01 is: 930

VS

. AIR FLOW TABLE

JA

q

JA

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

by V elocity (Linear Feet per Minute)

0 200 500

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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PACKAGE OUTLINE - Y SUFFIX

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

TABLE 8. PACKAGE DIMENSIONS

NOITAIRAVCEDEJ

LOBMYS

N
A

1A

2A
b
c
D

1D

2D
E

1E

2E
e
L

q

ccc

Reference Document: JEDEC Publication 95, MS-026

MUMINIMLANIMONMUMIXAM

84

----06.1

50.0--51.0

53.104.154.1

71.022.072.0

90.0--02.0

54.006.057.0

°

0

----80.0

--

SRETEMILLIMNISNOISNEMIDLLA

CBB

CISAB00.9
CISAB00.7

.feR05.5

CISAB00.9
CISAB00.7

.feR05.5

CISAB05.0

7

°

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

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TABLE 9. ORDERING INFORMATION

rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT

10-YD0358SCI10-YD0358SCIPFQLdaeL84yartrep052C°07otC°0

T10-YD0358SCI10-YD0358SCIleeRdnaepaTnoPFQLdaeL840001C°07otC°0

ICS8530-01

LOW SKEW, 1-TO-16

D

IFFERENTIAL-TO-3.3V L VPECL FANOUT BUFFER

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.

ICS8530DY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 8, 2001

12