Page 1
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
puts. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics
make the ICS85304-01 ideal for those applications
demanding well defined performance and repeatability.
The ICS85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS85304-01 has two selectable clock in-
FEATURES
• 5 differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: L VDS, L VPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V L VPECL
levels with resistor bias on nCLK input
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
0
0
1
1
D
Q
LE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
6.5mm x 4.4mm x 0.92mm Package Body
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
ICS85304-01
20-Lead TSSOP
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
G Package
Top View
V
CC
CLK_EN
V
CC
nPCLK
PCLK
V
EE
nCLK
CLK
CLK_SEL
V
CC
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
2,10Qn,0QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
6,52Qn,2QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
8,73Qn,3QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
01,94Qn,4QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,81,11V
21LES_KLCtupnInwodlluP
31KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
41KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
51V
61KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
71KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
91NE_KLCtupnIpulluP
pulluP
:ETON
CC
EE
dna
nwodlluP
rewoP.V3.3ottcennoC.snipylppusevitisoP
rewoP.dnuorgottcennoC.nipylppusevitageN
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleskcolC
.stupniKLCn,KLCstceles,WOLnehW
.slevelecafretniSOMCVL/LTTVL
kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniSOMCVL/LTTVL.hgih
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
R
PULLUP
R
NWODLLUP
KLCn,KLC4Fp
ecnaticapaCtupnI
rotsiseRpulluPtupnI 15KΩ
rotsiseRnwodlluPtupnI 15KΩ
KLCPn,KLCP4Fp
,NE_KLC
LES_KLC
4Fp
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
2
Page 3
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS4Qurht0Q4Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE
.1erugiFninwohssa
.B3elbaTni
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
nCLK, nPCLK
Disabled
CLK, PCLK
CLK_EN
nQ0 - nQ4
Q0 - Q4
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
KLCroKLCKLCPnroKLCPn4Qurht0Q4Qnurht0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
.sleveldedneelgnistpeccaottupni
Enabled
FIGURE 1 - CLK_EN TIMING DIAGRAM
edoMtuptuOottupnIytiraloP
laitnereffidehtgniriwsessucsidhcihw,8erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage T emperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
ods may affect product reliability.
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for extended peri-
TABLE 4A. POWER SUPPLY CHARACTERISTICS, V
=3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
I
EE
egatloVylppuSrewoP531.33.3564.3V
tnerruCylppuSrewoP 55Am
TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
egatloVhgiHtupnI
egatloVwoLtupnI
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
KLCnV
I
HI
I
LI
V
PP
V
RMC
2,1ETON
tnerruChgiHtupnI
KLCV
tnerruCwoLtupnI
KLCnV
KLCV
,NE_KLC
LES_KLC
,NE_KLC
LES_KLC
NE_KLCV
LES_KLCV
NE_KLCV
LES_KLCV
CC
egatloVtupnIkaeP-ot-kaeP 51.03.1V
;egatloVtupnIedoMnommoC
VsadenifedsiegatlovedomnommoC:2ETON
=3.3V±5%, TA = 0°C TO 70°C
CC
V=
NI
CC
V=
NI
CC
CC
CC
V564.3=5Aµ
V564.3=051Aµ
V,V564.3=
V0=051-Aµ
NI
V,V564.3=
V0=5-Aµ
NI
=3.3V±5%, TA = 0°C TO 70°C
V=
CC
NI
V=
CC
NI
CC
CC
V564.3=5Aµ
V564.3=051Aµ
V,V564.3=
V0=051-Aµ
NI
V,V564.3=
V0=5-Aµ
NI
.
2567.3V
3.0-8.0V
5.0V
VsiKLCn,KLCrofegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:1ETON
CC
.V3.0+
58.0-V
CC
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
4
Page 5
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V
=3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
V
HO
V
LO
V
GNIWS
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 5. AC CHARACTERISTICS, V
KLCPV
KLCPnV
KLCPV
KLCPnV
egatloVtupnIkaeP-ot-kaeP 51.03.1V
2,1ETON;egatloVtupnIedoMnommoC 5.0V
3ETON;egatloVhgiHtuptuOV
3ETON;egatloVwoLtuptuOV
gniwSegatloVtuptuOkaeP-ot-kaeP 6.058.0V
VsadenifedsiegatlovedomnommoC:1ETON
.
HI
05htiwdetanimretstuptuO:3ETON Ω Vot
=3.3V±5%, TA = 0°C TO 70°C
CC
.V2-
V=
CC
NI
V=
CC
NI
CC
CC
V564.3=051Aµ
V564.3=5Aµ
V,V564.3=
V0=5-Aµ
NI
V,V564.3=
V0=051-Aµ
NI
CC
4.1-V
CC
0.2-V
CC
VsiKLCPn,KLCProfegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
CC
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
t
DP
t
)o(ks4,2ETON;wekStuptuO 53sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 051sp
t
R
t
F
emiTesiRtuptuOzHM05@%08ot%02003007sp
emiTllaFtuptuOzHM05@%08ot%02003007sp
ycneuqerFtuptuOmumixaM 056zHM
1ETON;yaleDnoitagaporP IJ zHM0560.11.2sn
cdoelcyCytuDtuptuO840525sp
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA
rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
58.0-V
0.1-V
7.1-V
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
5
Page 6
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
V
CC
LVPECL
VCC = 2V
V
EE =
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
SCOPE
Qx
nQx
-1.3V ± 0.135V
nCLK, nPCLK
Qx
nQx
V
CLK, PCLK
V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
CC
VPP
EE
Cross Points
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
V
CMR
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
6
Page 7
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Clock Inputs
and Outputs
CLK, PCLK
nCLK, nPCLK
Q0 - Q4
nQ0 - nQ4
80%
20%
t
R
t
F
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
t
PD
FIGURE 6 - PROPAGATION DELAY
80%
20%
V
SWING
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
t
PERIOD
t
odc =
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
PW
t
PERIOD
FIGURE 7 - odc & t
7
PERIOD
Page 8
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICA TION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
= 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
CC
CLK_IN
CLK_IN
C1
0.1uF
C1
0.1uF
R1
1K
R1
1K
V_REF
V_REF
R2
1K
R2
1K
VCC
VCC
+
+
-
-
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
8
Page 9
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85304-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85304-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
• Power (core)
• Power (outputs)
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 55mA = 190.57mW
EE_MAX
(3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.341W * 66.6°C/W = 92.71°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
TM
devices is 125°C.
must be used . Assuming a
JA
T able 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
q
by V elocity (Linear Feet per Minute)
JA
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
9
Page 10
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
RL
50
ICS85304-01
LOW SKEW, 1-TO-5
V
OUT
V
- 2V
CC
FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load,
and a termination voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
• For logic high , V
Using V
• For logic low , V
Using V
(V
OH_MAX
OL_MAX
CC
(VCC- 2V))/RL]*(V
= 3.465, this results in V
CC
= 3.465, this results in V
CC
- 2V))/RL]*(V
= V
OUT
OUT
= V
OH_MAX
OL_MAX
- V
CC
OH_MAX
- V
CC
OL_MAX
= VCC 1.0V
OH_MAX
= V
1.7V
CC
OL_MAX
)
)
= 2.465V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
10
Page 11
Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θ
TRANSISTOR COUNT
The transistor count for ICS85304-01 is: 489
VS
. AIR FLOW TABLE
JA
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
11
Page 12
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
LOBMYS
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α
aaa--01.0
Reference Document: JEDEC Publication 95, MO-153
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
NIMXAM
°0 °8
12
sretemilliM
Page 13
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
10-GA40358SCI10-GA40358SCIPOSSTdael02ebutrep27C°07otC°0
T10-GA40358SCI10-GA40358SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001
13
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