Datasheet ICS8525BG, ICS8525BG-T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

GENERAL DESCRIPTION

,&6

HiPerClockS™

cept LVCMOS or LVTTL input levels and translate them to

1.8V L VHSTL levels. The clock enable is internally synchro­nized to eliminate runt pulses on the outputs during asyn­chronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.

The ICS8525 is a low skew, high performance
1-to-4 L VCMOS-to-LVHSTL fanout buf fer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that ac-

FEATURES

• 4 differential 1.8V L VHSTL outputs

• Selectable LVCMOS / LVTTL clock inputs for redundant

and multiple frequency fanout applications

• Maximum output frequency up to 266MHz

• Translates L VCMOS and LVTTL levels to 1.8V

L VHSTL levels

• Output skew: 35ps (maximum)

• Part-to-part skew: 150ps (maximum)

• Propagation delay: 1.9ns (maximum)

• 3.3V core, 1.8V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM PIN ASSIGNMENT

CLK_EN

CLK0
CLK1

CLK_SEL

D

Q

LE

0
1

Q0
nQ0

Q1
nQ1

Q2
nQ2

Q3
nQ3

6.5mm x 4.4mm x 0.92mm Package Body

GND

CLK_EN

CLK_SEL

CLK0

nc

CLK1

nc
nc
nc

V

DD

20-Lead TSSOP

20

1

19

2

18

3

17

4

16

5

15

6

14

7

13

8

12

9

11

10

ICS8525

G Package

T op View

Q0
nQ0
V

DDO

Q1
nQ1
Q2
nQ2
V

DDO

Q3
nQ3

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

1

Integrated
Circuit
Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

1DNGrewoP.dnuorgottcennoC.dnuorgylppusrewoP

2NE_KLCtupnIpulluP

3LES_KLCtupnInwodlluP
40KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL

61KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL

9,8,7,5cndesunU.tcennocoN

01V

81,31V
21,113Q,3QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
51,412Q,2QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD

pulluP

:ETON

DD

ODD

dna

nwodlluP

rewoP.V3.3ottcennoC.nipylppusevitisoP
rewoP.V8.1ottcecnnoC.snipylppustuptuO

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS

.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni

.slevelecafretniLTTVL/SOMCVL

.tupni1KLCstceles,HGIHnehW.tupnitceleskcolC

.slevelecafretniLTTVL/SOMCVL.tupni0KLCstceles,WOLnehW

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

C

NI

R

PULLUP

R

NWODLLUP

1KLC,0KLC4Fp

ecnaticapaCtupnI

rotsiseRpulluPtupnI 15KΩ

,NE_KLC
LES_KLC

rotsiseRnwodlluPtupnI 15KΩ

4Fp

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

2

Integrated
Circuit
Systems, Inc.

TABLE 3A. CONTROL INPUT FUNCTION TABLE

stupnIstuptuO

NE_KLCLES_KLCecruoSdetceleS3Qurht0Q3Qnurht0Qn

00 0KLCWOL;delbasiDHGIH;delbasiD
01 1KLCWOL;delbasiDHGIH;delbasiD

10 0KLCdelbanEdelbanE
11 1KLCdelbanEdelbanE

.1erugiFninwohssa

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuookcolceht,sehctiwsNE_KLCretfA

.B3elbaTnidebircsedsastupni1KLCdna0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

CLK0, CLK1

CLK_EN

nQ0 - nQ3

Q0 - Q3

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO

1KLCro0KLC3Qurht0Q3Qnurht0Qn

0WOLHGIH

1HGIHWOL

EnabledDisabled

FIGURE 1 - CLK_EN TIMING DIAGRAM

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

3

Integrated
Circuit
Systems, Inc.

LOW SKEW, 1-TO-4

ICS8525

LVCMOS-TO-L VHSTL FANOUT BUFFER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V
Inputs, V

I

Outputs, V
Package Thermal Impedance, θ

Storage Temperature, T

DDx

O

JA

STG

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat­ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the

DC Characteristics

or

AC Characteristics

extended periods may affect product reliability.

4.6V

-0.5V to VDD + 0.5V

-0.5V to V

DDO

+ 0.5V

73.2°C/W (0lfpm)

-65°C to 150°C

is not implied. Exposure to absolute maximum rating conditions for

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V

= 3.3V±5%, V

DD

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

DD

V

ODD

I

DD

egatloVylppuSevitisoP531.33.3564.3V
egatloVylppuStuptuO6.18.10.2V
tnerruCylppuSrewoP 05Am

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1KLC,0KLC2567.3V

V

HI

V

LI

I

HI

I

LI

egatloVhgiHtupnI

,NE_KLC
LES_KLC

1KLC,0KLC3.0-3.1V

egatloVwoLtupnI

,NE_KLC
LES_KLC

,1KLC,0KLC

tnerruChgiHtupnI

LES_KLC

NE_KLCV

,1KLC,0KLC

tnerruCwoLtupnI

LES_KLC

V

NE_KLCV

= 3.3V±5%, V

DD

V=

V

DD

NI

V=

DD

NI

DD

DD

= 1.8V±0.2V , TA = 0°C TO 70°C

DDO

= 1.8V±0.2V, TA = 0°C TO 70°C

DDO

2567.3V

3.0-8.0V

V564.3=051Aµ
V564.3=5Aµ

V,V564.3=

V0=5-Aµ

NI

V,V564.3=

V0=051-Aµ

NI

TABLE 4C. L VHSTL DC CHARACTERISTICS, V

= 3.3V±5%, V

DD

= 1.8V±0.2V , TA = 0°C TO 70°C

DDO

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HO

V

LO

V

XO

V

GNIWS

1ETON

1ETON

kaeP-ot-kaeP

;egatloVhgiHtuptuO

;egatloVwoLtuptuO

egatloVrevossorCtuptuOV(x%04

gniwSegatloVtuptuO

12.1V

04.0V

HOV-LO

V+)

LO

V(x%06

HOV-LO

V+)

V

LO

57.052.1V

05htiwdetanimretstuptuO:1ETON Ω .DNGot

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

4

Integrated
Circuit
Systems, Inc.

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

f

XAM

t

DP

t

)o(ks4,2ETON;wekStuptuO 53sp

t

)pp(ks4,3ETON;wekStraP-ot-traP 051sp

t

R

t

F

cdoelcyCytuDtuptuO540555%

emiTesiRtuptuOzHM05@%08ot%02003007sp

emiTllaFtuptuOzHM05@%08ot%02003007sp

DD

.stniopssorclaitnereffidehtta

= 3.3V±5%, V

ycneuqerFtuptuOmumixaM 662zHM

1ETON;yaleDnoitagaporP IJ zHM6620.19.1sn

= 1.8V±0.2V, TA = 0°C TO 70°C

DDO

.esiwrehtodetonsselnuzHM662taderusaemsretemarapllA

.stniopssorclaitnereffidtuptuoehttaderusaeM

.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT

.tniopgnissorctuptuolaitnereffidehtottupniehtfotniop%05ehtmorfderusaeM:1ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

dnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON

derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

5

Integrated
Circuit
Systems, Inc.

LOW SKEW, 1-TO-4

ICS8525

LVCMOS-TO-L VHSTL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

V

DDO

V

DD

SCOPE

Qx

LVHSTL

V

3.3V ± 5%

DD =

1.8V ± 0.2V

V

DDO =

nQx

Qx

nQx

Qy

nQy

PART 1

GND = 0V

FIGURE 2 - OUTPUT LOAD TEST CIRCUIT

tsk(o)

FIGURE 3 - OUTPUT SKEW

Qx

nQx

Qy

PART 2

nQy

tsk(pp)

FIGURE 4 - PART-TO-PART SKEW

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

6

Integrated
Circuit
Systems, Inc.

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

Clock Inputs
and Outputs

CLK0, CLK1

Q0 - Q3

nQ0 - nQ3

80%

20%

t

R

t

F

FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME

t

PD

80%

20%

V

SWING

CLK0, CLK 1, Qx

nQx

FIGURE 6 - PROPAGATION DELAY

Pulse Width

t

PERIOD

t

t

PERIOD

PW

odc =

FIGURE 7 - odc & t

PERIOD

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

7

Integrated
Circuit
Systems, Inc.

LOW SKEW, 1-TO-4

ICS8525

LVCMOS-TO-L VHSTL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8525.
Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

= 3.3V + 5% = 3.465V , which gives worst case results.

DD

• Power (core)

• Power (outputs)

If all outputs are loaded, the total power is 4 x 32mW = 128mW

Total Power

MAX

_MAX

= V

MAX

* I

DD_MAX

= 32mW/Loaded Output pair

= 3.465V * 50mA = 173.25mW

DD_MAX

(3.465V, with all outputs switching) = 173.25mW + 128mW = 301.25mW

2. Junction T emperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS

The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature

θ

= junction-to-ambient thermal resistance

JA

Pd_total = Total device power dissipation (example calculation is in section 1 above)
T

= Ambient T emperature

A

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow ,
and the type of board (single layer or multi-layer).

* Pd_total + T

JA

A

TM

devices is 125°C.

must be used . Assuming a

JA

Table 6. Thermal Resistance

qJA for 20-pin TSSOP, Forced Convection

qJA by Velocity (Linear Feet per Minute)

0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

8

Integrated
Circuit
Systems, Inc.

LVCMOS-TO-L VHSTL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

ICS8525

LOW SKEW, 1-TO-4

L VHSTL output driver circuit and termination are shown in

FIGURE 8 - LVHSTL DRIVER CIRCUIT AND TERMINATION

Figure 8.

V

DDO

Q1

RL

50

V

DDO

V

OUT

- 2V

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of VDD- 2V .

Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .

Pd_H = (V
Pd_L = (V

OH_MAX /RL

OL_MAX /RL

• For logic high, V

• For logic low, V

) * (V

) * (V

DD_MAX

DD_MAX

OUT

= V

OUT

- V

= V

- V

OL_MAX

OH_MAX

OL_MAX

OH_MAX

= V

)

)

= V

DD_MAX

DD_MAX

– 1.2V

– 0.4V

Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

9

Integrated
Circuit
Systems, Inc.

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

RELIABILITY INFORMATION

TABLE 7. θ

TRANSISTOR COUNT

The transistor count for ICS8525 is: 484

VS

. AIR FLOW TABLE

JA

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

qJA by Velocity (Linear Feet per Minute)

0 200 500

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

10

Integrated
Circuit
Systems, Inc.

PACKAGE OUTLINE - G SUFFIX

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

TABLE 8. PACKAGE DIMENSIONS

LOBMYS

N02
A--02.1

1A50.051.0

2A08.050.1
b91.003.0
c90.002.0

D04.606.6
ECISAB04.6

1E03.405.4
eCISAB56.0
L54.057.0

α

aaa--01.0

REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

NIMXAM

°0 °8

11

sretemilliM

<

Integrated
Circuit
Systems, Inc.

TABLE 9. ORDERING INFORMATION

rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT

GB5258SCIGB5258SCIPOSSTdael02ebutrep27C°07otC°0

T-GB5258SCIGB5258SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-L VHSTL FANOUT BUFFER

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom­mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.

8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001

12