Datasheet ICS8521BY Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

GENERAL DESCRIPTION

,&6

HiPerClockS™

accept most standard differential input levels. The PCLK,
nPCLK pair can accept L VPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulseson the outputs during asynchronous assertion/
deassertion of the clock enable pin.

Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.

The ICS8521 is a low skew, 1-to-9 3.3V Differ­ential-to-LVHSTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8521 has two
selectable clock inputs. The CLK, nCLK pair can

FEATURES

• 9 L VHSTL outputs

• Selectable CLK, nCLK or L VPECL clock inputs

• CLK, nCLK pair can accept the following differential input

levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL

• Maximum output frequency up to 500MHz

• Output skew: 50ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Propagation delay: 1.8ns (maximum)

= 1.2V (maximum)

• V

OH

• 3.3V core, 1.8V output operating supply voltages

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM PIN ASSIGNMENT

CLK_EN

CLK

nCLK

PCLK

nPCLK

CLK_SEL

D

Q

LE

0
1

Q0
nQ0

Q1
nQ1

Q2
nQ2

Q3
nQ3

Q4
nQ4

Q5
nQ5

Q6
nQ6

Q7
nQ7

Q8
nQ8

VDD

CLK

nCLK

CLK_SEL

PCLK

nPCLK

GND

CLK_EN

7mm x 7mm x 1.4mm Package Body

V

DDO

Q0

32 31 30 29 28 27 26 25
1
2
3

4
5
6
7
8

9 10 11 12 13 14 15 16

nQ8

V

DDO

32-Lead LQFP

nQ1

nQ0

Q1

ICS8521

Q7

nQ7

Q8

Y Package

Top View

Q2

nQ6

nQ2

Q6

VDDO

VDDO

24

VDDO

23

Q3

22

nQ3

21

Q4

20

nQ4

19

Q5

18

nQ5

17

VDDO

8521BY www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001

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TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

1V
2KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
3KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI

4LES_KLCtupnInwodlluP

5KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
6KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
7DNGrewoP.dnuorgottcennoC.dnuorgylppusrewoP

8NE_KLCtupnIpulluP

,71,61,9

23,52,42

11,018Q,8QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
31,217Q,7QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
51,416Q,6QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
91,815Q,5QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD

12,024Q,4QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
32,223Q3QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
72,622Q,2QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD
92,821Q,1QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD

13,030Q,0QntuptuO.levelecafretniLTSHVL.riaptuptuolaitnereffiD

:ETON

pulluP

DD

V

ODD

dna

nwodlluP

rewoP.V3.3ottcennoC.nipylppusevitisoP

rewoP.V8.1ottcennoC.snipylppustuptuO

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

stceles,WOLnehW.KLCn,KLC

.slevelecafretniSOMCVL/LTTVL

wollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS

stuptuoQn,woldecroferastuptuoQ,WOLnehW.tupnikcolc

/SOMCVL.hgihdecroferaLTTVL.slevelecafretni

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleskcolC

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

,KLCn,KLC

C

NI

R

PULLUP

R

8521BY www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001

NWODLLUP

ecnaticapaCtupnI

rotsiseRpulluPtupnI 15KΩ

rotsiseRnwodlluPtupnI 15KΩ

KCLPn,KLCP

LES_KLC,NE_KLC4Fp

2

4Fp

Integrated
Circuit
Systems, Inc.

TABLE 3A. CONTROL INPUT FUNCTION TABLE

stupnIstuptuO

NE_KLCLES_KLCdecruoSdetceleS8Qurht0Q8Qnurht0Qn

00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD

10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE

.1erugiFninwohssa

.B3elbaTni

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA

debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQ0 - nQ8

Q0 - Q8

Disabled

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO

KLCProKLCKLCPnroKLCn8Qurht0Q8Qnurht0Qn

01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN

10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN

01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN

11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN

1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI

.sleveldedneelgnistpeccaottupni

Enabled

FIGURE 1: CLK_EN TIMING DIAGRAM

edoMtuptuOottupnIytiraloP

laitnereffidehtgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON

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LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

ICS8521

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V
Inputs, V

I

Outputs, V
Package Thermal Impedance, θ

Storage T emperature, T

DDx

O

JA

STG

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics

or

AC Characteristics

ods may affect product reliability.

4.6V

-0.5V to VDD + 0.5V

-0.5V to V

DDO

+ 0.5V

47.9°C/W

-65°C to 150°C

is not implied. Exposure to absolute maximum rating conditions for extended peri-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

DD

V

ODD

I

DD

TABLE 4B. LVCMOS DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HI

V

LI

I

HI

I

LI

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

I

HI

I

LI

V

PP

V

RMC

2,1ETON

egatloVylppuSevitisoP 531.33.3564.3V
egatloVylppuStuptuO 6.18.10.2V
tnerruCylppuSrewoP 0608Am

= 3.3V±5%, V

DD

LES_KLC,NE_KLC2567.3V
LES_KLC,NE_KLC3.0-8.0V

tnerruChgiHtupnI

tnerruCwoLtupnI

tnerruChgiHtupnI

tnerruCwoLtupnI

NE_KLCV

LES_KLCV

NE_KLCV

LES_KLCV

DD

KLCV

KLCnV

KLCV

KLCnV

egatloVtupnIkaeP-ot-kaeP51.03.1V

;egatloVtupnIedoMnommoC

VsadenifedsiegatlovedomnommoC:2ETON

= 3.3V±5%, V

DD

NI

NI

NI

NI

= 3.3V±5%, V

V=

NI

DD

V=

NI

DD

V,V0=

NI

NI

DD

V,V0=

DD

.

= 1.8V±0.2V, TA = 0°C TO 70°C

DDO

= 1.8V±0.2V, TA = 0°C TO 70°C

DDO

V=

DD

V=

DD

V,V0=
V,V0=

V564.3=5Aµ
V564.3=051Aµ

DD

DD

DDO

V564.3=051-Aµ
V564.3=5-Aµ

= 1.8V±0.2V , TA = 0°C TO 70°C

V564.3=051Aµ
V564.3=5Aµ

V564.3=5-Aµ
V564.3=051-Aµ

5.0V
VsiKLCndnaKLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON

DD

.V3.0+

58.0-V

DD

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ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

TABLE 4D. LVPECL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

I

HI

I

LI

V

PP

V

RMC

2,1ETON

tnerruChgiHtupnI

tnerruCwoLtupnI

KLCPV

KLCPnV

KLCPV

KLCPnV

egatloVtupnIkaeP-ot-kaeP 3.01V

;egatloVtupnIedoMnommoC

TABLE 4E. L VHSTL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HO

V

LO

V

XO

V

GNIWS

1ETON

1ETON

kaeP-ot-kaeP

;egatloVhgiHtuptuO

;egatloVwoLtuptuO

egatloVrevossorCtuptuO(x%04VHO-VLO+)V

gniwSegatloVtuptuO

05htiwdetanimretstuptuO:1ETON Ω .dnuorgot

= 3.3V±5%, V

DD

DD

DD

VsadenifedsiegatlovedomnommoC:1ETON

.

HI

= 3.3V±5%, V

DD

= 1.8V±0.2V , TA = 0°C TO 70°C

DDO

V=

DD

NI

V=

DD

NI

DDO

V564.3=051Aµ
V564.3=5Aµ

V,V564.3=

V0=5-Aµ

NI

V,V564.3=

V0=051-Aµ

NI

5.1V

VsiKLCPndnaKLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON

.V3.0+

= 1.8V±0.2V, TA = 0°C TO 70°C

DD

V

0.12.1V

04.0V
V(x%06

V-

LO

HO

V+)

LO

V

LO

6.01.1V

TABLE 5. AC CHARACTERISTICS, V

= 3.3V±5%, V

DD

= 1.8V±0.2V, TA = 0°C TO 70°C

DDO

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

f

XAM

t

DP

t

)o(ks4,2ETON;wekStuptuO 05sp

t

)pp(ks4,3ETON;wekStraP-ot-traP 052sp

t

R

t

F

emiTesiRtuptuOzHM05@%08ot%02003007sp

emiTllaFtuptuOzHM05@%08ot%02003007sp

ycneuqerFtuptuOmumixaM 005zHM

1ETON;yaleDnoitagaporP IJ zHM0521 8.1sn

cdoelcyCytuDtuptuO 8425%

.esiwrehtodetonsselnuzHM052taderusaemsretemarapllA

.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON

VmorfderusaeM

DD

.sleveltupnidedneelgnisroftniopgnissorclaitnereffidtuptuoehtot2/

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

.stniopssorclaitnreffidtuptuoehttaderusaeM

segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
drusaemeratuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna

.stniopssorclaitnereffidehtta

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

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PARAMETER MEASUREMENT INFORMATION

V

DD

LVHSTL

V

DD

V

DDO

V

DDO

= 3.3V ± 5%

= 1.8V ± 0.2V

GND = 0V

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

SCOPE

Qx

nQx

Qx

nQx

V

CLK, PCLK

nCLK, nPCLK

GND

FIGURE 2 - OUTPUT LOAD TEST CIRCUIT

DD

VPP

Cross Points

FIGURE 3 - DIFFERENTIAL INPUT LEVEL

V

CMR

Qy

nQy

tsk(o)

FIGURE 4 - OUTPUT SKEW

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Qx

PART 1

nQx

Qy

PART 2

nQy

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

tsk(pp)

FIGURE 5 - PART-TO-PART SKEW

ICS8521

LOW SKEW, 1-TO-9

Clock Inputs
and Outputs

CLK, PCLK

nCLK, nPCLK

Q0, Q8

nQ0, nQ8

80%

20%

t

R

t

F

FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME

t

PD

FIGURE 7 - PROPAGATION DELAY

80%

20%

V

SWING

CLK, PCLK

nCLK, nPCLK

Pulse Width

t

PERIOD

t

odc =

8521BY www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001

PW

t

PERIOD

FIGURE 8 - odc & t

7

PERIOD

Integrated
Circuit
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D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

ICS8521

LOW SKEW, 1-TO-9

Figure 9

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V

shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is

= 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.

DD

CLK_IN

C1

0.1uF

FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

R1
1K

V_REF

R2
1K

VDD

+

-

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D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

LOW SKEW, 1-TO-9

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8521.
Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8521 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

= 3.3V + 5% = 3.465V , which gives worst case results.

DD

ICS8521

• Power (core)

• Power (outputs)

If all outputs are loaded, the total power is 9 * 32mW = 288mW

Total Power

MAX

= V

MAX

_MAX

* I

DD_MAX

= 32mW/Loaded Output pair

= 3.465V * 80mA = 277.2mW

DD_MAX

(3.465V, with all outputs switching) = 277.2mW + 288mW = 565.2mW

2. Junction T emperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS

The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature

θ

= junction-to-ambient thermal resistance

JA

Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T

= Ambient T emperature

A

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.565W * 42.1°C/W = 93.8°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).

* Pd_total + T

JA

A

TM

devices is 125°C.

must be used . Assuming a

JA

Table 6. Thermal Resistance qJA for 32-pin LQFP, Forced Convection

q

by V elocity (Linear Feet per Minute)

JA

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

ICS8521

LOW SKEW, 1-TO-9

L VHSTL output driver circuit and termination are shown in

V

DD

Figure 10.

Q1

V

OUT

RL

Ω

50

FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V
Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low .

DD

- 2V .

Pd_H = (V
Pd_L = (V

OH_MAX /RL

OL_MAX /RL

• For logic high, V

• For logic low , V

) * (V

) * (V

DD_MAX

DD_MAX

OUT

= V

OUT

= V

- V

- V

OH_MAX

OL_MAX

OH_MAX

OL_MAX

= V

)

)

= V

DD_MAX

DD_MAX

– 1.2V

– 0.4V

Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW

T otal Power Dissipation per output pair = Pd_H + Pd_L = 32mW

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D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

RELIABILITY INFORMATION

ICS8521

LOW SKEW, 1-TO-9

TABLE 6. θ

TRANSISTOR COUNT

The transistor count for ICS8521 is: 944

VS

. AIR FLOW TABLE

JA

q

by V elocity (Linear Feet per Minute)

JA

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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PACKAGE OUTLINE - Y SUFFIX

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

TABLE 6. PACKAGE DIMENSIONS

LOBMYS

N
A

1A

2A
b
c
D

1D

2D
E

1E

2E
e
L

q

ccc

MUMINIMLANIMONMUMIXAM

----06.1

50.0--51.0

53.104.154.1

03.073.054.0

90.0--02.0

54.006.057.0

°

0

----01.0

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

ABB

23

CISAB00.9
CISAB00.7

.feR06.5

CISAB00.9
CISAB00.7

.feR06.5

CISAB08.0

--

7

°

Reference Document: JEDEC Publication 95, MS-026

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TABLE 7. ORDERING INFORMATION

rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT

YB1258SCIYB1258SCIPFQLdaeL23yartrep052C°07otC°0

TYB1258SCIYB1258SCIleeRdnaepaTnoPFQLdaeL230001C°07otC°0

ICS8521

LOW SKEW, 1-TO-9

D

IFFERENTIAL-TO-L VHSTL FANOUT BUFFER

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no
responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or
licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature
range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical
instruments.

8521BY www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001

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