Datasheet HS-565ARH-T Datasheet (Intersil Corporation)

Page 1

HS-565ARH-T

Data Sheet July 1999 File Number

Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter

Intersil’sSatellite Applications FlowTM(SAF) devices are fully tested and guaranteed to 100kRAD total dose. This QML Class T device is processed to a standard ﬂow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability.

The HS-565ARH-T is a fast, radiation hardened 12-bit current output, digital-to-analog converter. The monolithic chip includes a precision voltage reference, thin-ﬁlm R-2R ladder, reference control ampliﬁer and twelve high-speed bipolar current switches.

The Intersil Semiconductor Dielectric Isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to codedependent ground currents.

4607.1

Features

• qml Class T, Per MIL-PRF-38535

• Radiation Performance

- Gamma Dose (γ) 1 x 10

RAD(Si)

- No Latch-Up, Dielectrically Isolated Device Islands

• DAC and Reference on a Single Chip

• Pin Compatible with AD-565A and HI-565A

• Very High Speed: Settles to 0.50 LSB in 500ns Max

• Monotonicity Guaranteed Over Temperature

• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature

• Low Gain Drift (Max., DAC Plus Reference) 50ppm/

• ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at 25

Pinouts

HS1-565ARH-T (SBDIP), CDIP2-T24

TOP VIEW

HS-565ARH-T die are laser trimmed for a maximum integral nonlinearity error of ±0.25 LSB at 25

C. In addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient.

Speciﬁcations

Speciﬁcations for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the HS-565ARH-T are contained in SMD 5962-96755. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/ne wsafc lasst.asp

Intersil‘s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website.

www.intersil.com/quality/manuals.asp

Ordering Information

TEMP.

ORDERING

NUMBER

5962R9675501TJC HS1-565ARH-T -55 to 125 5962R9675501TXC HS9-565ARH-T -55 to 125

NOTE:

Minimumorderquantity for -T is 150 units through

distribution, or 450 units direct.

PART

NUMBER

RANGE

(oC)

BIPOLAR RIN

NC NC

REF OUT REF GND

REF IN

-V

BIPOLAR RIN

IDAC OUT 10V SPAN 20V SPAN

PWR GND

NC NC

REF OUT

REF GND

REF IN

-V

IDAC OUT 10V SPAN 20V SPAN PWR GND

1 2 3 4 5 6 7 8

9 10 11 12

BIT 1 IN (MSB)

BIT 2 IN

23 22

BIT 3 IN BIT 4 IN

BIT 5 IN

BIT 6 IN

BIT 7 IN

BIT 8 IN

BIT 9 IN

16 15

BIT 10 IN BIT 11 IN

14 13

BIT 12 IN (LSB)

HS9-565ARH-T (FLATPACK), CDFP4-F24

TOP VIEW

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

BIT 1 IN (MSB)

BIT 2 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 7 IN BIT 8 IN BIT 9 IN BIT 10 IN BIT 11 IN BIT 12 IN

(LSB)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

www.intersil.com or 407-727-9207

Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

Page 2

Functional Diagram

HS-565ARH-T

REF

GND

REF OUT V

19.95K

10V

3.5K

REF

0.5mA

-V

Deﬁnitions of Speciﬁcations

Digital Inputs

The HS-565ARH-T accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two’s Complement (see note below), or Offset Binary, (see Operating Instructions).

DIGITAL

INPUT

STRAIGHT

BINARY

000 . . . 000 Zero - fS (Full Scale) Zero 100 . . . 000 0.50 f 111 . . . 111 + fS - 1 LSB + fS - 1 LSB Zero - 1 LSB 011 . . . 111 0.50 fS- 1 LSB Zero - 1 LSB + fS - 1 LSB

NOTE: Invert MSB with external inverter to obtain Two’s

Complement Coding.

Accuracy

Nonlinearity - Nonlinearity of a D/A converter is an

important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON).

Differential Nonlinearity - For a D/A converter, it is the differencebetween the actual output voltagechange and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input.

Settling Time

Settling time is the time required for the output to settle to within the speciﬁed error band for any input code transition. It is usually speciﬁed for a full scale or major carry transition, settling to within 0.50 LSB of ﬁnal value.

Drift

Gain Drift - The change in full scale analog output over the

speciﬁed temperature range expressed in parts per million of

ANALOG OUTPUT

OFFSET BINARY

(NOTE)

TWO’S

COMPLEMENTMSB . LSB

Zero - f

712

PWR

GND

BIP.

9.95K

DAC

(4X IREF

X CODE)

24. . . 13

MSB LSB

OFF.

2.5K

20V SPAN

10V SPAN

OUT

full scale range peroC (ppm of FSR/oC). Gain error is measured with respect to 25 temperatures. Gain drift is calculated for both high (t

C) and low ranges (25oC - tL) by dividing the gain error

C at high (tH) and low (tL)

bythe respectivechange in temperature. The speciﬁcation is the larger of the two representing worst case drift.

Offset Drift - The change in analog output with all bits OFF over the speciﬁed temperature range expressed in parts per million of full scale range per error is measured with respect to 25 (t

) temperatures.Offset drift is calculated for both high (tD-

C) and low (25oC-tL) ranges by dividing the offset error

C (ppm of FSR/oC). Offset

C at high (tH) and low

by the respective change in temperature. The speciﬁcation given is the larger of the two, representing worst case drift.

Power Supply Sensitivity

Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V or +15V supplies. It is specified under DC conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of FSR/%).

Compliance

Compliance Voltage is the maximum output voltage range that can be tolerated and still maintain its speciﬁed accuracy. Compliance Limit implies functional operation only and makes no claims to accuracy.

Glitch

A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example, if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably.

Page 3

HS-565ARH-T

Applying the HS-565ARH-T

OP AMP Selection

The HS-565ARH-T’s current output may be converted to voltage using the standard connections shown in Figures 1 and 2. The choice of operational ampliﬁer should be reviewed for each application, since a signiﬁcant trade-off may be made between speed and accuracy. Remember settling time for the DAC-ampliﬁer combination is:

tD()2tA()

where t

, tA are settling times for the DAC and ampliﬁer.

100Ω

REF

GND

REF OUT

19.95 K

10V

0.5mA

3.5K

REF

HS-565ARH-T

No Trim Operation

The HS-565ARH-T will perform as speciﬁed without calibration adjustments. To operate without calibration, substitute 50Ω resistors for the 100Ω trimming potentiometers: In Figure 1 replace R2 with 50Ω; also remove the network on pin 8 and connect 50Ω to ground. For bipolar operation in Figure 2, replace R3 and R4 with 50Ω resistors.

With these changes, performance is guaranteed as shown under Speciﬁcations, “External Adjustments”. Typical unipolar zero will be ±0.50 LSB plus the op amp offset.

The feedback capacitor C must be selected to minimize settling time.

+15V

R1 50kΩ

-15V

+ R (SEE

TABLE 7)

9.95K

DAC

(4 x I x CODE)

CODE INPUT

BIP.

OFF.

REF

2.5K

100kΩ

100Ω

20V SPAN

10V SPAN

DAC OUT

100Ω

REF

GND

REF OUT

19.95K

-V

PWR GND

. . . . .

24 13

MSB LSB

FIGURE 1. UNIPOLAR VOLTAGE OUTPUT

-V

0.5mA

100Ω

HS-565ARH-T

REF

MSB LSB

PWR

GND

BIP.

OFF.

9.95K

DAC

(4 x I x CODE)

CODE

INPUT

. . . . .

24 13

REF

2.5K

10V

3.5K

FIGURE 2. BIPOLAR VOLTAGE OUTPUT

10V SPAN

DAC OUT

20V SPAN

+ R (SEE

TABLE 7)

Page 4

HS-565ARH-T

Calibration

Calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero, For the HS-565ARH-T, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. Refer to Table 7 for the voltage output case, along with Figure 1 or 2.

Calibration is a two step process for each of the ﬁve output ranges shown in Table 1. First adjust the negative full scale (zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e., affectseach code by the same amount.

Nextadjust positivef rotates the output characteristic about the negative f

For the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. In general, only two values of output may be calibrated exactly; all others must tolerate some error. Choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes.

. This is a gain error adjustment, which

value.

shown this to be a reliable and repeatable way to measure settling time.

The usual speciﬁcation is based on a 10V step, produced by simultaneously switching all bits from off-to-on (t to-off (t

). The slower of the two cases is speciﬁed, as

OFF

measured from 50% of the digital input transition to the ﬁnal entry within a window of ±0.50 LSB about the settled value. Four measurements characterize a given type of DAC:

(a) t (b) t (c) t

, to final value +0.50 LSB

, to final value -0.50 LSB

, to final value +0.50 LSB

OFF

(d) OFF, to final value -0.50 LSB

(Cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 LSB). For example, refer to Figures 3A and 3B for the measurement of case (d).

Procedure

As shown in Figure 3B, settling time equals tX plus the comparator delay (t

• Adjust the delay on generator number 2 for a tXof several

microseconds. This assures that the DAC output has

Settling Time

This is a challenging measurement, in which the result

settled to its ﬁnal wave

• Switch on the LSB (+5V)

depends on the method chosen, the precision and quality of test equipment and the operating conﬁguration of the DAC (test conditions). As a result, the different techniques in use by converter manufacturers can lead to consistently different results. An engineer should understand the advantage and limitations of a given test method before using the speciﬁed settling time as a basis for design.

The approach used for several years at Intersil calls for a strobed comparator to sense ﬁnal perturbations of the DAC output waveform. This gives the LSB a reasonable magnitude (814mV for the HS-565ARH-T, which provides the comparator with enough overdrive to establish an accurate ±0.50 LSB window about the ﬁnal settled value. Also, the required test conditions simulate the DACs environment for a common application - use in a successive approximation A/D converter. Considerable experience has

TABLE 1. OPERATING MODES AND CALIBRATION

CIRCUIT CONNECTIONS CALIBRATION

OUTPUT

MODE

Unipolar (See Figure 1) 0 to +10V VO Pin 10 1.43K All 0’s

RANGE

0 to +5V VO Pin 9 1.1K All 0’s

PIN 10

PIN 11

• Adjust the VLSB supply for 50% triggering at COMPARATOR OUT. This is indicated by traces of equal brightness on the oscilloscope display as shown in Figure 3B. Note DVM reading

• Switch to LSB to Pulse (P)

• Readjust the VLSB supply for 50% triggering as before, and note DVM reading. One LSB equals one tenth the difference in the DVM readings noted above

• Adjust the VLSB supply to reduce the DVM reading by 5 LSBs (DVM reads 10X, so this sets the comparator to sense the ﬁnal settled value minus 0.50 LSB). Comparator output disappears

• Reduce generator number 2 delayuntil comparator output reappears, and adjust for “equal brightness”

• Measure t time equals t

RESISTOR

(R)

from scope as shown in Figure 3B. Settling

+ tD, i.e., tX + 15ns

APPLY

INPUT CODE ADJUST TO SET VO

All 1’s

= 15ns). To measure tX:

R1 R2

) or on-

+9.99756V

+4.99878V

Page 5

HS-565ARH-T

TABLE 1. OPERATING MODES AND CALIBRATION (Continued)

CIRCUIT CONNECTIONS CALIBRATION

OUTPUT

MODE

RANGE

Bipolar (See Figure 2) ±10V NC VO 1.69K All 0’s

±5V VO Pin 10 1.43K All 0’s

±2.5V VO Pin 9 1.1K All 0’s

PIN 10

PIN 11

RESISTOR

(R)

APPLY

INPUT CODE ADJUST TO SET VO

All 1’s

R3 R4

-10V

+9.99512V

-5V

+4.99756V

-2.5V

+2.49878V

SYNC

TRIG OUT

2.5K

GENERATOR

20V ± 20%

BIAS 8 11

DVM

PULSE

NO. 2

TURN ON TURN OFF

OUT

STROBE IN

90 200K

COMPARATOR OUT

0.1µF

VLSB

SUPPLY

OUT

~100

kHz

PULSE

GENERATOR

NO. 2

HS-565ARH-T

24 23

. . . .

9.95K . . . . . . . . .

2mA

LSB

FIGURE 3A. FIGURE 3B.

Other Considerations

Grounds

The HS-565ARH-T has two ground terminals, pin 5 (REF GND) and pin 12 (PWR GND). These should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (If such a point exists, then separate paths are required to pins 5 and 12).

The current through pin 5 is near zero DC (Note); but pin 12 carries up to 1.75mA of code - dependent current from bits 1, 2, and 3. The general rule is to connect pin 5 directly to the system “quiet” point, usually called signal or analog ground. Connect pin 12 to the local digital or power ground. Then, of course, a single path must connect the analog/signal and digital/power grounds.

NOTE: Current cancellation is a two step process within the HS565ARH-Tin which code dependent variations are eliminated, theresulting DC current is supplied internally. First an auxiliary 9-bit R-2R ladderisdrivenbythecomplementofthe DACsinput code. Together,

+3V

-400mV

(TURN OFF)

0.8V

50%

-0.50LSB

SETTLING TIME tD = COMPARATOR DELAY

“EQUAL BRIGHTNESS”

DIGITAL INPUT

DAC OUTPUT

COMP. STROBE

COMP. OUT

the main and auxiliary ladders draw a continuous 2.25mA from the internal ground node,regardlessofinputcode.PartoftheDCcurrent is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5).

Layout

Connections to pin 9 (I critical for high speed performance. Output capacitance of the DAC is only 20pF, so a small change of additional capacitance may alter the op amp’s stability and affect settling time. Connections to pin 9 should be short and few. Component leads should be short on the side connecting to pin 9 (as for feedback capacitor C). See the Settling Time Section.

) on the HS-565ARH-T are most

OUT

Bypass Capacitors

Power supply bypass capacitors on the op amp will serve the HS-565ARH-T also.If no op amp is used, a 0.01mF ceramic capacitor from each supply terminal to pin 12 is sufﬁcient, since supply current variations are small.

Page 6

Die Characteristics

HS-565ARH-T

DIE DIMENSIONS:

(2718µm x 4547µm x 483µm ±25.4µm) 107 x 179 x 19mils ±1mil

METALLIZATION:

Type: Al Si Cu Thickness: 16.0k

Å ±2kÅ

SUBSTRATE POTENTIAL:

Tie substrate to reference ground

BACKSIDE FINISH:

Silicon

Metallization Mask Layout

REF

OUT

REF

GND

PASSIVATION:

Type: Silox (S Thickness: 8k

)

iO2

Å ±1kÅ

WORST CASE CURRENT DENSITY:

< 2.0e5 A/cm

TRANSISTOR COUNT:

200

PROCESS:

Bipolar, Dielectric Isolation

HS-565ARH-T

(MSB)

BIT 1 BIT 2

BIT 3

BIT 4

BIT 5

REF

-V

BIPOLAR

IDAC

OUT

10V

SPAN

20V

SPAN

POWER

GND

(LSB)

BIT 11BIT 12

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com