• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Radiation Hardened
- Functional Total Dose Exceeds 1 x 10
• Pin for Pin Compatible with Intersil HI-3XX Series
Analog Switches
• Analog Signal Range 15V
• Low Leakage
•Low R
• No Latch Up
• Versions for 5V and 15V Digital Systems
• Low Operating Power
• Military Temperature Range -55
ON
o
C to +125oC
5
RAD Si
Applications
• Sample and Hold i.e. Low Leakage Switching
• Op Amp Gain Switching i.e. Low ON Resistance
• Switched Capacitor Filters
• Low Level Switching Circuits
• Satellites
• Nuclear Reactor Controls
• Military Environments
Description
The HS-3XXRH/883S family of analog switches are
monolithic devices fabricated using Radiation Hardened
CMOS technology and the Intersil dielectric isolation process for latch-up free operation. Improved total dose hardness is obtained by layout (thin oxide tabs extending to a
channel stop) and processing (hardened gate oxide). These
switches offer low-resistance switching performance for analog voltages up to the supply rails. “ON” resistance is low
and stays reasonably constant over the full range of operating voltage and current. “ON” resistance also stays reasonably constant when exposed to radiation, being typically 30Ω
pre-rad and 35Ω post 100K RAD-Si. All devices provide
break-before-make switching.
The 6 devices in this switch series are differentiated by type
of switch action, pinout and digital logic levels. The HS-302/
303/384/390RH/883S switches have 5V digital inputs while
the HS-306/307RH/883S switches have 15V digital inputs.
All devices are available in Ceramic Flatpack and SBDIP
packages. The HS-3XXRH/883S switches can directly
replace the HI-3XX series devices.
Functional Diagram
IN
NP
D
Ordering Information
PART NUMBERTEMPERATURE RANGESCREENING LEVELPACKAGE
HS1-302RH/883S-55oC to +125oCIntersil /883 Class S Equivalent14 Lead SBDIP
HS9-302RH/883S-55oC to +125oCIntersil /883 Class S Equivalent14 Lead Ceramic Flatpack
HS1-302RH/Sample+25oCSample14 Lead SBDIP
HS9-302RH/Sample+25oCSample14 Lead Ceramic Flatpack
HS1-303RH/883S-55oC to +125oCIntersil /883 Class S Equivalent14 Lead SBDIP
HS9-303RH/883S-55oC to +125oCIntersil /883 Class S Equivalent14 Lead Ceramic Flatpack
HS1-303RH/Sample+25oCSample14 Lead SBDIP
HS9-303RH/Sample+25oCSample14 Lead Ceramic Flatpack
HS1-306RH/883S ( Note 1)-55oC to +125oCIntersil /883 Class S Equivalent14 Lead SBDIP
HS9-306RH/883S ( Note 1)-55oC to +125oCIntersil /883 Class S Equivalent14 Lead Ceramic Flatpack
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
CC2VA = 15V+25oC-10pF
Switch OutputCOSMeasured Drain to GND+25oC-28pF
Off IsolationVISOVGEN = 1Vp-p, f = 1MHz+25oC40-dB
CrosstalkVCRVGEN = 1Vp-p, f = 1MHz+25oC40-dB
Charge TransferVCTEVS = GND, CL = 0.01µF+25oC-15mV
NOTE:1. Parameterslisted in Table 3are controlled viadesignor processparametersand arenotdirectly tested atfinalproduction. These
parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by
characterization based upon data from multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. HS-302RH/303RH/384RH/390RH/883S DC POST 100K RAD (Si) ELECTRICAL CHARACTERISTICS
Tested Per Mil-Std-883. Unless Otherwise Specified: HS-302RH/303RH/384RH/390RH/883S V- = -15V, V+ = +15V, VAH = +4.0V, VAL = 0.8V
CONDITIONSTEMPERATURE
LIMITS
UNITSMINMAX
LIMITS
PARAMETERSYMBOLCONDITIONSTEMPERATURE
“Switch On” Resistance+RDSVD = 10V, IS = -10mA, S1/S2/S3/S4+25oC-60Ω
-RDSVD = -10V, IS = 10mA, S1/S2/S3/S4+25oC-60Ω
Leakage Current Into the
Source Terminal of an “Off”
Switch
LeakageCurrentinto theDrain
Terminal of an “Off” Switch
Leakage Current from an “On”
Driver Into the Switch(Drain&
Source)
Positive Supply CurrentI(+)All Channels VA = 0.8V+25oC-100µA
Negative Supply CurrentI(-)All Channels VA = 0.8V+25oC-100-µA
High Level Address CurrentIAHAll Channels High+25oC-1+1µA
Low Level Address CurrentIALAll Channels Low+25oC-1+1µA
Break-Before-Make Time
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 72hrs. min.,
NOTES:
1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
4. Data Package Contents:
o
+125
C min.
failures from subgroup 7.
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number.Data header includes lot number and date of test. (See Table6)
• Group B and D attributes and/or Generic data.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
WORST CASE CURRENT DENSITY: 1.732e05 A/cm
SUBSTRATE POTENTIAL: Unbiased
PROCESS: DI Linear Metal Gate CMOS
HS-302RH/303RH/306RH/307RH/883S
V+
S3
S4
2
S3
D3
D1
S1
IN1
NC
HS-384RH/390RH/883S
D3
D1
GND
D4
D2
S2
IN2
V-
S1
IN1
V-
S4
D4
D2
15
S2
GND
V+
IN2
Spec Number 518526
Page 16
HS-302RH/303RH/306RH/307RH/384RH/390RH/883S
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
16
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