Datasheet HM-6642-883 Datasheet (Intersil Corporation)

HM-6642/883

March 1997

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Low Power Standby and Operating Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns

• Wide Operating . . . . . . . . . . . . . . . . . . -55

o

C to +125oC

• Temperature Range

• Industry Standard Pinout

• Single 5.0V Supply

• CMOS/TTL Compatible Inputs

• Field Programmable

• Synchronous Operation

• On-Chip Address Latches

• Separate Output Enable

Ordering Information

PACKAGE TEMP. RANGE 120ns 200ns

SBDIP -55oC to +125oC HM1-

6642B/883

SLIM
SBDIP

CLCC -55oC to +125oC - HM4-

-55oC to +125oC HM6­6642B/883

HM1­6642/883

HM6­6642/883

6642/883

PKG.

NO.

D24.6

D24.3

J28.A

512 x 8 CMOS PROM

Description

The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.

On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642/883 in high speed pipelined architecture systems,
and also in synchronous logic replacement functions.

Applications for the HM-6642/883 CMOS PROM include low
power hand held microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchro­nous logic replacement.

All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.

Pinouts

M-6642/883 (BDIP)

TOP VIEW

A7

1

A6

2

A5

3

A4

4

A3

5

A2

6

A1

7

A0

8

Q0

9

Q1

10

Q2

11

GND

12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

24

V

CC

A8

23
22

G1

21

G2

20

G3

19

E
P

18
17

Q7
Q6

16

Q5

15

Q4

14
13

Q3

A4
A3
A2
A1
A0

10

NC

11

Q0

| Copyright © Intersil Corporation 1999

HM-6642/883 (CLCC)

A6

A5

3 2 14

5
6
7
8
9

Q1

Q2

TOP VIEW

NC

A7

14 15 16 17 1812 13

NC

GND

6-243

CC

A8

V

28 27 26

Q3Q5Q4

G1

25
24
23
22
21

20
19

G2
G3
E
P
NC

Q7
Q6

PIN DESCRIPTION

PIN DESCRIPTION

NC No Connect
A0-A8 Address Inputs
E Chip Enable
Q Data Output
V

CC

G1, G2, G3 Output Enable
P (Note) Program Enable

NOTE: P should be hardwired to GND

Power (+5V)

except during programming.

File Number 3013.1

Functional Diagram

HM-6642/883

A8
A7
A6
A5
A4

A3

A2
A1

A0

E

G1

G2

G3

LATCHED

ADDRESS

REGISTER

LATCHED

ADDRESS

REGISTER

A

6

GATED

ROW

A

DECODER

6

A

3

A

3

64

8 8

D

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

64 x 64

MATRIX

8 8

8 8

GATED COLUMN

DECODER

8-BIT DATA LATCH

ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:

A HIGH

DATA LATCHES:

8

8

L HIGH
Q LATCHES ON RISING EDGE OF

ADDRESS LATCHES AND GATED DECODERS:

LATCH ON FALLING EDGE OF
GATE ON FALLING EDGE OF

P SHOULD BE HARDWIRED TO GND EXCEPT

DURING PROGRAMMING

OUTPUT ACTIVE

Q = D

E

E

E

6-244

HM-6642/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V

Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4.5V

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 to VCC+0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTES 1, 4)

PARAMETER SYMBOL

CONDITIONS

Thermal Resistance (Typical) θ

SBDIP Package. . . . . . . . . . . . . . . . . . 52oC/W 14oC/W

Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70oC/W 19oC/W

CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 14oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC

JA

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 Gates

LIMITS

GROUP A

SUBGROUPS TEMPERATURE

θ

JC

UNITSMIN MAX

High Level Output
Voltage

Low Level Output
Voltage

High Impedance
Output Leakage
Current

Input Leakage
Current

Standby Supply
Current

Operating Supply
Current

Functional Test FT VCC = 4.5V (Note 5) 7, 8A, 8B -55oC ≤ TA≤ +125oC---

Device Guaranteed and 100% Tested

PARAMETER SYMBOL

VOH VCC = 4.5V,

IO = -1.0mA

VOL VCC = 4.5V,

IO = +3.2mA

IIOZ VCC = 5.5V, G = 5.5V,

VI/O = GND or VCC

II VCC = 5.5V, VI = GND or

VCC, P Not Tested

ICCSB VI = VCC or GND,

VCC = 5.5V, IO = 0mA

ICCOP VCC = 5.5V, G = GND,

G = VCC, (Note 3),
f = 1MHz,IO = 0mA,
VI = VCC or GND

TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

(NOTES 1, 2, 4)

CONDITIONS

1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V

1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC - 100 µA

1, 2, 3 -55oC ≤ TA≤ +125oC - 20 mA

GROUP A

SUB-

GROUPS TEMPERATURE

6642B/883

MIN MAX MIN MAX

HM-

LIMITS

HM-

6642/883

UNITS

Address Access Time TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 140 - 220 ns
Output Enable Access Time TGVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 50 - 150 ns
Chip Enable Access Time TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 120 - 200 ns
Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 20 - 20 - ns
Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 25 - 60 - ns
Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 120 - 200 - ns
Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 40 - 150 - ns

6-245

TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

Device Guaranteed and 100% Tested

HM-6642/883

LIMITS

PARAMETER SYMBOL

(NOTES 1, 2, 4)

CONDITIONS

GROUP A

SUB-

GROUPS TEMPERATURE

HM-

6642B/883

MIN MAX MIN MAX

HM-

6642/883

UNITS

Read Cycle Time TELEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 160 - 350 - ns

NOTES:

1. All voltages referenced to VSS.

2. A.C. measurements assume transition time < 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equiv­alent load and CL ≅ 50pF.

3. Typical derating = 5mA/MHz increase in ICCOP.

4. All tests performed with P hardwired to GND.

5. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V.

TABLE 3. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD SUBGROUPS

Initial Test 100%/5004 ­Interim Test 100%/5004 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 7, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9

Switching Waveform

TAVEL

A

TEHEL

E

Q

TGXQZ

G

(NOTE)

TIME

REFERENCE

NOTE: G has the same timing as G except signal is inverted.

ADD VALID

-1 0 1 2 3 456

FIGURE 1. READ CYCLE

TAVQV

TELAX

TELQV

TGVQX

TGVQV

TELEH

TAVEL

NEXT ADD

TELEL

TEHEL

DATA VALID

TGXQZ

6-246

Test Load Circuit

Burn-In Circuits

HM-6642/883 (0.300 INCH) SBDIP HM-6642/883 (0.600 INCH) SBDIP

DUT

CL

(NOTE)

NOTE:
TEST HEAD
CAPACITANCE,
INCLUDES STRAY
AND JIG CAPACITANCE

HM-6642/883

EQUIVALENT CIRCUIT

FIGURE 2. TEST LOAD CIRCUIT

1.5V IOLIOH

±

F8
F7
F6
F5
F4

F3
F2
F1

VCC / 2

2.4K

2.4K

2.4K

VCC

2.4K

2.4K

2.4K

2.4K

2.4K

C

F9
F10
F11
F12
F0
GND

VCC / 2

F10

F9
F8
F7
F6
F5
F4
F3

VCC / 2

1

A7

2

A6

3

A5

4

A4

5

A3

6

A2

7

A1

8

A0

9

Q0

10

Q1

11

Q2

12

GND

VCC

A8
G1
G2
G3

Q7
Q6
Q5
Q4
Q3

24
23
22
21
20
19

E

18

P

17
16
15
14
13

A7

1

A6

2

A5

3

A4

4

A3

5

A2

6

A1

7

A0

8

Q0

9

Q1

10

Q2

11

GND

12

VCC

A8
G1
G2
G3

Q7
Q6
Q5
Q4
Q3

24
23
22
21
20
19

E

18

P

17
16
15
14
13

C

VCC
F9
F10

F11
F12
F0
GND

VCC / 2

6-247

HM-6642/883

Burn-In Circuits

(Continued)

F5
F4

F3
F2

F1

VCC

1.5K

1.5K

1.5K

NC

HM-6642/883 CLCC

F6

F7

F8

C

NC

3 2

4 28 27 26
5
6

7
8
9

10
11

1

14 15 16 17 1812 13

NC

VCC

F9

F10

25
24
23
22

NC

21
20
19

F11
F12
F0

820

820

820

NOTES:

1. F0 = 100kHz ± 10%.

2. All Resistors = 47kΩ.

3. Unless Otherwise Noted.

4. VCC = 5.5V ± 0.5V.

5. VIL = 4.5V ± 10%.

6. C = 0.01µF Min.

1.5K

1.5K

1.5K

1.5K

1.5K

R1

820

820

820

820

820

R2

6-248

Die Characteristics

HM-6642/883

DIE DIMENSIONS:

136 x 168 x 19 ± 1mils

METALLIZATION:

Type: Si - Al
Thickness: 11k

Å ±15kÅ

Metallization Mask Layout

A3
A2

GLASSIVATION:

Type: SiO

2

Thickness: 8kű 1kÅ

WORST CASE CURRENT DENSITY:

1.7 x 10

HM-6642/883

A4 A5 A6 A7 VCC A8 G1 G2

5

A/cm

2

G3
E

P

A1
A0

Q0 Q1 Q2 GND Q3 Q4 Q5 Q6

Q7

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed b y Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

6-249