Datasheet HM-6551 Datasheet (Intersil Corporation)

HM-6551

March 1997

Features

• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max

• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min

• TTL Compatible Input/Output

• High Output Drive - 1 TTL Load

• Internal Latched Chip Select

• High Noise Immunity

• On-Chip Address Register

• Latched Outputs

• Three-State Output

Ordering Information

PACKAGE TEMPERA TURE RANGE 220ns 300ns PKG. NO.

Plastic DIP -40oC to +85oC
CERDIP -40oC to +85oC HM1-6551B-9 HM1-6551-9 F22.4

Pinout

256 x 4 CMOS RAM

Description

The HM-6551 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation.

On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.

The HM-6551 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention
supply voltage and supply current are guaranteed over­temperature.

HM3-6551B-9 HM3-6551-9 E22.4

HM-6551

(PDIP, CERDIP)

TOP VIEW

A3

1
2

A2
A1

3
4

A0
A5

5

A6

6

A7

7
8

GND

D0

9

10

Q0
D1

11

PIN DESCRIPTION

A Address Input
E Chip Enable

W Write E5able

S Chip Select
D Data Input
Q Data Output

V

22

CC

A4

21

W

20

S1

19

E

18

S2

17

Q3

16

D3

15

Q2

14
13

D2
Q1

12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-1

File Number 2989.1

Functional Diagram

HM-6551

A0
A1
A5
A6
A7

D0

D1

D2

D3

S2

S1

LATCHED

ADDRESS

REGISTER

A

A

A

A

E

W

A

5

GATED

ROW

DECODER

A

5

L

DQ

SELECT

LATCH

32

32 x 32

MATRIX

GATED COLUMN

DECODER

AND DATA I/O

33

A A

LATCHED ADDRESS

REGISTER

A2

A3

8 888

D

D

OUTPUT

D

LATCHES

D

A4

NOTES:

1. Select Latch: L Low → Q = D and Q latches on rising edge of L.

2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.

3. All lines positive logic-active high.

4. Three-State Buffers: A high → output active.

5. Data Latches: L High → Q = D and Q latches on falling edge of L.

DAT A

Q

Q

Q

Q

L

Q0

A

Q1

A

Q2

A

Q3

A

6-2

HM-6551

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC+0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

HM-6551B-9, HM-6551-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θ

CERDIP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W

Plastic DIP Package . . . . . . . . . . . . . . 75oC/W N/A

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

JA

θ

JC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1930 Gates

DC Electrical Specifications V

SYMBOL PARAMETER

ICCSB Standby Supply Current - 10 µA IO = 0mA, VI = VCC or GND,

ICCOP Operating Supply Current (Note 1) - 4 mA E = 1MHz, IO = 0mA, VCC = 5.5V,

ICCDR Data Retention Supply Current - 10 µAVCC = 2.0V, IO = 0mA, VI = VCC or

VCCDR Data Retention Supply Voltage 2.0 - V

II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V

IOZ Output Leakage Current -1.0 +1.0 µA VO = VCC or GND, VCC = 5.5V

VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V

VIH Input High Voltage VCC -2.0 VCC +0.3 V VCC = 5.5V

VOL Output Low Voltage - 0.4 V IO = 1.6mA, VCC = 4.5V

VOH Output High Voltage 2.4 - V IO = -0.4mA, VCC = 4.5V

Capacitance T

SYMBOL PARAMETER MAX UNITS TEST CONDITIONS

= +25oC

A

= 5V ±10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9)

CC

LIMITS

UNITS TEST CONDITIONSMIN MAX

VCC = 5.5V

VI = VCC or GND, W = GND

GND, E = V

CC

CI Input Capacitance (Note 2) 6 pF f = 1MHz, All measurements are

CO Output Capacitance (Note 2) 10 pF

NOTES:

1. Typical derating 1.5mA/MHz increase in ICCOP.

2. Tested at initial design and after major design changes.

referenced to device GND

6-3

HM-6551

AC Electrical Specifications V

SYMBOL PARAMETER

(1)

TELQV Chip Enable Access Time - 220 - 300 ns (Notes 1, 3)

(2)

TAVQV Address Access Time - 220 - 300 ns (Notes 1, 3, 4)

(3)

TS1LQX Chip Select 1 Output Enable Time 5 130 5 150 ns (Notes 2, 3)

(4)

TWLQZ Write Enable Output Disable Time - 130 - 150 ns (Notes 2, 3)

(5)

TS1HQZ Chip Select 1 Output Disable Time - 130 - 150 ns (Notes 2, 3)

(6)

TELEH Chip Enable Pulse Negative Width 220 - 300 - ns (Notes 1, 3)

(7)

TEHEL Chip Enable Pulse Positive Width 100 - 100 - ns (Notes 1, 3)

(8)

TAVEL Address Setup Time 0 - 0 - ns (Notes 1, 3)

(9)

TS2LEL Chip Select 2 Output Disable Time 0 - 0 - ns (Notes 1, 3)

(10)

TELAX Address Hold Time 40 - 50 - ns (Notes 1, 3)

(11)

TELS2X Chip Select 2 Hold Time 40 - 50 (Notes 1, 3)

= 5V ±10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9)

CC

LIMITS

HM-6551B-9 HM-6551-9

MIN MAX MIN MAX

UNITS

TEST

CONDITIONS

(12)

TDVWH Data Setup Time 100 - 150 - ns (Notes 1, 3)

(13)

TWHDX Data Hold Time 0 - 0 - ns (Notes 1, 3)

(14)

TWLS1H Chip Select 1 Write Pulse Setup Time 120 - 180 - ns (Notes 1, 3)

(15)

TWLEH Chip Enable Write Pulse Setup Time 120 - 180 - ns (Notes 1, 3)

(16)

TS1LWH Chip Select 1 Write Pulse Hold Time 120 - 180 - ns (Notes 1, 3)

(17)

TELWH Chip Enable Write Pulse Hold Time 120 - 180 - ns (Notes 1, 3)

(18)

TWLWH Write Enable Pulse Width 120 - 180 - ns (Notes 1, 3)

(19)

TELEL Read or Write Cycle Time 320 - 400 - ns (Notes 1, 3)

NOTES:

1. Input pulse levels: 0.8V to VCC- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. VCC = 4.5V and 5.5V.

4. TAVQV = TELQV + TAVEL.

6-4

Timing Waveforms

(8) TAVEL

(10)

TELAX

HM-6551

(8) TAVEL

TIME

REFERENCE

TIME

REFERENCE

S2

S1

A

TEHEL

(7)

E

(9)

TS2LEL

D

Q

W

HIGH

-1

VALID

(19) TELEL

TELEH (6) TELEL (7)

TELS2X

(11)

TELQV (1)

TAVQV (2)

VALID OUTPUT

(3) TS1LQX

012345

(9)

TS2LEL

NEXT

TS1HQZ (5)

FIGURE 1. READ CYCLE

TRUTH TABLE

INPUTS OUTPUTS

FUNCTIONE S1 S2 WAD Q

-1 HHXXXX ZMemory Disabled
0 X L H V X Z Addresses and S2 are Latched,

1 L L X H X X X Output Enabled but Undefined
2 L L X H X X V Data Output Valid
3 L X H X X V Outputs Latched, Valid Data,

4 HHXXXX ZPrepare for Next Cycle

5 X L H V X Z Cycle Ends, Next Cycle Begins

The HM-6551 Read Cycle is initiated by the falling edge ofE.
This signal latches the input address word and

S2 into on
chip registers, providing the minimum setup and hold times
are met. After the required hold time, these inputs may
change state without affecting device operation.

S2 acts as a
high order address and simplifies decoding. For the output to
be read,
have been latched low on the falling edge of

E, S1 must be low and W must be high. S2 must

E. The output

Cycle Begins

S2 Unlatches

(Same as -1)

(Same as 0)

data will be valid at access time (TELQV). The HM-6551 has
output data latches that are controlled by
edge of
state until

E the present data is latched and remains in that

E falls. Also on the rising edge of E, S2 unlatches

and controls the outputs along with

E. On the rising

S1. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.

6-5

HM-6551

Timing Waveforms

A

E

S2

D

W

S1

TIME

REFERENCE

(Continued)

(8) TAVEL

TEHEL (7)

(9) TS2LEL

-1

(10)

TELAX

VALID

TELEL (19)

TELEH (6)

TELS2X

(11)

DATA VALID

TWLEH (15)

TELWH (17)

TDVWH (12)

TWLWH (18)

TS1LWH (16)

TWLS1H (14)

01 23 45

(8) TAVEL

NEXT

TEHEL (7)

(9) TS2LEL

TWHDX (13)

FIGURE 2. WRITE CYCLE

TRUTH TABLE

TIME

REFERENCE

-1 HHXXXX ZMemory Disabled
0 X L X V X Z Cycle Begins, Addresses and S2 are

1 L L X X X Z Write Period Begins
2 L L X X V Z Data In is Written
3 X X H X X Z Write is Completed
4 HHXXXX ZPrepare for Next Cycle (Same as -1)
5 X L X V X Z Cycle Ends, Next Cycle Begins

INPUTS OUTPUTS

In the Write Cycle the falling edge of E latches the
addresses and

S2 into on chip registers. S2 must be latched
in the low state to enable the device. The write portion of the
cycle is defined as
simultaneously. The

E, W, S1 being low and S2 being latched

W line may go low at any time during
the cycle, providing that the write pulse setup times (TWLEH
and TWLS1H) are met. The write portion of the cycle is ter­minated on the first rising edge of either

E, W, or S1.

If a series of consecutive write cycles are to be executed, the
W line may be held low until all desired locations have been
written. If this method is used, data setup and hold times
must be referenced to the first rising edge of

E or S1. By

FUNCTIONE S1 S2 WAD Q

Latched

(Same as 0)

positioning the write pulse at different times within the

E and
S1 low time (TELEH), various types of write cycles may be
performed. If the

S1 low time (TS1LS1H) is greater than the
W pulse plus an output enable time (TS1LQX), a combina­tion read-write cycle is executed. Data may be modified an
indefinite number of times during any write cycle (TELEH).

The HM-6551 may be used on a common I/O bus structure
by tying the input and output pins together. The multiplexing
is accomplished internally by the
when

W goes low, the output buffers are forced to a high

W line. In the write cycle,

impedance state. One output disable time delay (TWLQZ)
must be allowed before applying input data to the bus.

6-6

Test Load Circuit

HM-6551

DUT

(NOTE 1) C

NOTE:

1. Test head capacitance includes stray and jig capacitance.

L

+

1.5V IOLIOH

-

EQUIVALENT CIRCUIT

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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