Datasheet HM-65262-883 Datasheet (Intersil Corporation)

March 1997

HM-65262/883

16K x 1 Asynchronous

CMOS Static RAM

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max

• Low Standby Current. . . . . . . . . . . . . . . . . . . .50

• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max

• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max

• TTL Compatible Inputs and Outputs

µA Max

Description

The HM-65262/883 is a CMOS 16384 x 1-bit Static Ran­dom Access Memory manufactured using the Intersil
Advanced SAJI V process. The device utilizes asynchro­nous circuit design for fast cycle times and ease of use.
The HM-65262/883 is available in both JEDEC Standard 20
pin, 0.300 inch wide CERDIP and 20 pad CLCC packages,
providing high board-level packing density. Gated inputs
lower standby current, and also eliminate the need for pull­up or pull-down resistors.

The HM-65262/883, a full CMOS RAM, utilizes an array of
six transistor (6T) memory cells for the most stable and

• JEDEC Approved Pinout

• No Clocks or Strobes Required

o

• Temperature Range. . . . . . . . . . . . . . . +55

C to +125oC

• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required

lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of
the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of
four transistor (4T) devices.

• Equal Cycle and Access Time

• Single 5V Supply

Ordering Information

70ns/20µA 85ns/20µA 85ns/400µA TEMP. RANGE PACKAGE PKG. NO.

- HM1-65262/883 - -55oC to +125oC CERDIP F20.3

HM4-65262B/883 HM4-65262/883 - -55oC to +125oC CLCC J20.C

Pinouts

HM1-65262/883 (CERDIP)

TOP VIEW

1

A0
A1

2

A2

3

A3

4

A4

5

A5

6

A6

7
8

Q

9

W

10

GND

VCC

20

A13

19

A12

18

A11

17

A10

16

A9

15

A8

14

A7

13
12

D

11

E

HM-65262 (CLCC)

TOP VIEW

A1A2VCC

220119

3

A3

4

A4

5

A5

6

A6

7

Q

8

9101112

W

A0

GND

A13

18

A12
A11

17

A10

16

A9

15

A8

14

A7

13

E

D

A0 - A13 Address Input

E Chip Enable/Power Down
Q Data Out
D Data In

VSS/GND Ground

VCC Power (+5)

W Write Enable

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-204

File Number 3003.2

Functional Diagram

HM-65262/883

A0
A1
A2
A3
A4

A12
A13

A

ROW

ADDRESS

BUFFER

D

E

W

7

DECODER
(1 OF 128)

A

7

ROW

MEMORY ARRAY

128

128 X 128

128

COLUMN DECODER

(1 OF 128)

AND I / O CIRCUITRY

A

A

7

COLUMN

ADDRESS BUFFERS

A7A6A8

A9

A10

A11

Q

7

A5

6-205

HM-65262/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input or Output Voltage Applied for all Grades . . . . . -0.3V to VCC +0.3V

Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Thermal Resistance (Typical) θ

CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W

CLCC Package. . . . . . . . . . . . . . . . . . . . 75

Maximum Storage Temperature Range. . . . . . . . . . . . .-65

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300

JA

o

C/W 18oC/W

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . . . . .±2.2V to VCC

Data Retention Supply Voltage. . . . . . . . . . . . . . . . . . . 2.0V to 4.5V

Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max.

θ

JC

o

C to +150oC

o
o

C
C

Device Guaranteed and 100% Tested

DC PARAMETER SYMBOL

High Level Output Voltage VOH1 VCC = 4.5V, IO = -4.0mA 1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
Low Level Output Voltage VOL VCC = 4.5V, IO = 8.0mA 1, 2, 3 -55
High Impedance Output

Leakage Current
Input Leakage Current II VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
Standby Supply Current ICCSB1 VCC = 5.5V, IO = 0mA,

Standby Supply Current ICCSB VCC = 5.5V, IO = 0mA, E = 2.2V 1, 2, 3 -55oC ≤ TA≤ +125oC- 5 mA
Operating Supply

Current
Data Retention Supply

Current
Enable Supply Current ICCEN VCC = 5.5V, IO = 0mA, E = 0.8V 1, 2, 3 -55oC ≤ TA≤ +125oC - 50 mA
Functional Test FT VCC = 4.5V (Note 3) 7, 8A, 8B -55

IOZ VCC = 5.5V,

or VCC

-0.3V

ICCOP VCC = 5.5V, (Note 2), f = 1MHz,

= 0.8V

ICCDR VCC = 2.0V, IO = 0mA,E = VCC

-0.3V

(NOTE 1)

CONDITIONS

E = 5.5V, VO = GND

E = VCC

GROUP A

SUB-GROUPS TEMPERATURE MIN MAX UNITS

o

C ≤ TA≤ +125oC - 0.4 V

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC- 50 µA

E

1, 2, 3 -55oC ≤ TA≤ +125oC - 50 mA

1, 2, 3 -55oC ≤ TA≤ +125oC- 20 µA

o

C ≤ TA≤ +125oC- - -

NOTES:

1. All voltages referenced to device GND.

2. Typical derating 1.5mA/MHz increase in ICCOP.

3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V.

TABLE 1. HM-65262/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

AC PARAMETER SYMBOL

TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

Read/Write/Cycle
Time

Address Access
Time

(1) TAVAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 70 - 85 - ns

(2) TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 70 - 85 ns

(NOTES 1, 2)

CONDITIONS

GROUP A

SUB-

GROUPS TEMPERATURE

6-206

HM-

65262B/883

LIMITS

HM-65262/883

LIMITS

UNITSMIN MAX MIN MAX

HM-65262/883

Device Guaranteed and 100% Tested

HM-

TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

GROUP A

(NOTES 1, 2)

AC PARAMETER SYMBOL

Chip Enable to End
of Write

Chip Enable Access
Time

Address Hold Time (5) TWHAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC0 - 0 - ns
Address Setup Time (6) TAVWL VCC = 4.5V and 5.5V 9, 10, 11 -55
Address Valid to

End of Write
Address Setup Time (8) TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC0 - 0 - ns
Address Hold Time (9) TEHAX VCC = 4.5V and 5.5V 9, 10, 11 -55
Address Valid to

End of Writes
Write Enable Pulse

Write
Data Setup Time (12) TDVWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 30 - 35 - ns
Data Hold Time (13) TWHDX VCC = 4.5V and 5.5V 9, 10, 11 -55
Enable Pulse Width (14) TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55
Write to End of

Write

(3) TELWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 55 - 65 - ns

(4) TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 70 - 85 ns

(7) TAVWH VCC = 4.5V and 5.5V 9, 10, 11 -55

(10) TAVEH VCC = 4.5V and 5.5V 9, 10, 11 -55

(11) TWLWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 40 - 45 - ns

(15) TWLEH VCC = 4.5V and 5.5V 9, 10, 11 -55

CONDITIONS

SUB-

GROUPS TEMPERATURE

o

C ≤ TA≤ +125oC0 - 0 - ns

o

C ≤ TA≤ +125oC 55 - 65 - ns

o

C ≤ TA≤ +125oC0 - 0 - ns

o

C ≤ TA≤ +125oC 55 - 65 - ns

o

C ≤ TA≤ +125oC0 - 0 - ns

o

C ≤ TA≤ +125oC 55 - 65 - ns

o

C ≤ TA≤ +125oC 40 - 45 - ns

LIMITS

65262B/883

HM-65262/883

LIMITS

UNITSMIN MAX MIN MAX

Data Setup Time (16) TDVEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 30 - 35 - ns
Data Hold Time (17) TEHDX VCC = 4.5V and 5.5V 9, 10, 11 -55

o

C ≤ TA≤ +125oC0 - 0 - ns

NOTES:

1. All voltages referenced to device GND.

2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1
TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

3. TAVQV = TELQV + TAVEL.

TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC

LIMITS

UNITSMIN MAX

PARAMETER SYMBOL

Input Capacitance

Output Capacitance

CIN

CO

(NOTE 1)

CONDITIONS NOTES TEMPERATURE

VCC = Open, f = 1MHz, All
Measurements Refer­enced To Device Grounds

VCC = Open, f = 1MHz, All
Measurements Refer­enced To Device Grounds

VCC = Open, f = 1MHz, All
Measurements Refer­enced To Device Grounds

VCC = Open, f = 1MHz, All
Measurements Refer­enced To Device Grounds

1, 2 T

1, 3 T

1, 2 T

1, 3 T

= +25oC - 10 pF

A

= +25oC-6pF

A

= +25oC - 12 pF

A

= +25oC-8pF

A

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HM-65262/883

TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC (Continued)

PARAMETER SYMBOL

(NOTE 1)

CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Write Enable to Output in High Z

(18)

VCC = 4.5V and 5.5V 1 -55oC ≤ TA≤ +125oC - 40 ns

TWLQZ

Write Enable High to Output ON

(19)

VCC = 4.5V and 5.5V 1 -55oC ≤ TA≤ +125oC0 -ns

TWHQX

Chip Enable to Output ON

(20)

VCC = 4.5V and 5.5V 1 -55oC ≤ TA≤ +125oC5 -ns

TELQX

Output Enable High to Output in
High Z

Chip Disable to Output Hold Time

(21) TE-

HQZ

(22) TE-

VCC = 4.5V and 5.5V 1 -55oC ≤ TA≤ +125oC - 40 ns

VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤+125oC5 -ns

HQX

Address Invalid Output Hold Time

(23) TAX-

VCC = 4.5V and 5.5V 1 -55oC ≤ TA≤ +125oC5 -ns

QX

High Level Output Voltage

(24) VOH2

VCC = 4.5V, IO = -100mA 1 -55oC≤TA≤+125oC- VCC -0.4V - V

NOTES:

1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.

2. Applies to DIP device types only.

3. Applies to LCC device types only.

TABLE 4. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD SUBGROUPS

Initial Test 100%/5004 ­Interim Test 100%/5004 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9

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Timing Waveforms

A

HM-65262/883

E

(20) TELQX

Q

(4) TELQV

(21) TEHQZ

(22) TEHQX

NOTE:

1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high.

FIGURE 1. READ CYCLE 1: CONTROLLED BY E

(1) TAVAX

A

(2) TAVQV

E

(20) TELQX

Q

(21) TEHQZ

(23) TAXQX

NOTE:

1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid.

FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS

(1) TAVAX

A

(7) TAVWH

E

(6)

TAVWL

W

D

(20)

TELQX

Q

(3) TELWH

(11) TWLWH

(12) TDVWH

(18) TWLQZ

(5) TWHAX

(13) TWHDX

(19) TWHQX

NOTE:

1. In this mode, E rises after W. The address must remain stable whenever both E and W are low.

FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)

(21) TEHQZ

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HM-65262/883

Timing Waveforms

A

E

W

D

Q

(Continued)

(8) TAVEL

(1) TAVAX

(10) TAVEH

(14) TELEH

(15) TWLEH

(16) TDVEH

(20) TELQX

(18) TWLQZ (21) TEHQZ

(9) TEHAX

(17)

TEHDX

(19) TWHQX

NOTE:

1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.

FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)

Low Voltage Data Retention

Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran­teed over temperature. The following rules ensure data
retention:

1. Chip Enable (

E) must be held high during data retention;

within VCC to VCC +0.3V.

DATA RETENTION

VCC

4.5V

E

VCC ≥ 2.0V

VCC -0.3V TO VCC +0.3V

2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.

3. Inputs which are to be held high (e.g.,

E) must be kept
between VCC +0.3V and 70% of VCC during the power
up and down transitions.

4. The RAM can begin operation >55ns after VCC reaches
the minimum operating voltage (4.5V).

MODE

4.5V

>55ns

FIGURE 5. DATA RETENTION TIMING

6-210

Test Circuit

DUT

(NOTE 1) CL

NOTE:

1. Test head capacitance includes stray and jig capacitance.

Burn-In Circuits

HM-65262/883

CERDIP

TOP VIEW

HM-65262/883

EQUIVALENT CIRCUIT

+

1.5V IOLIOH

-

HM-65262/883

CLCC

TOP VIEW

F3
F4
F5
F6
F7
F8
F9
F2
F1

A0
A1
A2
A3
A4
A5
A6

GND

1
2
3
4
5
6
7

Q

8

W

9

10

VCC

20

A13

19

A12

18

A11

17

A10

16

A9

15

A8

14

A7

13

D

12

E

11

F16
F15
F14
F13
F12
F11
F10
F2
F0

NOTES:
All resistors 47kΩ±5%.

F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C = 0.01µF Min.

VCC

C

A12

18

A11

17

A10

16

A9

15

A8

14

A7

13

VCC

E

F16

A13

D

F0

F2

F0

F4

A0

A1

220119

F5
F6
F7
F8
F9
F2

A2
A3
A4
A5

A6

3
4
5
6
7

Q

8

9101112

W

GND

F1

NOTES:
All resistors 47kΩ±5%.

F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C = 0.01µF Min.

F15
F14
F13
F12
F11
F10

6-211

Die Characteristics

HM-65262/883

DIE DIMENSIONS:

148 x 187 x 19 mils

METALLIZATION:

Type: Si - Al
Thickness: 11k

Å ±2kÅ

Metallization Mask Layout

A2 A1 A0 VCC A13 A12

A3

A4

GLASSIVATION:

Type: SiO
Thickness: 8kű1kÅ

WORST CASE CURRENT DENSITY:

1.2 x 10

HM-65262/883

2

5

A/cm

2

A11

A10

A5

A6

EGNDWQ

A7D

A9

A8

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Cor poration reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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