Datasheet HM-6518 Datasheet (Intersil Corporation)

HM-6518

March 1997

Features

• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max

• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min

• TTL Compatible Input/Output

• High Output Drive - 2 TTL Loads

• High Noise Immunity

• On-Chip Address Register

• Two-Chip Selects for Easy Array Expansion

• Three-State Output

Ordering Information

PACKAGE TEMP. RANGE 180ns 250ns PKG. NO.

CERDIP -40oC to +85oC HM1-

6518B-9

HM1­6518-9

F18.3

1024 x 1 CMOS RAM

Description

The HM-6518 is a 1024 x 1 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation.

On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.

The HM-6518 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention
supply voltage and supply current are guaranteed over­temperature.

Pinout

HM-6518

(CERDIP)

TOP VIEW

1

S1

2

E

A0

3
4

A1
A2

5

A3

6

A4

7

Q

8

GND

9

PIN DESCRIPTION

A Address Input
E Chip Enable

W Write Enable

S Chip Select
D Data Input
Q Data Output

18

V

CC

17

S2

16

D

15

W

14

A9

13

A8

12

A7
A6

11

A5

10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-1

File Number 2987.1

Functional Diagram

HM-6518

A5
A6
A7
A8
A9

S1,
S2

LATCHED
ADDRESS

REGISTER

D

W

E

A

5

A

5

GATED

ROW

DECODER

G

A

32 x 32

32

MATRIX

GATED COLUMN

DECODER

AND DATA I/O

55

AA

LATCHED ADDRESS

REGISTER

32

NOTES:

1. All lines positive logic - active high.

2. Three-state buffers: A high → output active.

3. Data latches: L high → Q = D; Q Latches on rising edge of L.

4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.

D

LATCH

A4A3A2A1A0

Q

L

Q

A

6-2

HM-6518

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC+0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

HM-6518B-9, HM-6518-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θ

CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

JA

θ

JC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1936 Gates

DC Electrical Specifications V

PARAMETER SYMBOL

Standby Supply Current ICCSB - 10 µA IO = 0mA, VI = VCC or GND,

Operating Supply
Current (Note 1)

Data Retention Supply
Current

Data Retention Supply Voltage VCCDR 2.0 - V
Input Leakage Current II -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V
Output Leakage Current IOZ -1.0 +1.0 µA VO = VCC or GND, VCC = 5.5V
Input Low Voltage VIL -0.3 0.8 V VCC = 4.5V
Input High Voltage VIH VCC -2.0 VCC +0.3 V VCC = 5.5V
Output Low Voltage VOL - 0.4 V IO = 3.2mA, VCC = 4.5V
Output High Voltage VOH 2.4 - V IO = -0.4mA, VCC = 4.5V

Capacitance T

A

PARAMETER SYMBOL MAX UNITS TEST CONDITIONS

HM-6518B-9 ICCDR - 5 µAVCC = 2.0V, IO = 0mA, VI = VCC or
HM-6518-9 - 10 µA

= +25oC

= 5V ±10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9)

CC

LIMITS

UNITS TEST CONDITIONSMIN MAX

ICCOP - 4 mA E = 1MHz, IO = 0mA, VI =VCC or

VCC = 5.5V

GND, VCC = 5.5V

GND, E = V

CC

Input Capacitance (Note 2) CI 6 pF f = 1MHz, All measurements are
Output Capacitance (Note 2) CO 10 pF
NOTES:

1. Typical derating 1.5mA/MHz increase in ICCOP.

2. Tested at initial design and after major design changes.

referenced to device GND

6-3

HM-6518

AC Electrical Specifications V

PARAMETER SYMBOL

Chip Enable Access Time
Address Access Time
Chip Select Output Enable Time
Write Enable Output Disable Time
Chip Select Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Chip Select Write Pulse Setup Time
Chip Enable Write Pulse Setup Time

= 5V ±10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9)

CC

LIMITS

HM-6518B-9 HM-6518-9

MIN MAX MIN MAX

(1)

TELQV - 180 - 250 ns (Notes 1, 3)

(2)

TAVQV - 180 - 250 ns (Notes 1, 3, 4)

(3)

TSLQX 5 120 5 160 ns (Notes 2, 3)

(4)

TWLQZ - 120 - 160 ns (Notes 2, 3)

(5)

TSHQZ - 120 - 160 ns (Notes 2, 3)

(6)

TELEH 180 - 250 - ns (Notes 1, 3)

(7)

TEHEL 100 - 100 - ns (Notes 1, 3)

(8)

TAVEL 0 - 0 - ns (Notes 1, 3)

(9)

TELAX 40 - 50 - ns (Notes 1, 3)

(10)

TDVWH 80 - 110 - ns (Notes 1, 3)

(11)

TWHDX 0 - 0 - ns (Notes 1, 3)

(12)

TWLSH 100 - 130 - ns (Notes 1, 3)

(13)

TWLEH 100 - 130 - ns (Notes 1, 3)

UNITS

TEST

CONDITIONS

Chip Select Write Pulse Hold Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Read or Write Cycle Time

NOTES:

1. Input pulse levels: 0.8V to VCC- 2.0V; input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. VCC = 4.5V and 5.5V.

4. TAVQV = TELQV + TAVEL.

(14)

TSLWH 100 - 130 - ns (Notes 1, 3)

(15)

TELWH 100 - 130 - ns (Notes 1, 3)

(16)

TWLWH 100 - 130 - ns (Notes 1, 3)

(17)

TELEL 280 - 350 - ns (Notes 1, 3)

6-4

Timing Waveforms

HM-6518

S1,
S2

TIME

REFERENCE

A

E

W

D

Q

1

PREVIOUS

DAT A

TSHQZ

(8)

TAVEL

TEHEL

(7)

HIGH

HIGH Z HIGH Z

(5)

-1

(9)

TELAX

VALID

TELEH

(6)

TELQV (1)

TAVQV (2)

TSLOX

(3)

012345

TELEL

VALID OUTPUT LATCHED

(5)

(8)

TAVEL

TEHEL

(7)

TSHQZ

FIGURE 1. READ CYCLE

NEXT

(17)

TRUTH TABLE

INPUTS OUTPUTS

TIME

REFERENCE

FUNCTIONE S1 WAD Q

-1 H H X X X Z Memory Disabled
0 X H V X Z Cycle Begins, Addresses are Latched
1 L L H X X X Output Enabled
2 L L H X X V Output Valid
3 L H X X V Output Latched
4 H H X X X Z Device Disabled, Prepare for Next Cycle

(Same as -1)

5 X H V X Z Cycle Ends, Next Cycle Begins

(Same as 0)

NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.

In the HM-6518 read cycle the address information is
latched into the on chip registers on the falling edge of
(T = 0). Minimum address setup and hold time require­ments must be met. After the required hold time the
addresses may change state without affecting device oper­ation. In order for the output to be read

S1, S2 and E must

be low,
data is latched into an on chip register. Taking either or

E

both
impedance state. The output data may be re-enabled at
any time by taking
the data will be unlatched.

W must be high. When E goes high, the output

S1 or S2 high, forces the output buffer to a high

S1 and S2 low. On the falling edge of E

6-5

HM-6518

Timing Wavforms

A

E

W

D

Q

S1,
S2

TIME

REFERENCE

(Continued)

(8) TAVEL

TEHEL (7)

HIGH Z

-1 01 234 5

(9)

TELAX

VALID

TELEH (6)

TELWH (15)

TSLWH (14)

TWLSH (12)

FIGURE 2. WRITE CYCLE

TWLEH (13)

TWLWH (16)

TDVWH (10)

VALID DATA

(8) TAVEL

NEXT

TELEL (17)

TEHEL (7)

TWHDX (11)

TRUTH TABLE

TIME

REFERENCE

-1 HXXXX ZMemory Disabled
0 XXVX ZCycle Begins, Addresses are Latched
1 L L L X V Z Write Mode has Begun
2 L L X V Z Data is Written
3 XXXX ZWrite Completed
4 HXXXX ZPrepare for Next Cycle (Same as -1)
5 XXVX ZCycle Ends, Next Cycle Begins (Same as 0)

NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.

The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as
being low simultaneously.

W may go low anytime during the
cycle provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is ter minated
by the first rising edge of either
and hold times must be referenced to the terminating signal.

If a series of consecutive write cycles are to be performed,
the

W line may remain low until all desired locations have
been written. When this method is used, data setup and hold
times must be referenced to the rising edge of

INPUTS OUTPUTS

By positioning the
time (TELEH), various types of write cycles may be

E, W, S1 and S2

performed. If the
pulse (TWLWH) plus an output enable time (TSLQX), a
combination read write cycle is executed. Data may be
modified an indefinite number of times during any write cycle

E, W, S1 or S2. Data setup

(TELEH).
The data input and data output pins may be tied together for

use with a common I/O data bus structure. When using the
RAM in this method, allow a minimum of one output disable
time (TWLQZ) after

E.

the bus. This will ensure that the output buffers are not

FUNCTIONE S1 WAD Q

W pulse at different times within the E low

E low time (TELEH) is greater than the W

W goes low before applying input data to

active.

6-6

Test Load Circuit

HM-6518

DUT

(NOTE 1) C

NOTE:

1. Test head capacitance includes stray and jig capacitance.

L

+

1.5V IOLIOH

-

EQUIVALENT CIRCUIT

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
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