Datasheet HM-6516 Datasheet (Intersil Corporation)

HM-6516

March 1997

Features

• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max

• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max

• Industry Standard Pinout

• Single Supply. . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V V

• TTL Compatible

• Static Memory Cells

• High Output Drive

• On-Chip Address Latches

• Easy Microprocessor Interfacing

Ordering Information

2K x 8 CMOS RAM

Description

The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows

CC

easy memory board layouts, flexible enough to accommo­date a variety of PROMs, RAMS, EPROMs, and ROMs.

The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time . The
address latches allow very simple interfacing to recent gen­eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.

120ns 200ns TEMP. RANGE PACKAGE PKG. NO.

HM1-6516B-9 HM1-6516-9 -40oC to +85oC CERDIP F24.6

- 29102BJA -55oC to +125oC JAN# F24.6

8403607JA 8403601JA -55oC to +125oC SMD# F24.6

- HM4-6516-9 -40oC to +85oC CLCC J32.A

8403607ZA 8403601ZA -55oC to +125oC SMD# J32.A

Pinouts

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2

GND

1
2
3
4
5
6
7
8

9
10
11
12

HM-6516

(CERDIP)

TOP VIEW

24

V

CC

23

A8

22

A9

21

W

20

G

19

A10

18

E

17

DQ7

16

DQ6

15

DQ5

14

DQ4

13

DQ3

A6
A5

A4
A3
A2
A1
A0

NC

DQ0

5
6

7
8

9
10
11
12
13

14

HM-6516

(CLCC)

TOP VIEW

CC

V

NC

NC

A7

NC

1

3 2

4 32 31 30

16 17 18 19 20

15

DQ1

DQ2

GND

NC

DQ3

NC

DQ4

NC

DQ5

PIN DESCRIPTION

29

A8

28

A9

27

NC

26

W
G

25

A10

24

E

23
22

DQ7
DQ6

21

NC No Connect

A0 - A10 Address Inputs

E Chip Enable/Power Down

VSS/GND Ground

DQ0 - DQ7 Data In/Data Out

V

CC

Power (+5V)

W Write Enable

G Output Enable

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-1

File Number 2998.1

Functional Diagram

HM-6516

A10

A9
A8
A7
A6
A5
A4

G

W

E

LATCHED

ADDRESS

REGISTER

A

7

GATED

ROW

DECODER

A

7

LG

128

16

G

L

A3 A2 A1 A0

128 x 128

MATRIX

16

16

16

16

GATED COLUMN

DECODER

44

A

LATCHED ADDRESS

REGISTER

16 16

A

1 OF 8

16

A

8

A

DQ0
THRU

8

DQ7

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HM-6516

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input or Output Voltage Applied for all Grades. . . . . . .GND -0.3V to

VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Ranges:

HM-6516B-9, HM-6516-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance θ

CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W

CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC

JA

θ

JC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25953 Gates

DC Electrical Specifications V

SYMBOL PARAMETER

ICCSB Standby Supply Current - 50 µA IO = 0mA, VI = VCC or GND,

ICCOP Operating Supply Current (Note 1) - 10 mA f = 1MHz, IO = 0mA, G = VCC, VCC =

ICCDR Data Retention Supply Current - 25 µAVCC = 2.0V, IO = 0mA, VI = VCC or

VCCDR Data Retention Supply Voltage 2.0 - V

II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V

IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V

V

IL

V

IH

VOL Output Low Voltage - 0.4 V IO = 3.2mA, VCC = 4.5V

Input Low Voltage -0.3 0.8 V VCC= 4.5V
Input High Voltage 2.4 VCC +0.3 V VCC = 5.5V

= 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)

CC

LIMITS

UNITS TEST CONDITIONSMIN MAX

- 100 µA IO = 0mA, VI = VCC or GND,

-50µAVCC = 2.0V, IO = 0mA, VI = VCC or

VCC = 5.5V, HM-6516B-9

HM-6516-9

5.5V, VI = VCC or GND

GND, E = VCC, HM-6516B-9

GND, E = VCC, HM-6516-9

VOH1 Output High Voltage 2.4 - V IO = -1.0mA, VCC = 4.5V
VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, VCC = 4.5V

Capacitance T

SYMBOL PARAMETER MAX UNITS TEST CONDITIONS

CI Input Capacitance (Note 2) 8 pF f = 1MHz, All measurements are

CIO Input/Output Capacitance (Note 2) 10 pF

NOTES:

1. Typical derating 5mA/MHz increase in ICCOP.

2. Tested at initial design and after major design changes.

= +25oC

A

referenced to device GND

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HM-6516

AC Electrical Specifications V

SYMBOL PARAMETER

(1)

TELQV Chip Enable Access Time - 120 - 200 ns (Notes 1, 3)

(2)

TAVQV Address Access Time - 120 - 200 ns (Notes 1, 3, 4)

(3)

TELQX Chip Enable Output Enable Time 10 - 10 - ns (Notes 2, 3)

(4)

TWLQZ Write Enable Output Disable Time - 50 - 80 ns (Notes 2, 3)

(5)

TEHQZ Chip Enable Output Disable Time - 50 - 80 ns (Notes 2, 3)

(6)

TGLQV Output Enable Output Valid Time - 80 - 80 ns (Notes 1, 3)

(7)

TGLQX Output Enable Output Enable Time 10 - 10 - ns (Notes 2, 3)

(8)

TGHQZ Output Enable Output DisableTime - 50 - 80 ns (Notes 2, 3)

(9)

TELEH Chip Enable Pulse Negative Width 120 - 200 - ns (Notes 1, 3)

(10)

TEHEL Chip Enable Pulse Positive Width 50 - 80 - ns (Notes 1, 3)

(11)

TAVEL Address Setup Time 0 - 0 - ns (Notes 1, 3)

(12)

TELAX Address Hold Time 30 - 50 - ns (Notes 1, 3)

(13)

TWLWH Write Enable Pulse Width 120 - 200 - ns (Notes 1, 3)

= 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)

CC

LIMITS

HM-6516B-9 HM-6516-9

MIN MAX MIN MAX

UNITS

TEST

CONDITIONS

(14)

TWLEH Write Enable Pulse Setup Time 120 - 200 - ns (Notes 1, 3)

(15)

TELWH Write Enable Pulse Hold Time 120 - 200 - ns (Notes 1, 3)

(16)

TDVWH Data Setup Time 50 - 80 - ns (Notes 1, 3)

(17)

TWHDX Data Hold Time 10 - 10 - ns (Notes 1, 3)

(18)

TELEL Read or Write Cycle Time 170 - 280 - ns (Notes 1, 3)

NOTES:

1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. VCC = 4.5V and 5.5V.

4. TAVQV = TELQV + TAVEL.

6-4

Timing Waveforms

A

E

W

DQ

G

TIME

REFERENCE

(11) TAVEL

(10)

TEHEL

HIGH

(5)

TEHQZ

-1 012345

TELAX

VALID ADD

(2)

TAVQV

(12)

(3)

TELQX

HM-6516

(9)

TELEH

(1)

TELQV

(6)

TGLQV

(7)

TGLQX

(18)

TELEL

VALID DATA OUT

(5)

TEHQZ

(10)

TEHEL

TAVEL

(8)TGHQZ

(11)

NEXT

ADD

FIGURE 1. READ CYCLE

The address information is latched in the on-chip registers
on the falling edge of

E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2),

Timing Waveforms

A

E

W

(Continued)

(10)

TEHEL

TAVEL

W must

TELAX

(11)

VALID ADD

(12)

TELWH

remain high throughout the read cycle. After the data has
been read,

E may return high (T = 3). This will force the out­put buffers into a high impedance mode at time (T = 4).
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.

(11)

TAVEL

NEXT ADD

(18)

(15)

(9)

TELEH

TWLWH

TELEL

(14)

TWLEH

(13)

(16)

TDVWH

TEHEL

(17)

TWHDX

(10)

G is

DQ

TIME

REFERENCE

VALID DATA IN

G

HIGH

-1

012345

FIGURE 2. WRITE CYCLE

6-5

HM-6516

The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on-chip
registers. If a write cycle is to be performed where the output
is not to become active,

G can be held high (inactive).
TDVWH and TWHDX must be met for proper device opera­tion regardless of
mode), a possible bus conflict may exist. If

G. If E and G fall before W falls (read

E rises before W

Typical Performance Curve

-3

-4

-5

-6

/(1A))

-7

CC

-8

LOG (I

-9

-10

-11

-12

-55 -35 -15 5 25 45 65 85 105 125

rises, reference data setup and hold times to the
edge. The write operation is terminated by the first rising edge
of

W (T = 2) or E (T = 3). After the minimum E high time
(TEHEL), the next cycle may begin. If a series of consecutive
write cycles are to be performed, the

W line may be held low
until all desired locations have been written. In this case, data
setup and hold times must be referenced to the rising of

= 2.0V

V

CC

E rising

E.

FIGURE 3. TYPICAL ICCDR vs T

A

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries f or its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

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