Datasheet HI5810 Datasheet (Intersil Corporation)

August 1997

HI5810

CMOS 10 Microsecond, 12-Bit, Sampling

A/D Converter with Internal Track and Hold

Features

• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .100 KSPS

• Built-In Track and Hold

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V

• Maximum Power Consumption. . . . . . . . . . . . . . .40mW

• Internal or External Clock

• 1MHz Input Bandwidth . . . . . . . . . . . . . . . . . . . . . -3dB

Applications

• Remote Low Power Data Acquisition Systems

• Digital Audio

• DSP Modems

• General Purpose DSP Front End

• µP Controlled Measurement Systems

• Process Controls

• Industrial Controls

Description

The HI5810 is a fast, low power, 12-bit, successive­approximation, analog-to-digital conv erter. It can operate from
a single 3V to 6V supply and typically draws just 1.9mA when
operating at 5V. The HI5810 features a built-in track and hold.
The conversion time is as low as 10µs with a 5V supply.

The twelve data outputs feature full high speed CMOS three­state bus driver capability, and are latched and held through a
full conversion cycle. The output is user selectable: [i.e.,
12-bit, 8-bit (MSBs), and/or 4-bit (LSBs)]. A data ready flag,
and conversion-start input complete the digital interface.

An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.

Ordering Information

INL (LSB)

PART

NUMBER

HI5810JIP ±2.5 -40 to 85 24 Ld PDIP E24.3
HI5810KIP ±2.0 -40 to 85 24 Ld PDIP E24.3
HI5810JIB ±2.5 -40 to 85 24 Ld SOIC M24.3
HI5810KIB ±2.0 -40 to 85 24 Ld SOIC M24.3
HI5810JIJ ±2.5 -40 to 85 24 Ld CERDIP F24.3
HI5810KIJ ±2.0 -40 to 85 24 Ld CERDIP F24.3

(MAX OVER

TEMP.)

TEMP.

RANGE

(oC) PACKAGE

PKG.

NO.

Pinout

HI5810

(PDIP, CERDIP, SOIC)

TOP VIEW

DRDY

1

(LSB) D0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

2
3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

10

D8

11

D9

V

12

SS

6-1777

24

V
OEL

23

CLK

22

STRT

21

V

20

V

19

V

18

V

17

VAA-

16

OEM

15

D11 (MSB)

14

D10

13

DD

REF
REF
IN
AA

+

­+

File Number 3633.1

Functional Block Diagram

HI5810

V

V
V

REF

V

AA

VAA-

STRT

DD
SS

V

IN

+

+

TO INTERNAL LOGIC

50Ω
SUBSTRATE

64C

63

32C

16C

8C

4C

2C

C

32C

16C

8C

4C

2C

CONTROL

AND

TIMING

12-BIT

SUCCESSIVE

APPROXIMATION

REGISTER

12-BIT EDGE

TRIGGERED

“D” LATCHED

CLOCK

CLK

DRDY

OEM

D11 (MSB)

D10

D9

D8

D7

D6

D5

D4

V

REF

P1

-

C

C

D3

D2

D1

D0 (LSB)

OEL

6-1778

HI5810

Absolute Maximum Ratings Thermal Information

Supply Voltage

VDD to VSS . . . . . . . . . . . . . . . . . . . .(VSS -0.5V) < VDD < +6.5V

VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)

VAA+ to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

Analog and Reference Inputs

V

IN,VREF+,VREF

Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD+0.3V)

-. . . . . . . . . (VSS -0.3V) < V

< (VDD +0.3V)

INA

Operating Conditions

Temperature Range

PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . 60 12

PDIP Package. . . . . . . . . . . . . . . . . . . 80 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 75 N/A

Maximum Junction Temperature

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Hermetic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications V

PARAMETER

ACCURACY

Resolution 12 - - 12 - Bits
Integral Linearity Error, INL

(End Point)

Differential Linearity Error, DNL J - - ±2.0 - ±2.0 LSB

Gain Error, FSE
(Adjustable to Zero)

Offset Error, V
(Adjustable to Zero)

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD

Signal to Noise Ratio, SNR

Total Harmonic Distortion, THD J fS = Internal Clock, fIN = 1kHz

Spurious Free Dynamic Range, SFDR J fS = Internal Clock, fIN = 1kHz

ANALOG INPUT

Input Current, Dynamic At VIN = V

OS

RMS Signal

RMS Noise + Distortion

RMS Signal

RMS Noise

= VAA+ = 5V, V

DD

Unless Otherwise Specified

J--±2.5 - ±2.5 LSB
K--±2.0 - ±2.0 LSB

K--±2.0 - ±2.0 LSB
J--±3.5 - ±3.5 LSB
K--±2.5 - ±2.5 LSB
J--±2.5 - ±2.5 LSB
K--±1.5 - ±1.5 LSB

JfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

JfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

+ = +4.608V, VSS = VAA- = V

REF

TEST CONDITIONS

+, 0V - ±125 ±150 - ±150 µA

REF

- = GND, CLK = External 1.5MHz,

REF

25oC -40oC TO 85oC

MIN TYP MAX MIN MAX

- 68.8

62.1

- 71.0

63.6

- 70.5

63.2

- 71.5

65.0

- -73.9

-68.4

- -80.3

69.7

- 75.4

69.2

- 80.9

70.7

-- -dB

-- -dB

-- -dB

-- -dB

- - - dBc

- - - dBc

-- -dB

-- -dB

UNITS

dB

dB

dB

dB

dBc

dBc

dB

dB

6-1779

HI5810

Electrical Specifications V

= VAA+ = 5V, V

DD

+ = +4.608V, VSS = VAA- = V

REF

- = GND, CLK = External 1.5MHz,

REF

Unless Otherwise Specified (Continued)

25oC -40oC TO 85oC

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN MAX

UNITS

Input Current, Static Conversion Stopped - ±0.6 ±10 - ±10 µA

Input Bandwidth -3dB - 1 - - - MHz
Reference Input Current - 160 - - - µA
Input Series Resistance, R
Input Capacitance, C
Input Capacitance, C

SAMPLE
HOLD

S

In Series with Input C

SAMPLE

- 420 - - - Ω
During Sample State - 380 - - - pF
During Hold State - 20 - - - pF

DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
Low-Level Input Voltage, V
Input Leakage Current, I
Input Capacitance, C

IL

IN

IH

IL

Except CLK, VIN = 0V, 5V - - ±10 - ±10 µA

2.4 - - 2.4 - V

- - 0.8 - 0.8 V

-10- - - pF

DIGITAL OUTPUTS

High-Level Output Voltage, V
Low-Level Output Voltage, V
Three-State Leakage, I
Output Capacitance, C

OZ

OUT

OH

OL

I

SOURCE

I

SINK

Except DRDY, V

= -400µA 4.6 - - 4.6 - V

= 1.6mA - - 0.4 - 0.4 V

= 0V, 5V - - ±10 - ±10 µA

OUT

Except DRDY - 20 - - - pF

CLOCK

High-Level Output Voltage, V
Low-Level Output Voltage, V

OH

OL

I

SOURCE

I

SINK

= -100µA (Note 2) 4 - - 4 - V

= 100µA (Note 2) - - 1 - 1 V

Input Current CLK Only, VIN = 0V, 5V - - ±5- ±5mA

TIMING

Conversion Time (t

CONV

+ t

ACQ

)

10 - - 10 - µs

(Includes Acquisition Time)
Clock Frequency Internal Clock, (CLK = Open) 200 300 400 150 500 kHz

External CLK (Note 2) 0.05 - 2.0 - - MHz

Clock Pulse Width, t

LOW

, t

HIGH

External CLK (Note 2) 100 - - 100 - ns

Aperture Delay, tDAPR (Note 2) - 35 50 - 70 ns
Clock to Data Ready Delay, tD1DRDY (Note 2) - 105 150 - 180 ns
Clock to Data Ready Delay, tD2DRDY (Note 2) - 100 160 - 195 ns
Start Removal Time, tRSTRT (Note 2) 75 30 - 75 - ns
Start Setup Time, tSUSTRT (Note 2) 85 60 - 100 - ns
Start Pulse Width, tWSTRT (Note 2) 10 4 - 15 - ns
Start to Data Ready Delay, tD3DRDY (Note 2) - 65 105 - 120 ns
Clock Delay from Start, tDSTRT (Note 2) - 60 - - - ns
Output Enable Delay, t
Output Disabled Delay, t

EN

DIS

(Note 2) - 20 30 - 50 ns
(Note 2) - 80 95 - 120 ns

POWER SUPPLY CHARACTERISTICS

Supply Current, IDD + I

AA

- 2.6 8 - 8.5 mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

6-1780

Timing Diagrams

HI5810

CLK

(EXTERNAL

OR INTERNAL)

STRT

DRDY

D0 - D11

V

OEL = OEM = V

1

IN

SS

2

t

DRDY

D1

t

D2

DATA N - 1

TRACK N TRACK N + 1

3

DRDY

4

5 - 14

t

LOW

HOLD N

15

1

t

HIGH

2

DATA N

3

FIGURE 1. CONTINUOUS CONVERSION MODE

CLK

(EXTERNAL)

STRT

DRDY

15

HOLD

V

IN

1

tRSTRT

2

2

TRACK

2

3

tSUSTRT

t

STRT

W

tD3DRDY

4

5

HOLD

FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK

6-1781

Timing Diagrams (Continued)

HI5810

(INTERNAL)

OEL OR OEM

D0 - D3 OR

D4 - D11

HIGH

IMPEDANCE

TO HIGH

HIGH

IMPEDANCE

TO LOW

CLK

STRT

DRDY

V

50%

50%

15 1

STRT

t

R

HOLD

IN

2

TRACK

345

t

STRT

D

t

STRT

W

DON’T CARE

tD3DRDY

HOLD

FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK

t

t

EN

1.6mA

DIS

90%

10%

TO
OUTPUT
PIN

1.6mA

+2.1V

50pF

-1.6mA

50pF

-400µA

FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM FIGURE 5. TIMING LOAD CIRCUIT

Typical Performance Curves

2.0

1.9

1.8

1.7

1.6

1.5

1.4

INL ERROR (LSBs)

1.3

1.2

1.1

1.0

-50

VDD = VAA+ = 5V, V

-20 -10 80 90

-30

-40

+ = 4.608V, CLK = 1.5MHz

REF

0

10 20 30 40 50 60 70

TEMPERATURE (oC)

FIGURE 6. NL vs TEMPERATUREI FIGURE 7. OFFSET ERROR vs TEMPERATURE

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

ERROR (LSBs)

0.55

OS

V

0.50

0.45

0.40

0.35

0.30

-50

VDD = VAA+ = 5V, V

-30

-40

-20 -10 80 90

+ = 4.608V, CLK = 1.5MHz

REF

0

10 20 30 40 50 60 70

TEMPERATURE (

o

+2.1V

C)

6-1782

Typical Performance Curves (Continued)

HI5810

1.75

1.70

VDD = VAA+ = 5V, V

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

DNL ERROR (LSBs)

1.20

1.15

1.10

1.05

1.00

-50 -40-30 0 10203040506070

-20 -10 80 90

+ = 4.608V, CLK = 1.5MHz

REF

TEMPERATURE (

o

C)

-1.0

-1.1
VDD = VAA+ = 5V, V

-1.2

-1.3

-1.4

-1.5

-1.6

-1.7

-1.8

-1.9

FSE (LSBs)

-2.0

-2.1

-2.2

-2.3

-2.4

-2.5

-50 -40-30 0 10203040506070

-20 -10 80 90

+ = 4.608V, CLK = 1.5MHz

REF

TEMPERATURE (

FIGURE 8. DNL vs TEMPERATURE FIGURE 9. FULL SCALE ERROR vs TEMPERATURE

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

SUPPLY CURRENT (mA)

1.5

1.0

0.5

0.0

-50 -40-30 0 10203040506070

-20 -10 80 90
TEMPERATURE (

o

C)

AMPLITUDE (dB)

FREQUENCY

FIGURE 10. SUPPLY CURRENT vs TEMPERATURE FIGURE 11. FFT SPECTRUM

o

C)

INPUT FREQUENCY = 1kHz
SAMPLING RATE = 100kHz
SNR = 64.92dB
SINAD = 63.82dB
EFFECTIVE BITS = 10.30
THD = -69.44dBc
PEAK NOISE = -70.1dB
SFDR = 70.1dB

500

450

400

350

300

250

200

INTERNAL CLOCK FREQUENCY (kHz)

150

-60

VDD = VAA+ = 5V, V

-20 0 20 40 60 80 100 120 140

-40

+ = 4.608V

REF

TEMPERATURE (

o

C)

FIGURE 12. INTERNAL CLOCK FREQUENCY vs TEMPERATURE

6-1783

HI5810

TABLE 1. PIN DESCRIPTIONS

PIN NO. NAME DESCRIPTION

1 DRDY Output flag signifying new data is av ailab le .

Goes high at end of clock period 15. Goes low

when new conversion is started.
2 D0 Bit-0 (Least Significant Bit, LSB).
3 D1 Bit 1.
4 D2 Bit 2.
5 D3 Bit 3.
6 D4 Bit 4.
7 D5 Bit 5.
8 D6 Bit 6.
9 D7 Bit 7.

10 D8 Bit 8.
11 D9 Bit 9.
12 V
13 D10 Bit 10.
14 D11 Bit 11 (Most Significant Bit, MSB)
15 OEM Three-State Enable for D4-D11. Active low

16 VAA- Analog Ground, (0V).
17 VAA+ Analog Positive Supply. (+5V) (See text.)
18 VINAnalog Input.
19 V

20 V

Digital Ground, (0V).

SS

input.

+ Reference Voltage Positive Input, sets 4095

REF

code end of input range.

- Reference Voltage Negative Input, sets 0

REF

code end of input range.

During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto balanced at the capacitor
common node.

During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V
capacitors to V
charges balance out, will indicate whether the input was

1

above

/2 of (V

REF

REF

+ terminal; and the remaining

REF

-. The capacitor common node, after the
+ - V

-). At the end of the fourth

REF

period, the comparator output is stored and the MSB
capacitor is either left connected to V
was high) or returned to V
comparison to be at either

REF

3

/4 or1/4 of (V

+ (if the comparator

REF

-. This allows the next

REF

+ - V

REF

-).

At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V

REF

+ or at V

REF

-.

At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data ready output goes active. The conversion cycle is
now complete.

Analog Input

The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.

At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have lo w
enough impedance to dissipate the current spike by the end of
the tracking period as shown in Figure 13. The amount of
charge is dependent on supply and input voltages. The
average current is also proportional to clock frequency.

21 STRT Start Conversion Input active low, recognized

after end of clock period 15.

22 CLK CLK Input or Output. Conversion functions are

synchronized to positive going edge (see text).
23 OEL Three-State Enable for D0 D3. Active lo w input.
24 V

Digital Positive Supply (+5V).

DD

Theory of Operation

The HI5810 is a CMOS 12-bit, Analog-to-Digital Converter
that uses capacitor charge balancing to successively
approximate the analog input. A binarily weighted capacitor
network forms the A/D heart of the device. See the block
diagram for the HI5810.

The capacitor network has a common node which is
connected to a comparator. The second terminal of each
capacitor is individually switchable to the input, V
V

-.

REF

REF

+ or

6-1784

20mA

I

IN

10mA

0mA

CLK

DRDY

5V

0V
5V

0V

200ns/DIV.

CONDITIONS: VDD= VAA+ = 5.0V, V

V

= 4.608V, CLK = 750kHz, TA = 25oC

IN

FIGURE 13. TYPICAL ANALOG INPUT CURRENT

+ = 4.608V,

REF

HI5810

As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 1.5MHz the track period is 2µs.

A simplified analog input model is presented in Figure 14.
During tracking, the A/D input (V

) typically appears as a

IN

380pF capacitor being charged through a 420Ω internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external “zero Ω” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time
constants or 1.4µs. The maximum source impedance
(R

SOURCE

Max) for a 2µs acquisition time settling to within

0.5 LSB is 164Ω.
If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.

V

IN

R

SOURCE

R

SOURCE (MAX)

FIGURE 14. ANALOG INPUT MODEL IN TRACK MODE

=

C

SAMPLE

R

SW

-t

ACQ

ln [2

≈ 420Ω

-(N + 1)

- R

]

C

SAMPLE

SW

≈ 380pF

Reference Input

The reference input V

+ should be driven from a low

REF

impedance source and be well decoupled.
As shown in Figure 15, current spikes are generated on the

reference pin during each bit test of the successive approxi­mation part of the conversion cycle as the charge balancing
capacitors are switched between V

REF

- and V

REF

+ (clock
periods 5 - 14). These current spikes must settle completely
during each bit test of the conversion to not degrade the
accuracy of the converter. Therefore V
should be well bypassed. Reference input V
connected directly to the analog ground plane. If V

REF

REF

+ and V

- is normally

REF

REF

- is
biased for nulling the converters offset it must be stable
during the conversion cycle.

20mA

+

I

10mA

REF

0mA

CLK

DRDY

5V
0V

5V
0V

2µs/DIV.

CONDITIONS: VDD= VAA+ = 5.0V, V

V

= 2.3V, CLK = 750kHz, TA = 25oC

IN

FIGURE 15. TYPICAL REFERENCE INPUT CURRENT

+ = 4.608V,

REF

The HI5810 is specified with a 4.608V reference, however, it
will operate with a reference down to 3V having a slight
degradation in performance.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5810 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.

The V

REF

+ and V

- pins reference the two ends of the

REF

analog input range and may be used for offset and full scale
adjustments. In a typical system the V

- might be returned

REF

to a clean ground, and the offset adjustment done on an input
amplifier. V
scale error. When this is not possible, the V
adjusted to null the offset error, however, V

+ would then be adjusted to null out the full

REF

- input can be

REF

- must be well

REF

decoupled.
Full scale and offset error can also be adjusted to zero in the

signal conditioning amplifier driving the analog input (V

Control Signal

The HI5810 may be synchronized from an external source
by using the
sion, or if

STRT (Start Conversion) input to initiate conv er-

STRT is tied low, may be allowed to free run. Each

conversion cycle takes 15 clock periods.
The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by t
data), the output is updated.

The DRDY (Data Ready) status output goes high (specified
by t

DRDY) after the star t of clock period 1, and returns

D1

low (specified by t

DRDY) after the start of clock period 2.

D2

The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the

­significant byte (D4 through D11) while the

enables the four least significant bits (D0 - D3). t

OEM input enables the most

OEL input

EN

specify the output enable and disable times.
If the output data is to be latched externally, either the trailing

edge of data ready or the next falling edge of the clock after
data ready goes high can be used.

When

STRT input is used to initiate conv ersions, oper ation is
slightly different depending on whether an internal or
external clock is used.

Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least tRSTRT) before clock
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.

A low signal applied to
now initiate a new conversion. The
delay of (t

STRT)) causes the clock to restart.

D

STRT (at least tWSTRT wide) can

STRT signal (after a

Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.

IN

and t

).

D

DIS

6-1785

HI5810

The input will continue to track until the end of period 3, the
same as when free running.

Figure 2 illustrates the same operation as above but with an
external clock. If STRT is removed (at least tRSTRT) before
clock period 2, a low signal applied to

STRT will drop the
DRDY flag as before, and with the first positive going clock
edge that meets the (t

STRT) setup time, the converter will

SU

continue with clock period 3.

Clock

The HI5810 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are synchro­nized with the rising edge of the clock signal.

Figure 16 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.

The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.

If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minium frequency shown in the specifications.
In the above two cases, a further restriction applies in that
the clock should not be shut off during the third sample
period for more than 1ms. This might cause an internal
charge pump voltage to decay.

If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.

An external clock must also meet the minimum t
t

times shown in the specifications. A violation may

HIGH

LOW

and

cause an internal miscount and invalidate the results.

Except for VAA+, which is a substrate connection to VDD, all
pins have protection diodes connected to V
Input transients above V

or below VSS will get steered to

DD

and VSS.

DD

the digital supplies.
The V

+ and VAA- terminals supply the charge balancing

AA

comparator only. Because the comparator is autobalanced
between conversions, it has good low frequency supply
rejection. It does not reject well at high frequencies however;
V

- should be returned to a clean analog ground and VAA+

AA

should be RC decoupled from the digital supply as shown in
Figure 17.

There is approximately 50Ω of substrate impedance
between V

and VAA+. This can be used, for example, as

DD

part of a low pass RC filter to attenuate switching supply
noise. A 10µF capacitor from V

+ to ground would

AA

attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from V

to VAA+ to

DD

handle supply to capacitor turn-on or turn-off current spikes.

Dynamic Performance

Fast Fourier Transform (FFT) techniques are used to evalu­ate the dynamic performance of the A/D. A low distortion
sine wave is applied to the input of the A/D conver ter. The
input is sampled by the A/D and its output stored in RAM.
The data is than transformed into the frequency domain with
a 4096 point FFT and analyzed to evaluate the conver ters
dynamic performance such as SNR and THD. See Typical
Performance Characteristics.

Signal-To-Noise Ratio

The signal to noise ratio (SNR) is the measured RMS signal to
RMS sum of noise at a specified input and sampling frequency.
The noise is the RMS sum of all except the fundamental and
the first five harmonic signals. The SNR is dependent on the
number of quantization levels used in the conver ter. The theo­retical SNR for an N-bit converter with no differential or integral
linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 12-bit
converter the SNR is 74dB. Differential and integral linearity
errors will degrade SNR.

SNR = 10 Log

Sinewave Signal Power

Total Noise Power

INTERNAL
ENABLE

CLK

OPTIONAL

EXTERNAL

CLOCK

FIGURE 16. INTERNAL CLOCK CIRCUITRY

100kΩ

CLOCK

18pF

Power Supplies and Grounding

and VSS are the digital supply pins: they power all

V

DD

internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V

DD

and V

SS

lines, VSS should have a low impedance path to digital
ground and V

should be well bypassed.

DD

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Signal-To-Noise + Distortion Ratio

SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following.

SINAD = 10 Log

Sinewave Signal Power

Noise + Harmonic Power (2nd - 6th)

Effective Number of Bits

The effective number of bits (ENOB) is derived from the
SINAD data;

ENOB =

SINAD - 1.76

6.02

HI5810

Total Harmonic Distortion

The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
the fundamental RMS signal for a specified input and
sampling frequency.

THD = 10Log

Total Harmonic Power (2nd - 6th Harmonic)

Sinewave Signal Power

Spurious-Free Dynamic Range

The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the RMS amplitude of the
next largest spur or spectral component. If the harmonics
are buried in the noise floor it is the largest peak.

SFDR = 10Log

Sinewave Signal Power

Highest Spurious Signal Power

TABLE 2. CODE TABLE

INPUT

BINARY OUTPUT CODE

VOLTAGE†

V

CODE

DESCRIPTION

+ = 4.608V

REF

V

REF

- = 0V

(V)

DECIMAL

COUNT

MSB LSB

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Full Scale (FS) 4.6069 4095 1 1 1 1 1 1 1 1 1 1 1 1
FS - 1 LSB 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0

3

/4 FS 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0

1

/2 FS 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0

1

/4 FS 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0
1 LSB 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1
Zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0

†The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.

+5V

0.1µF

0.01µF0.1µF10µF

VAA+V

V

REF

0.1µF4.7µF

ANALOG

INPUT

0.001µF

V

+

REF

V

IN

-VAA-V

V

REF

DD

D11

D0

DRDY

OEM

OEL

STRT

CLK

.

.

.

SS

4.7µF

OUTPUT
DAT A

1.5MHz CLOCK

FIGURE 17. GROUND AND SUPPLY DECOUPLING

6-1787

Die Characteristics

HI5810

DIE DIMENSIONS:

3200µm x 3940µm

METALLIZATION:

Type: AlSi
Thickness: 11k

Å ±1kÅ

Metallization Mask Layout

D2

D3

D4

D1

D0
(LSB)

PASSIVATION:

Type: PSG
Thickness: 13k

Å ±2.5kÅ

WORST CASE CURRENT DENSITY:

5

2

1.84 x 10

HI5810

DRDY VDDOEL

A/cm

CLK

STRT

V

REF

-

D5

V

D6

D7

D8

D9

SS

D11D10

(MSB)

OEMV

REF

V

IN

VAA+

VAA-

+

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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

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6-1788