Datasheet HI5662 Datasheet (Intersil Corporation)

HI5662

Data Sheet February 1999 File Number 4317.2

Dual 8-Bit, 60MSPS A/D Converter with
Internal Voltage Reference

The HI5662 is a monolithic, dual 8-Bit, 60MSPS analog-to­digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. The HI5662 reaches
a new level of multi-channel integration. The fully pipeline
architecture and an innovativeinputstageenable the HI5662
to accept a variety of input configurations, single-ended or
fully differential. Only one external clock is necessary to
drive both converters and an internal band-gap voltage
reference is provided. This allows the system designer to
realize an increased level of system integration resulting in
decreased cost and power dissipation.

The HI5662 has excellent dynamic performance while
consuming only 650mW power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.

For those customers needing dual channel 10-bit resolution,
please refer to the HI5762. For single channel 10-bit
applications, please refer to the HI5767.

Ordering Information

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS

• 7.8 Bits at f

= 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

• Excellent Channel-to-Channel Isolation. . . . . . . . . >75dB

• On-Chip Sample and Hold Amplifiers

• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V

• Fully Differential or Single-Ended Analog Inputs

• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary Digital Data Output Format

• Dual 8-Bit A/D Converters on a Monolithic Chip

Applications

• Wireless Local Loop

• PSK and QAM I and Q Demodulators

• Medical Imaging

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE PKG. NO.

HI5662/6IN -40 to 85 44 Ld MQFP Q44.10x10
HI5662EVAL2 25 Evaluation Platform

• High Speed Data Acquisition

Pinout

HI5662

(MQFP)

TOP VIEW

AV

DV

A

D

GND

CC2

ID7
ID6
ID5
ID4
ID3

CC3

GND

ID2
ID1

DC

IV

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

IN-IIN+

I

GND

RIN

A

V

39 38 37 36 35 34

NC

ROUT

V

CC1

AV

IN+QIN-

Q

DC

QV

33
32
31
30
29

28
27
26
25
24
23

2221201918

A

GND

AV
QD7
QD6
QD5
QD4
QD3
DV
D

GND

QD2
QD1

CC2

CC3

10

NC

NC

ID0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

CC1

GND

CLK

D

DV

| Copyright © Intersil Corporation 1999

CC2

DV

GND

D

NC

NC

QD0

Functional Block Diagram

HI5662

I/QIN-

I/Q

BIAS

+

IN

S/H

STAGE 1

X2

2-BIT

FLASH

+

∑

-

STAGE M-1

2-BIT

FLASH

+

∑

-

2-BIT

DAC

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

2-BIT

DAC

I/QV

DC

DV

CC3

I/QD7 (MSB)

I/QD6

I/QD5

I/QD4

I/QD3

I/QD2

I/QD1

I/QD0 (LSB)

V

REFOUT

V

REFIN

X2

REFERENCE

11

2-BIT

FLASH

AV

CC1,2

STAGE M

AGND DV

CC1,2

DGND

CLOCK

I or Q CHANNEL

CLK

Typical Application Schematic

HI5662

HI5662

+

I

IN

IIN-

Q

+

IN

-

Q

IN

0.1µF

+

(42) I

IN

(44) IV

DC

(43) IIN-

+

(36) Q

IN

(34) QV

DC

(35) QIN-

(40) V

RIN

(38) V

ROUT

(13,14,20,21,39) NC

(LSB) ID0 (12)

ID1 (11)
ID2 (10)
ID3 (7)
ID4 (6)
ID5 (5)
ID6 (4)

(MSB) ID7 (3)

(LSB) QD0 (22)

QD1 (23)
QD2 (24)
QD3 (27)
QD4 (28)
QD5 (29)
QD6 (30)

(MSB) QD7 (31)

CLK (17)

DV

(8,26)

CC3

ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7

QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7

0.1µF10µF

+

CLOCK

+5V or +3V

+5V

10µF

(37) AV

CC1

(2,32) AV

+

0.1µF

AGND

BNC

CC2

(1,33,41) AGND

DGND

DV

(18)

CC2

DV

(16)

CC1

DGND (9,15,19,25)

10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE

0.1µF10µF

+

+5V

12

Pin Descriptions

HI5662

PIN NO. NAME DESCRIPTION

1A
2AV

GND

CC2

Analog Ground

Analog Supply (+5.0V)
3 ID7 I-Channel, Data Bit 7 Output (MSB)
4 ID6 I-Channel, Data Bit 6 Output
5 ID5 I-Channel, Data Bit 5 Output
6 ID4 I-Channel Data Bit 4 Output
7 ID3 I-Channel, Data Bit 3 Output
8DV

CC3

Digital Output Supply

(+3.0V or +5.0V)
9D

GND

Digital Ground

10 ID2 I-Channel, Data Bit 2 Output
11 ID1 I-Channel, Data Bit 1 Output
12 ID0 I-Channel, Data Bit 0 Output (LSB)
13 NC No Connect
14 NC No Connect
15 D
16 DV

GND

CC1

Digital Ground

Digital Supply (+5.0V)

17 CLK Sample Clock Input
18 DV
19 D

CC2

GND

Digital Supply (+5.0V)

Digital Ground

20 NC No Connect
21 NC No Connect
22 QD0 Q-Channel, Data Bit 0 Output(LSB)
23 QD1 Q-Channel, Data Bit 1 Output

PIN NO. NAME DESCRIPTION

24 QD2 Q-Channel, Data Bit 2 Output
25 D
26 DV

GND

CC3

Digital Ground
Digital Output Supply

(+3.0V or +5.0V)
27 QD3 Q-Channel, Data Bit 3 Output
28 QD4 Q-Channel, Data Bit 4 Output
29 QD5 Q-Channel, Data Bit 5 Output
30 QD6 Q-Channel, Data Bit 6 Output
31 QD7 Q-Channel, Data Bit 7 Output

(MSB)
32 AV
33 A
34 QV
35 Q
36 Q
37 AV
38 V

CC2

GND

DC

IN-

IN+

CC1

ROUT

Analog Supply (+5.0V)

Analog Ground

Q-Channel DC Bias Voltage Output

Q-Channel Negative Analog Input

Q-Channel Positive Analog Input

Analog Supply (+5.0V)

+2.5V Reference Voltage Output
39 NC No Connect
40 V
41 A
42 I
43 I
44 IV

RIN

GND

IN+

IN-

DC

+2.5V Reference Voltage Input

Analog Ground

I-Channel Positive Analog Input

I-Channel Negative Analog Input

I-Channel DC Bias Voltage Output

13

HI5662

Absolute Maximum Ratings T

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

Operating Conditions

Temperature Range

HI5662/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits
Integral Linearity Error, INL f
Differential Linearity Error, DNL

(Guaranteed No Missing Codes)
Offset Error, V
Full Scale Error, FSE fIN = DC - 1 - LSB

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes - 1 - MSPS
Maximum Conversion Rate No Missing Codes 60 - - MSPS
Effective Number of Bits, ENOB fIN = 10MHz

Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz - 48.7 - dB

--------------------------------------------------------------=

RMS Noise + Distortion

OS

RMS Signal

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

HI5662/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

CC
CC

= DV

CC1,2

= 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified

C

L

= +5.0V, DV

CC1,2

= 10MHz - 0.5 - LSB

IN

fIN = 10MHz - ±0.2 ±1.0 LSB

fIN = DC -10 - +10 LSB

fIN = 10MHz, Single Ended Analog Input

CC3

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(Lead Tips Only)

= +3.0V; V

= 2.50V; fS = 60MSPS at 50% Duty Cycle;

RIN

7.5

7.0

7.8

7.7

-

-

Bits
Bits

Signal to Noise Ratio, SNR f

RMS Signal

-------------------------------=

RMS Noise

Total Harmonic Distortion, THD fIN = 10MHz - -66 - dBc
2nd Harmonic Distortion fIN = 10MHz - -71 - dBc
3rd Harmonic Distortion fIN = 10MHz - -71 - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz - 71 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - 64 - dBc
I/Q Channel Crosstalk - -75 -60 dBc
I/Q Channel Offset Match - 2.5 - LSB
I/Q Channel Full Scale Error Match - 2.5 - LSB
Transient Response (Note 2) - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

= 10MHz - 48 - dB

IN

14

HI5662

Electrical Specifications AV

CC1,2

= DV

CC1,2

= +5.0V, DV

= +3.0V; V

CC3

= 2.50V; fS = 60MSPS at 50% Duty Cycle;

RIN

CL= 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

- ±0.5 - V

Range (VIN+ - VIN-)
Maximum Peak-to-Peak Single-Ended

- 1.0 - V

Analog Input Range
Analog Input Resistance, R
Analog Input Capacitance, C
Analog Input Bias Current, IB+ or IB-V

IN+

IN+

or R

or C

IN-

IN-

V

, V

IN+

V

IN+
IN+

= VREF,DC - 1 - MΩ

IN-

, V

= 2.5V,DC - 10 - pF

IN-

, V

IN-

= V

REF-

, V

REF+

, DC

-10 - 10 µA

(Notes 2, 3)

Differential Analog Input Bias Current
I

= (IB+- IB-)

BDIFF

(Notes 2, 3) -0.5 - +0.5 µA

Full Power Input Bandwidth, FPBW (Note 2) - 250 - MHz
Analog Input Common Mode Voltage Range

Differential Mode (Note 2) 0.25 - 4.75 V

(VIN++ VIN-) / 2

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage, V
Reference Output Current, I

(Loaded) 2.35 2.5 2.65 V

ROUT

ROUT

-24mA

Reference Temperature Coefficient - -400 - ppm/oC

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

RIN

Total Reference Resistance, R
Reference Current, I

RIN

RIN

with V
with V

= 2.5V - 1.25 - kΩ

RIN

= 2.5V - 2 - mA

RIN

- 2.5 - V

DC BIAS VOLTAGE

DC Bias Voltage Output, V

DC

- 3.0 - V

Maximum Output Current - - 0.4 mA

SAMPLING CLOCK INPUT

Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic High Current, I
Input Logic Low Current, I
Input Capacitance, C

IN

IH

IL

IH

IL

CLK 2.0 - - V
CLK - - 0.8 V
CLK, VIH= 5V -10.0 - +10.0 µA
CLK, VIL= 0V -10.0 - +10.0 µA
CLK - 7 - pF

DIGITAL OUTPUTS

Output Logic High Voltage, V
Output Logic Low Voltage, V
Output Logic High Voltage, V
Output Logic Low Voltage, V
Output Capacitance, C

OUT

OH

OL

OH

OL

IOH= 100µA; DV
IOL= 100µA; DV
IOH= 100µA; DV
IOL= 100µA; DV

= 5V 4.0 - - V

CC3

= 5V - - 0.8 V

CC3

= 3V 2.4 - - V

CC3

= 3V - - 0.5 V

CC3

-7- pF

TIMING CHARACTERISTICS

Aperture Delay, t
Aperture Jitter, t

AP

AJ

Data Output Hold, t

H

-5- ns

-5-ps

RMS

- 10.7 - ns

15

HI5662

Electrical Specifications AV

CC1,2

= DV

CC1,2

= +5.0V, DV

= +3.0V; V

CC3

= 2.50V; fS = 60MSPS at 50% Duty Cycle;

RIN

CL= 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Data Output Delay, t
Data Latency, t

LAT

OD

For a Valid Sample (Note 2) 6 6 6 Cycles

- 11.7 - ns

Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles
Sample Clock Pulse Width (Low) (Note 2) 7.5 8.3 - ns
Sample Clock Pulse Width (High) (Note 2) 7.5 8.3 - ns
Sample Clock Duty Cycle Variation ±5%

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV
Digital Supply Voltage, DV

CC

CC1

and DV

Digital Output Supply Voltage, DV

CC2

CC3

(Note 2) 4.75 5.0 5.25 V
(Note 2) 4.75 5.0 5.25 V
At 3.0V (Note 2) 2.7 3.0 3.3 V
At 5.0V (Note 2) 4.75 5.0 5.25 V

Supply Current, I

CC

fS= 60MSPS - 130 - mA
Power Dissipation - 650 670 mW
Offset Error Sensitivity, ∆V

OS

AVCCor DVCC = 5V ±5% - ±0.125 - LSB
Gain Error Sensitivity, ∆FSE AVCC or DVCC= 5V ±5% - ±0.15 - LSB

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

16

Timing Waveforms

ANALOG

INPUT

HI5662

CLOCK

INPUT

S

N - 1HN - 1SN

HNS

N + 1HN + 1SN + 2

INPUT

S/H

1ST

STAGE

2ND

STAGE

M-th

STAGE

DAT A

OUTPUT

B2,

N - 2

B1,

B9,

N - 1

N - 5

B2,

D

N - 1

N - 6

B9,

B1,

N

N - 4

B2,

D

N

N - 5

B1,

N + 1

t

LAT

NOTES:

4. SN: N-th sampling period.

5. HN: N-th holding period.

6. BM, N: M-th stage digital output corresponding to N-th sampled input.

7. DN: Final data output corresponding to N-th sampled input.

FIGURE 1. HI5662 INTERNAL CIRCUIT TIMING

S

N + 5HN + 5SN + 6HN + 6SN + 7HN + 7SN + 8HN + 8

B1,

B9,

N + 4

N

B2,

D

N + 4

N - 1

B1,

B9,

N + 5

N + 1

B2,

D

N + 5

N

B1,

B9,

N + 6

N + 2

B2,

D

N + 6

N + 1

B1,

B9,

N + 7

N + 3

D

N + 2

ANALOG

INPUT

CLOCK

INPUT

DAT A

OUTPUT

17

1.5V

t

AP

t

AJ

1.5V

t

OD

t

H

2.4V

DATA N-1

0.5V

FIGURE 2. HI5662 INPUT-TO-OUTPUT TIMING

DATA N

Typical Performance Curves

HI5662

8

7

ENOB (BITS)

6

fS = 60MSPS
T

= 25oC

A

5

1 10 100

INPUT FREQUENCY (MHz)

FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND

SINAD vs INPUT FREQUENCY

90

85

-2HD

80

75

-3HD

70

dBc

65

-THD

60

55

fS = 60MSPS

= 25oC

T

A

50

1 10 100

INPUT FREQUENCY (MHz)

50

44

38

32

SINAD (dB)

50

44

SNR (dB)

38

fS = 60MSPS
T

= 25oC

A

32

1 10 100

INPUT FREQUENCY (MHz)

FIGURE 4. SNR vs INPUT FREQUENCY

70

60

50

-THD (dBc)

40

dB

30

SNR (dB) OR SINAD (dB)

20

10

-40 -10 0-30 -20
INPUT LEVEL (dBFS)

FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE

8

7

ENOB (BITS)

6

5

fS = 60MSPS
1MHz < f
T

A

= 25oC

42 44 46 48 50 52 5440

< 15MHz

IN

DUTY CYCLE (%, t

HI/tCLK

56 58 60

)

FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs

SAMPLE CLOCK DUTY CYCLE

150

1MHz < fIN < 15MHz

140

TA = 25oC

130
120
110

I

CC

100

90

AI

80

CC

70
60
50
40

SUPPLY CURRENT (mA)

30
20
10

0

10

30 40 50 60 7020

f

(MSPS)

S

DI

CC3

FIGURE 8. SUPPLYCURRENT vs SAMPLE CLOCK

FREQUENCY

DI

CC1

DI

18

CC2

Typical Performance Curves (Continued)

HI5662

2.50

2.49

2.48

2.47

2.46

(V)

2.45

ROUT

2.44

V

2.43

2.42

INTERNAL REFERENCE VOLTAGE,

2.41

2.40

-40

0 20406080-20

TEMPERATURE (oC)

FIGURE 9. INTERNAL REFERENCE VOLTAGE (V

TEMPERATURE

13.0

12.5

t

(ns)

OD

t

12.0

OD

ROUT

)vs

3.10

3.05

(V)

DC

3.00

2.95

2.90

DC BIAS VOLTAGE, I/Q V

2.85

-40

IV

DC

0 20406080-20
TEMPERATURE (oC)

QV

DC

FIGURE 10. DC BIAS VOLTAGE (I/QVDC) vs TEMPERATURE

140

I

CC

120

100

80

AI

CC

60

fS = 60MSPS
1MHz < f

IN

< 15MHz

40

DI

11.5

11.0

-40

SUPPLY CURRENT (mA)

0 20406080-20
TEMPERATURE (oC)

CC1

20

DI

CC2

DI

0

-40

CC3

0 20406080-20
TEMPERATURE (oC)

FIGURE 11. DATA OUTPUT DELAY (tOD) vs TEMPERATURE FIGURE 12. SUPPLY CURRENT vs TEMPERATURE

0

fS = 60MSPS

-10
f

= 10MHz

IN

dB

-100

-20

-30

-40

-50

-60

-70

-80

-90

= 25oC

T

A

0 100 200 300 400 500 600 700 800 900 1023

FREQUENCY (BIN)

FIGURE 13. 2048 POINT FFT PLOT

19

HI5662

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

DIFFERENTIAL INPUT

CODE CENTER

DESCRIPTION

+Full Scale (+FS) -7/16LSB 0.498291V 11111111
+FS - 17/16LSB 0.494385V 11111110
+9/16LSB 2.19727mV 10000000

-7/16LSB -1.70898mV 01111111

-FS + 19/16LSB -0.493896V 00000001

-Full Scale (-FS) +9/16LSB -0.497803V 00000000

NOTE:

8. The voltages listed above represent the ideal center of each output code shown with V

VOLTAGE

(I/QIN+ - I/QIN-)

MSB LSB

I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

= +2.5V.

REFIN

Detailed Description

Theory of Operation

The HI5662 is a dual 8-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 14
depicts the circuit for the front end differential-in-differential­out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a non­overlapping two phase signal, φ
master sampling clock. During the sampling phase, φ
input signal is applied to the sampling capacitors, C
same time the holding capacitors, C
analog ground. At the falling edge of φ
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, φ

, the two bottom plates of the

2

sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between C
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample­and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the I/Q
a switch and C

. The relatively small values of these

S

IN

components result in a typical full power input bandwidth of
250MHz for the converter.

Φ

1

Φ

1

C

I/Q

IN+

I/Q

IN-

Φ

FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD

S

Φ

2

C

S

1

Φ

1

and φ2, derived from the

1

, are discharged to

H

the input signal is

1

and CH completing

S

, the

1

. At the

S

pins see only the on-resistance of

C

H

+

-

+

-

C

H

Φ

1

V

OUT+

V

OUT-

Φ

1

As illustrated in the functional block diagram and the timing
diagram in Figure 1, identical pipeline subconverter stages,
each containing a two-bit flash converter and a two-bit
multiplying digital-to-analog converter, follow the S/H circuit
with the last stage being a two bit flash converter. Each
converter stage in the pipeline will be sampling in one phase
and amplifying in the other clock phase. Each individual
subconverter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in
the pipeline performing the same operation.

The output of each of the identical two-bit subconverter
stages is a two-bit digital word containing a supplementary
bit to be used by the digital error correction logic. The output
of each subconverter stage is input to a digital delay line
which is controlled by the internal sampling clock. The
function of the digital delay line is to time align the digital
outputs of the identical two-bit subconverter stages with the
corresponding output of the last stage flash converter before
applying the results to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
eight bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).

Internal Reference Voltage Output, V

REFOUT

The HI5662 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. V

must be connected to V

ROUT

when using the

RIN

internal reference voltage.

20

HI5662

An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A band-gap reference circuit
is used to generate a precision +1.25V internal reference
voltage. This voltage is then amplified by a wide-band
uncompensated operational amplifier connected in a
gain-of-two configuration. An external, user-supplied, 0.1µF
capacitor connected from the V

output pin to analog

ROUT

ground is used to set the dominant pole and to maintain the
stability of the operational amplifier.

Reference Voltage Input, V

REFIN

The HI5662 is designed to accept a +2.5V reference voltage
source at the V
converter requires V
tested with V

input pin. Typical operation of the

RIN

RIN

to be set at +2.5V. The HI5662 is

RIN

connected to V

yielding a fully

ROUT

differential analog input voltage range of ±0.5V.
The user does have the option of supplying an external

+2.5V reference voltage. As a result of the high input
impedance presented at the V

input pin, 1.25kΩ typically,

RIN

the external reference voltage being used is only required to
source 2mA of reference input current. In the situation where
an external reference voltage will be used an external 0.1µF
capacitor must be connected from the V

ROUT

output pin to
analog ground in order to maintain the stability of the internal
operational amplifier.

In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V

RIN

.

Analog Input, Differential Connection

The analog input of the HI5662 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 15 and Figure 16) will deliver
the best performance from the converter.

V

IN

I/QIN+

an AC coupled differential input. This lo w output impedance
voltagesourceisnotdesignedtobeareferencebutmakes an
excellent DC bias source and stays well within the analog
input common mode voltage range ov er temper ature .

For the AC coupled differential input (Figure 15) and with
V

connected to V

RIN

V

and -VIN input signals are 0.5V

IN

180 degrees out of phase with V
positive full scale when the I/Q
the I/Q

input is at VDC- 0.25V (I/Q

IN-

, full scale is achieved when the

ROUT

IN

+ input is at VDC+ 0.25V and

IN

, with -VIN being

P-P

. The converter will be at

- I/Q

IN+

IN-

= +0.5V).
Conversely, the converter will be at negative full scale when
the I/Q
V

DC

input is equal to VDC- 0.25V and I/Q

IN+

+ 0.25V (I/Q

IN+

- I/Q

= -0.5V).

IN-

IN-

is at

The analog input can be DC coupled (Figure 16) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 4.75V).

V

IN

VDC

R

-V

IN

VDC

FIGURE 16. DC COUPLED DIFFERENTIAL INPUT

R

I/QIN+

I/QV

I/QIN-

HI5662

DC

C

The resistors, R, in Figure 16 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from I/Q

+ to I/QIN- will help filter any high

IN

frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.

Analog Input, Single-Ended Connection

The configuration shown in Figure 17 may be used with a
single ended AC coupled input.

R

R

-V

IN

FIGURE 15. AC COUPLED DIFFERENTIAL INPUT

I/QV

I/QIN-

HI5662

DC

Since the HI5662 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.

A DC voltage source, I/QV

, equal to 3.0V (typical), is made

DC

availableto the user to help simplify circuit design when using

21

V

IN

R

VDC

FIGURE 17. AC COUPLED SINGLE ENDED INPUT

Again, with V
sinewav e , then I/Q
positive voltage equal to V
fullscalewhenI/Q

connected to V

RIN

is a 1.0V

IN+

isatVDC+ 0.5V (I/Q

IN+

ROUT

sinewav e riding on a

P-P

. The converter will be at positive

DC

and will be at negative full scale when I/Q
V

- 0.5V (I/Q

DC

IN+

- I/Q

= -0.5V). Sufficient headroom must

IN-

I/QIN+

HI5662

I/QIN-

, if VIN is a 1V

- I/Q

IN+

is equal to

IN+

P-P

IN-

= +0.5V)

be provided such that the input voltage never goes above +5V

HI5662

or below AGND. In this case, VDC could range between 0.5V
and 4.5V without a significant change in ADC performance.
The simplest waytoproduceVDCis to use the DC bias source,
I/QV

, of the HI5662.

DC

The single ended analog input can be DC coupled
(Figure 18) as long as the input is within the analog input
common mode voltage range.

V

IN

V

DC

R

V

DC

FIGURE 18. DC COUPLED SINGLE ENDED INPUT

I/QIN+

C

HI5662

I/QIN-

The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/Q

+ to I/QIN- will help filter any high

IN

frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.

A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5662.

Sampling Clock Requirements

The HI5662 sampling clock input provides a standard high­speed interface to external TTL/CMOS logic families.

In order to ensure rated performance of the HI5662, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL/CMOS levels.

Performance of the HI5662 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must to be performed
before valid data is available.

Supply and Ground Considerations

The HI5662 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
digital data outputs also have a separate supply pin, DV
which can be powered from a 3.0V or 5.0V supply. This allows
the outputs to interface with 3.0V logic if so desired.

The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5662 should be driven by clean, linear

CC3

,

regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.

Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.

Static Performance Definitions

Offset Error (VOS)

The midscale code transition should occur at a level1/4LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

3

is

/4LSB below Positive Full Scale (+FS) with the offset
error removed. Full scale error is defined as the deviation of
the actual code transition from this point.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the
ideal value of 1LSB.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.

Dynamic Performance Definitions

FastFourierTransform (FFT) techniques are used to evaluate
the dynamic performance of the HI5662. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D . The sine w ave input to the
part is typically -0.5dB down from full scale for all these tests.

SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors f or normalizing to full scale.

The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:

ENOB = (SINAD - 1.76 + V
where: V
V

adjusts the SINAD, and hence the ENOB, for the

CORR

= 0.5 dB (Typical).

CORR

amount the analog input signal is backed off from full scale.

CORR

) / 6.02,

22

HI5662

Signal To Noise and Distortion Ratio (SINAD)

SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, f

/2, excluding DC.

S

Signal To Noise Ratio (SNR)

SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below f
excluding the fundamental, the first five harmonics and DC.

/2

S

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below f

/2.

S

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f
(f

+2f2), (f1-2f2). The ADC is tested with each tone 6dB

1

below full scale.

), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),

1+f2

and f2, are

1

Transient Response

Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.

Over-Voltage Recovery

Over-Voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.

I/Q Channel Crosstalk

I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the amount that signal is below, in dBc, a
fullscale signal on the opposite channel.

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

Aperture Delay (tAP)

Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.

Aperture Jitter (tAJ)

Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)
is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the new data (N)
is valid.

Data Latency (t

After the analog sample is taken, the digital data
representing an analog input sample is output to the digital
data bus following the 6th cycle of the clock after the analog
sample is taken. This is due to the pipeline nature of the
converter where the analog sample has to ripple through the
internal subconverter stages. This delay is specified as the
data latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.

Power-Up Initialization

This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.

LAT

)

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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