Datasheet HI3276 Datasheet (Intersil Corporation)

HI3276

Data Sheet June 1999

8-Bit, 160MSPS, Flash A/D Converter

The HI3276 is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of
use. With a 160MSPS encode rate capability and full-power
analog bandwidth of 250MHz, this component is ideal for
applications requiring the highest possible dynamic
performance.

To minimize system cost and pow er dissipation, only a +5V
power supply is required. The HI3276 clock input interf aces
directly to TTL, ECL or PECL logic and will operate with single­ended inputs. The user may select 16-bit demultiple xed output
or 8-bit single channel digital outputs. The demultiplex ed mode
interleaves the data through two 8-bit channels at

1

/2 the clock
rate. Operation in demultiple x ed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D
converter to be clocked to the full 160MSPS conv ersion r ate .

Fabricated with an advanced Bipolar process, the HI3276 is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20

o

C to 75oC

temperature range.

Ordering Information

PART

NUMBER

HI3276JCQ -20 to 75 48 Ld MQFP Q48.12x12-S

TEMP. RANGE

(oC) PACKAGE PKG. NO.

File Number 4717.1

Features

• Differential Linearity Error. . . . . . . . . . . . . . . . . . ±0.5 LSB

• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Low Input Capacitance. . . . . . . . . . . . . . . . . . . . . . . 10pF

• Wide Analog Input Bandwidth . . . . . . . . . . . . . . . 250MHz

• Low Power Consumption . . . . . . . . . . . . . . . . . . . 550mW

• 1:2 Demultiplexed Output Pin

1

• Internal

/2 Frequency Divider Circuit (w/Reset Function)

• CLK/2 Clock Output

• Compatible with PECL, ECL and TTL Digital Input Levels

• Direct Replacement for Sony CXA3276Q

Applications

• LCD/PDP Monitors and Projectors (RGB Video)

• Digital Oscilloscopes

• Digital Communications (QPSK, QAM)

• Magnetic Recording (PRML)

Pinout

DV

EE3

V

RB

AGND

V

RM1

AV

CC

V

V

RM2

AV

CC

V

RM3

AGND

V

RT

DGND3

HI3276 (MQFP)

TOP VIEW

RESET/E

RESETN/T

RESETN/E

1
2

3
4
5

IN

6

7
8

9
10
11
12

13 14 15 16

CLK/E

CLK/T

CLKN/E

SELECT

NCNCNC

INV

CLKOUT

CC2

DV

CC2

DV

PBD7

DGND2

PAD0

DGND2

PBD6

PAD1

PBD5

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

PAD2

PBD4

PAD3

PBD3
PBD2
PBD1
PBD0

DGND2
DV

CC2

DV

CC1

DGND1
PAD7

PAD6
PAD5
PAD4

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

Block Diagram

11

V

RT

R1

R/2
R/2

R

R

HI3276

AV

CC

5 8 30 19 31 42 12

1

2

6 BITS

INV

44

DV

CC1

DV

CC2

DGND3

(MSB)

40

PBD7

PBD6

39

PBD5

38

V

V

V

RM3

RM2

V

RM1

V

RB

63

9

7

6

IN

4

2

R/2

R

R

R

R

R

R

R

R

R

R

R

R/2

64

65

126

127

128

129

191

192

193

254

255

6 BITS

ENCODER

6 BITS

6 BITS

(8 BITS)

8 BITS

6-BIT LATCH AND ENCODER

LATCHA

LATCHB

TTLOUT

TTLOUT

PBD4

37

PBD3

36

PBD2

35

PBD1

34

P1D0

33

(LSB)

(MSB)
PAD7

28

PAD6

27

PAD5

26

PAD4

25

PAD3

24

PAD2

23

PAD1

22

PAD0

21

(LSB)

CLK/T

CLK/E

CLKN/E

RESETN/T

RESETN/E

RESET/E

15

13

14

46

48

47

3 10 45 29 20 32 41 1

AGND

DELAY

DQ

Q

SELECT

DGND2DGND1SELECT

DV

EE3

16
17
18

43

NC
NC
NC

CLKOUT

2

HI3276

Absolute Maximum Ratings T

Supply Voltage (AVCC, DV

CC1

, DV

= 25oC Thermal Information

A

) . . . . . . . . . . -0.5V to +7.0V

CC2

(DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V

(DV

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to +0.5V

EE3

(DGND3 - DV

Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . VRT - 2.7V to AV

Reference Input Voltage (VRT). . . . . . . . . . . . . . . . . +2.7V to AV

(VRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN - 2.7V to AV

) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V

EE3

CC
CC
CC

(|VRT - VRB|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V

Digital Input Voltage

PECL/ECL . . . . . . . . . . . . . . . . . . . DV

TTL. . . . . . . . . . . . . . . . . . . . . . . . . DGND3 - 0.5 to DV

- 0.5 to DGND3 + 0.5

EE3

CC1

+ 0.5

VID (|***/E - ***N/E| (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V

Recommended Operating Conditions

WITH A SINGLE POWER SUPPLY MIN TYP MAX

Supply Voltage

DV

, DV

CC1

DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V

DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

DV

EE3

Analog Input Voltage (VIN). . . . . . . . . . . . . . V

Reference Input Voltage

VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 - +2.6V

|VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 - +2.1V

Digital Input Voltage

PECL (***/E) VIH . . . . . . . . . . . . . . DV

PECL (***/E) VIL. . . . . . . . . . . . . . . DV

TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . +2.0V - -

TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . - - +0.8V

Other (SELECT) VIH . . . . . . . . . . . . . . . . - DV

Other (SELECT) VIL. . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 +0.8 -

Max Conversion Rate (fC, Straight Mode) . . . 125 - -

Max Conversion Rate (fC, DMUX Mode) . . . . 160 - -

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . -20oC to 75oC

, AVCC. . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

-V

RB

+ 1.5 DGND3

EE3

+ 1.1 VIH - 0.4V

EE3

CC1

RT

-

MSPS

MSPS

Thermal Resistance (Typical, Note 1) θJA (oC/W)

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . -

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(Lead Tips Only)

WITH DUAL POWER SUPPLIES MIN TYP MAX

Supply Voltage

DV

CC1

, DV

, AVCC. . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V

DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V

EE3

Analog Input Voltage (VIN). . . . . . . . . . . . . . V

RB

-V

RT

Reference Input Voltage

VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 - +2.6V

|VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 - +2.1V

Digital Input Voltage

PECL/ECL VIH. . . . . . . . . . . . . . . . . . . . . . . DV

PECL/ECL VIL. . . . . . . . . . . . . . . . . . . . . . . DV

+ 1.5 DGND3

EE3

+ 1.1 VIH- 0.4

EE3

TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0 - -

TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . - - +0.8V

Other (SELECT) VIH . . . . . . . . . . . . . . . . - DV

CC1

-

Other (SELECT) VIL. . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 0.8 -

Max Conversion Rate (fC, Straight Mode) . . . 125 - -

MSPS

Max Conversion Rate (fC, DMUX Mode) . . . . 160 - -

MSPS

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . -20oC to 75oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. VID: Input Voltage Differential.

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

= 0V, VRT = 4V, VRB = 2V, TA = 25oC

EE3

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Resolution - 8 - Bits

DC CHARACTERISTICS

Integral Linearity Error, INL V

IN

= 2V

, fC = 5MSPS - - ±0.5 LSB

P-P

Differential Linearity Error, DNL - - ±0.5 LSB

ANALOG INPUT

Analog Input Capacitance, C
Analog Input Resistance, R
Analog Input Current, I

IN

IN

IN

VIN = +3.0V, +0.07V

RMS

-10-pF
71535kΩ
0 100 285 µA

3

HI3276

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, D V

CC1,2

= 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued)

EE3

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE INPUT

Reference Resistance (Note 3), R
Reference Current (Note 4), I
Offset Voltage V
Offset Voltage V

Side, EOT 6 8 10 mV

RT

Side, EOB 0 1.5 3 mV

RB

REF

REF

400 600 740 Ω

2.7 3.3 5.0 mA

DIGITAL INPUT (PECL/ECL)

DV

Digital Input Voltage: High, V
Digital Input Voltage: Low, V
Threshold Voltage, V

TH

Digital Input Current: High, I
Digital Input Current: Low, I

IH

IL

IH

IL

VIH = DGND3 - 0.8V -50 - 20 µA
VIL = DGND3 - 1.6V -50 - 20 µA

+ 1.5 - DGND3 V

EE3

DV

+ 1.1 - VIH - 0.4 V

EE3

- DGND3 - 1.2 - V

Digital Input Capacitance - - 5 pF

DIGITAL INPUT (TTL)

Digital Input Voltage: High, V
Digital Input Voltage: Low, V
Threshold Voltage, V

TH

Digital Input Current: High, I
Digital Input Current: Low, I

IH

IL

IH

IL

VIH = 3.5V -10 - 0 µA
VIL = 0.2V -20 - 0 µA

2.0 - - V

- - 0.8 V

- 1.5 - V

Digital Input Capacitance - - 5 pF

DIGITAL OUTPUT (TTL)

Digital Output Voltage: High, V
Digital Output Voltage: Low, V

OH

OL

IOH = -2mA 2.4 - - V
IOL = 1mA - - 0.5 V

SWITCHING CHARACTERISTICS

Maximum Conversion Rate, f
Aperture Jitter, t
Sampling Delay, t
Clock High Pulse Width, t
Clock Low Pulse Width, t

AJ

DS

PW1

PW0

RESET Signal Setup Time, t
RESET Signal Hold Time, t
CLKOUT Output Delay, t

RH

DCLK

Data Output Delay (Note 5), t

Output Rise Time, t
Output Fall Time, t

r

f

RS

C

t

DO1
DO2

DMUX Mode 160 - - MSPS

-10-ps

1.2 1.3 1.5 ns
CLK 2.5 - - ns
CLK 2.9 - - ns
RESETN-CLK 1.0 - - ns
RESETN-CLK -0.5 - - ns
CL = 5pF 3.0 4.5 6.5 ns
DEMUX Mode (CL = 5pF) - t + 0.5 - ns

(C

= 5pF) 3.5 4.5 7.0 ns

L

0.8 to 2.0V (CL = 5pF) - 1 - ns

0.8 to 2.0V (CL = 5pF) - 1 - ns

DYNAMIC CHARACTERISTICS

Input Bandwidth V
S/N Ratio f

= 2V

IN

= 160MSPS, fIN = 1kHz Full Scale,

C

, -3dB 250 - - MHz

P-P

-46-dB

DMUX Mode

= 160MSPS, fIN = 29.999MHz Full Scale,

f

C

-42-dB

DMUX Mode

Error Rate (Note 6) f

= 160MSPS, fIN = 1kHz Full Scale,

C

--

10

-12

DMUX Mode, Error > 16 LSB

= 160MSPS, fIN = 29.999MHz Full Scale,

f

C

--

2 x 10

-8

DMUX Mode, Error > 16 LSB

= 125MSPS, fIN = 24.999MHz Full Scale,

f

C

--

10

-9

Straight Mode, Error > 16 LSB

TPS

TPS

TPS

4

HI3276

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, D V

CC1,2

= 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued)

EE3

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY OPERATING

Total Supply Current, I

Pin Supply Current, AI

AV

CC

DV

Pin Supply Current, DICC1 22 - 36 mA

CC1

Pin Supply Current, DICC2 4.0 - 15 mA

DV

CC2

DGND3 Pin Supply Current, I
Power Consumption, PD

CC

*6

+ I

EE
CC

EE

89 108 140 mA
62 - 87 mA

0.5 - 1.5 mA

480 550 700 mW

NOTES:

3.

4.

5.

: Resistance value between VRT and VRB.

R

REF

VRTVRB–

I

t

REF

-----------------------------=

R

1

-----=

.

f

C

REF

.

6.The unit of measure TPS: Times Per Sample.
P

7. .

DICCIEE

+()VCC•

VRTVRB–()

-------------------------------------+=

V

2

REF

Timing Diagrams

N - 1

V

IN

t

DS

N + 2

N + 3

CLK

PAD0 TO D7

PBD0 TO D7

CLK OUT

RESET PULSE

t

t

PW1tPW0

t

DCLK

t

PWR

N

2V

0.8V

N + 1

N - 2

N - 1

t

D02

t + 1ns

2V

0.8V

t

D01

FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC)

2V

0.8V

2V

0.8V

N

N + 1

N + 2

N + 3

5

Timing Diagrams (Continued)

HI3276

V

CLK

PAD0 TO D7

PBD0 TO D7

CLK OUT

(CLK IS INVERTED AND OUTPUT)

RESET PULSE

N - 1

IN

t

t

PW1

DS

N - 4

N - 5

t

t

DCLK

D02

8ns

t

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

t

PW0

N

N - 3

N - 2

N + 1

N - 2

N - 1

FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)

N + 2

N - 1

N

DGND3

(MAX)

V

IH

N + 3

N

N + 1

V

IL

VTH (DGND3 - 1.2V)

V

ID

V

IH

VIL (MIN)

FIGURE 3. PECL SWITCHING LEVEL

Pin Descriptions

TYPICAL

PIN NO SYMBOL I/O

3, 10 AGND GND Analog Ground. Separated from the

5, 8 AV

20, 29
32, 41

19, 30
31, 42

CC

DGND1
DGND2

DV

CC1

DV

CC2

12 DGND3 +5V (Typ) (With a Single Power

VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION

digital ground.

+5V (Typ) Analog Power Supply. Separated

from the digital power supply.

GND Digital Ground.

+5V (Typ) Digital Power Supply.

Digital Power Supply. Apply -5V for

Supply)

PECL and TTL input.

GND (With Dual Power Supplies)

6

HI3276

Pin Descriptions (Continued)

TYPICAL

PIN NO SYMBOL I/O

1DV

16, 17,

EE3

NC No Connect Pin.

18
13 CLK/E I PECL/ECL Clock Input.
14 CLK/NE I CLK/E Complementary Input. When

48 RESETN/E I Reset Input. When the input is set to

47 RESET/E I RESETN/E Complementary Input.

15 CLK/T I TTL Clock input.
46 RESETN/T I Reset Input. When left open, this

VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION

GND (With a Single Power
Supply)

Digital Power Supply. Apply -5V for
PECL and TTL input.

+5V (Typ) (With Dual Power
Supplies)

DGND3

left open, this pin goes to the
threshold potential. Only CLK/E can
be used for operation, but

13 48

4714

complementary input is recommend­ed to attain fast and stable operation.

low level, the built-in CLK frequency
divider circuit can be reset.

DV

EE3

When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.

DV

CC1

input goes to high level. When the
input is set to low level, the built-in
CLK frequency divider circuit can be

OR

44 45,

DGND1

DV

EE3

4615

reset.

1.5V

44 INV I TTL Data Output Polarity Inversion Input.

DV

CC1

When left open, this input goes to
high level. (See Table 1; I/O
Correspondence Table).

44

DGND1

DV

EE3

45 SELECT V

or Ground Data Output Mode Selection. (See

CC

DV

CC1

DGND1

DV

Table 2; Operating Mode Table).

45

EE3

7

HI3276

Pin Descriptions (Continued)

TYPICAL

PIN NO SYMBOL I/O

11 V

9V

7V

4V

RT

RM3

RM2

RM1

I 4.0V (Typ) Top Reference Voltage. Bypass to

2VRBI 2.0V (Typ) BottomReferenceVoltage. Bypassto

VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION

R1

11

3

VRB + (VRT - VRB) ReferenceVoltageMidPoint. Bypass

-- -

4
2

VRB + (VRT - VRB) ReferenceVoltageMidPoint. Bypass

-- -

4
1

VRB + (VRT - VRB) ReferenceVoltageMidPoint. Bypass

-- -

4

9

7

4

2

R2

R/2

R

COMPARATOR 1

R

COMPARATOR 63

R

COMPARATOR 64
COMPARATOR 127

R

COMPARATOR 128
COMPARATOR 191

R

COMPARATOR 192

R

COMPARATOR 255

R/2

AGNDwitha 1µF tantalcapacitorand
a 0.1µF chip capacitor.

to AGND with a 0.1µF chip capacitor.

to AGND with a 0.1µF chip capacitor.

to AGND with a 0.1µF chip capacitor.

AGNDwitha 1µF tantalcapacitorand
a 0.1µF chip capacitor.

6V

IN

33 to40PBD0 to

PBD7

21 to28PAD0 to

PAD7

43 CLKOUT O Clock Output. (See Table 2;

IVRT to V

RB

DV

AV

CC

EE3

COMPARATOR

AV

CC

6

AGND

V

REF

Analog Input.

O TTL Port 1 Side Data Output.

DV

O Port 2 Side Data Output.

CC1

DGND1

DV

CC2

21

TO

334340

TO

DGND2
DV

EE3

28

Operating Mode Table).

8

HI3276

TABLE 1. A/D CODE

INV

10

V

V

V

V

IN

RT

RM2

RB

STEP

D7 D0 D7 D0

255 1111111100000000
254 1111111000000001

•

•

•
128 1000000001111111
127 0111111110000000

•

•

•

1 0000000111111110
0 0000000011111111

•

•

•

•

•

•

•

•

•

•

•

•

Notes on Operation

• The HI3276 isa high-speed A/D conv erterwhich is capable
of TTL, ECL and PECL level cloc k input.Characteristic
impedance should be properly matchedto ensure optimum
performance during high-speed operation.

• The power supply andgrounding have a profound influence
on converter performance. The power supply and
grounding method are particularly important during high­speed operation. General points for caution are as follows:

- The ground patternshould be aslarge as possible. It is

recommended to make the power supply and ground
patterns wider at an inner layer using a multi-layer
board.

- To prevent interference between AGND and DGND
and between AV

and DVCC, make sure the

CC

respective patterns are separated. To prevent a DC
offset in the power supply pattern, connect the AV

CC

and DVCC lines at one point each, via a ferrite-bead
filter. Shorting the AGND and DGND patterns in one
place immediately under the A/D converter improves
A/D converter performance.

- Ground the powersupply pins (AV
DV

) as close to each pin as possible with a 0.1µF

EE3

or larger ceramic chip capacitor. (Connect the AV
pin to the AGND pattern and the DV
DV

pins to the DGND pattern).

EE3

CC

,DV

CC1

CC1

, DV

,DV

CC2

CC2

CC

,

- The digital output wiring should be as short as
possible. If the digital output wiring is long, the wiring
capacitance will increase,deteriorating the output slew
rate and resulting in reflection to the output waveform
since the original output slew rate is quite fast.

• The analog input pin V

has an input capacitance of

IN

approximately 10pF. To drive the A/D converter with proper
frequency response, it isnecessary to pre vent performance
deterioration due to parasitic capacitance or parasitic
inductance by using a large capacity drive circuit; keeping
wiring as short as possible, and using chip parts for
resistors and capacitors, etc.

• The V

and VRB pins must have adequate b ypass to

RT

protect them from high-frequency noise. Bypass them to
AGND with approximately 1µF tantal capacitor and, 0.1µF
capacitor.Atthistime,approximatelyDGND3- 1.2V voltage
is generated. However, this is not recommended for use as
threshold voltage V

as it is too weak.

BB

When the digital input level is PECL level, ***/E pins should
be used and ***/T pins left open. When the digital input level
is TTL, ***/T pins should be used and III/E pins left open.

,

Test Circuits

5V 5V

I

A A

CC

AV

4V

1.95V

2V

FIGURE 4. CURRENT CONSUMPTION MEASUREMENT

V

RT

V

IN

V

RB

CIRCUIT

CC

DV

CC1

DV

CC2

DGND2
DGND1
AGND

9

DGND3

CLK/E

DV

EE3

I

EE

5MHz PECL

+V

S2

-

+

-V
A < B A > B

COMPARATOR

V

IN

HI3276 BUFFER

DVM

FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL

LINEARITY ERROR MEASUREMENT CIRCUIT

8

“0”

CONTROLLER

S1: ON WHEN A < B

S1

S2: ON WHEN A > B

A8

B8

TO

TO

A1

B1
B0A0

“1”

8

000...00
TO

111..10

Test Circuits (Continued)

SIGNAL

SOURCE

2V

SIGNAL

SOURCE

100MHz

OSC1

φ: VARIABLE

f

R

OSC2

100MHz

f

C

4

SINE WAVE

P-P

-1kHz

f

AMP

V

CLK

PECL
BUFFER

V

IN

C

IN

FIGURE 7. SAMPLING DELAY/APERTURE JITTER

MEASUREMENT CIRCUIT

HI3276

CLK CLK

FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT

HI3276

8

8

1

/

8

ANALYZER

SAMPLES

LATCH

LOGIC

1024

HI3276

16 LSB

A

COMPARATOR

B

+

LATCH

V

IN

CLK

V

IN

CLK

∆υ

∆t

A > B

129
128

127
126
125

SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)

PULSE

COUNTER

V

RT

V

RM2

V

RB

(LSB)

σ

NOTE: Where σ(LSB) isthe deviation of the outputcodes when the
largest slew rate point is sampled atthe clock which hasexactly the
same frequency as the analog input signal, the aperture jitter tAJ is:



tAJ= σ /



∆υ

-------

∆t

256



--------- -

= σ/

x2πf



2

.

FIGURE 8. APERTURE JITTER MEASUREMENT METHOD

Operating Modes

The HI3276 has two types of operating modes which are selected with Pin 45 (SELECT).

TABLE 2. OPERATING MODE

OPERATING

MODE SELECT

DMUX Mode V

CC

Straight Mode GND 125MSPS Straight Output 125 MBPS The input clock is inverted and output at 100MHz.

DMUX Mode (See Application Circuits,
Figures 18, 19)

Set the SELECT pin to VCC for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is
output after being demultiplexed by this
divided clock. The
adequate setup time and hold time for the output data, is
output from the CLKOUT pin.

When using multiple HI3276 units in parallel in this mode,
differences in thestart timingof the
may cause operation as shown in Figure 9. As a
countermeasure, the HI3276 is equipped with a function which
resets the

1

clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at f

1

/2 frequency divided clock, which has

/2 frequency divided clock. When resetting this

C

MAXIMUM

CONVERSION RATE DATA OUTPUT CLOCK OUTPUT

160MSPS Demultiplexed Output 80 MBPS The input clock is1/2 frequency divided and output at

80MHz.

Straight Mode (See Application Circuits,
Figures 20, 21)

Set the SELECT pin to GND for this mode. In this mode, data

1

/2 frequency

1

/2frequency divided clock

(Min) = 160MSPS in this mode.

output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.

The A/D converter can operate at f

(Min) = 100MSPS in

C

this mode.

Digital Input Level and Supply Voltage Settings

The logic input level for the HI3276 supports PECL and TTL
levels.

The power supplies (DV
block must be set to match the logic input (CLK and RESET
signals) level.

, DGND3) for the logic input

EE3

10

DIGITAL INPUT LEVEL DV

PECL 0V +5V +5V Figures 18, 20

TTL 0V +5V +5V Figures 19, 21

HI3276

TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS

EE3

DGND3 SUPPLY VOLTAGE APPLICATION CIRCUITS

CLK

CLK

CLK

RESET PULSE

HI3276

CLK

RESETN

HI3276

CLK

RESETN

A

B

HI3276

CLK

RESETN

HI3276

CLK

RESETN

8 BITS

8 BITS

CLKOUT

DAT A

CLKOUT

DAT A

FIGURE 9. WHEN THE RESET PULSE IS NOT USED

CLK
RESET

PULSE

A

8 BITS

B

8 BITS

CLKOUT

DAT A

CLKOUT

DAT A

FIGURE 10. WHEN THE RESET PULSE IS USED

Typical Performance Curves

120

115

110

105

CURRENT CONSUMPTION (mA)

100

25-25

, AMBIENT TEMPERATURE (oC)

T

A

FIGURE 11. CURRENT CONSUMPTION vs AMBIENT

TEMPERATURE CHARACTERISTICS

11

120

115

110

105

CURRENT CONSUMPTION (mA)

100

75

f

CLK

fIN = -1kHz

4

DMUX MODE

= 5pF

C

L

, CONVERSION RATE (MSPS)

f

C

600

160

FIGURE 12. CURRENT CONSUMPTION vs CONVERSION

RATE CHARACTERISTICS RESPONSE

Typical Performance Curves (Continued)

HI3276

VRT = 4V
VRB = 2V

100

50

ANALOG INPUT CURRENT (µA)

0

234

ANALOG INPUT VOLTAGE (V)

FIGURE 13. ANALOG INPUT CURRENT vsANALOG INPUT

VOLTAGE CHARACTERISTICS

50

fC = 160MSPS

40

SNR (dB)

30

4

3

REFERENCE CURRENT (mA)

2

-25
, AMBIENT TEMPERATURE (oC)

T

A

25

FIGURE 14. REFERENCE CURRENT vs AMBIENT

TEMPERATURE CHARACTERISTICS

f

CLK

-5

10

-6

10

-7

10

-8

10

ERROR RATE (TPS)

fIN =
ERROR > 16 LSB

-1kHz

4

75

-9

20

135103050

INPUT FREQUENCY (MHz)

10

120 140 180

f

, CONVERSION RATE (MSPS)

C

FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATEvs CONVERSION RATE

CHARACTERISTICS

f

CLK

fIN =

180

ERROR > 16 LSB
ERROR RATE: 10

170

160

150

, MAXIMUM CONVERSION (MSPS)

C

140

f

-25 25 75

-1kHz

4

-8

TPS

, AMBIENT TEMPERATURE (Co)

T

A

FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS

12

Application Circuits

PECL RESET PULSE

+5V (D)

HI3276

DG

DG

DG
AG

+5V (A)

AG

+5V (A)

AG
AG

+5V (D)

PECL - CLK

2V

4V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 18. DMUX PECL INPUT

+5V (D)

DG

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26

25

DG

+5V (D)

DG

P2D0 TO P2D7
8-BIT DIGITAL DATA

8-BIT DIGITAL DATA

LATCH

8-BIT DIGITAL DATA

LATCH

TTL RESET PULSE

DG
AG
AG

+5V (A)

AG

+5V (A)

AG
AG

+5V (D)

TTL - CLK

2V

4V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 19. DMUX TTL INPUT

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26
25

DG
+5V (D)

DG

P2D0 TO P2D7
8-BIT DIGITAL DATA

8-BIT DIGITAL DATA

LATCH

8-BIT DIGITAL DATA

LATCH

13

Application Circuits (Continued)

DG

+5V (D)

HI3276

DG

DG

AG
AG

+5V (A)

AG

+5V (A)

AG
AG

+5V(D)

PECL - CLK

4V

48 47 46 45 44 43 42 41 40 39 38 37

1
2

2V

3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

+5V (D)

FIGURE 20. STRAIGHT PECL INPUT

DG

+5V (D)

DG

DG

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26
25

PECL - TTL

DG

+5V (D)

DG

8-BIT DIGITAL DATA

LATCH

DG
AG

AG

+5V (A)

AG

+5V (A)

AG
AG

+5V(D)

TTL - CLK

2V

4V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8
9

10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 21. STRAIGHT TTL INPUT

14

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26
25

DG
+5V (D)

DG

8-BIT DIGITAL DATA

LATCH

Application Circuits (Continued)

4V

+5V

+

10µF

+

-

DG(D)

13

HI3276

AG

ANALOG
INPUT

AG

V

DGND3

AG +5V (A)

+

10µF

RT

AGND

RM3

V

AV

CC

RM2

V

+ -

1µF

IN

CC

V

AV

V

+

1µF

AG

SHORT
SHORT

12 11 10 9 8 7 6 5 4 3 2 1

CLK/E

+

AG

RM1

AGND

+

-

RB

EE3

V

DV

RESETN/E

2V

48

TTL CLK

14

15

16

17

18

19

20

21

22

23

24

CLKN/E

CLK/T

NC

NC

NC

DV

CC2

DGND2

P2D0

P2D1

P2D2

P2D3

P2D4

P2D5

P2D6

P2D7

25 26 27 28 29 30 31 32 33 34 35 36

DGND1

CC1DVCC2

DV

DGND2

P1D0

P1D1

RESET/E

RESETN/T

SELECT

CLKOUT

DGND2

P1D2

P1D3

DV

P1D7

P1D6

P1D5

P1D4

INV

CC2

47

46

45

44

43

42

41

40

39

38

37

P1D1

P2D1

(LSB) P2D0

P2D2

P2D3

SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY
UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION

IS THE CHIP CAPACITOR OF 0.1µF.

P2D4

P2D5

P2D6

(MSB) P2D7

(LSB) P1D0

P1D2

FIGURE 22. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED)

15

P1D3

P1D4

P1D5

P1D6

(MSB) P1D7

HI3276

Metric Plastic Quad Flatpack Packages (MQFP/PQFP)

EE1

-H-

0o-10

D

D1

Q48.12x12-S

48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A 0.081 0.100 2.05 2.55 -

A1 0.000 0.011 0.00 0.30 -

B 0.008 0.017 0.20 0.45 5
D 0.587 0.618 14.90 15.70 2

D1 0.469 0.488 11.90 12.40 3, 4

E 0.587 0.618 14.90 15.70 2

E1 0.469 0.488 11.90 12.40 3, 4

L 0.028 0.043 0.70 1.10 -

N48 486

e

e 0.032 BSC 0.80 BSC -

Rev. 0 2/96

PIN 1

SEATING

PLANE

A

0.15

0.006

M

0.24

o

A1

-C-

B

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

2. Dimensions D and E to be determined at seating plane .

-C-

3. Dimensions D1 and E1 to be determined at datum plane .

4. Dimensions D1 and E1 do not include mold protrusion.

5. Dimension B does not include dambar protrusion.

6. “N” is the number of terminal positions.

-H-

L

0.10/0.25

0.004/0.010

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are soldby description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for itsuse; nor for any infringements of patents or other rights of third parties which mayresult
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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16