Datasheet HI3026A Datasheet (Intersil Corporation)

HI3026A

August 1997

Features

• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB

• Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Integral Linearity Compensation Circuit

• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . 21pF

• Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz

• Low Power Consumption . . . . . . . . . . . . . . . . . 790mW

1

• Internal

/2 Frequency Divider Circuit (With Reset

Function)

• CLK/2 Clock Output Pin

• Compatible with ECL, PECL and TTL Digital Input Levels

• 1:2 Demultiplexed Output

• Direct Replacement for Sony CXA3026A

Applications

• RGB Graphics Processing (LCD, PDP)

• Digital Oscilloscopes

• Digital Communications (QPSK, QAM)

• Magnetic Recording (PRML)

8-Bit, 140 MSPS, Flash A/D Converter

Description

The HI3026A is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of
use. With a 140 MSPS encode rate capability and full-power
analog bandwidth of 150MHz, this component is ideal for appli­cations requiring the highest possible dynamic performance.

To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3026A’s clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with single­ended inputs. The user may select 16-bit demultiplexed output
or 8-bit single-channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D
converter to be clocked to the full 140 MSPS conv ersion r ate .

Fabricated with an advanced bipolar process, the HI3026A is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20
temperature range.

Ordering Information

PART

NUMBER

HI3026AJCQ -20 to 75 48 Ld MQFP Q48.12x12-S
HI3026AEVAL 25 Evaluation Board

TEMPT.

RANGE (oC) PACKAGE PKG. NO.

1

/2 the clock

o

C to 75oC

Pinout

DV

EE3

V

RB

AGND

V

RM1

AV

CC

V

V

RM2

AV

CC

V

RM3

AGND

V

RT

DGND3

HI3026A (MQFP)

TOP VIEW

CC2

RESET/E

RESET/T

INV

RESETN/E

1
2

3
4
5

IN

6
7

8
9
10

11
12

13 14 15 16

CLK/E

CLKN/E

CLK/T

SELECT

NC

NC

CLKOUT

NC

DV

CC2

DV

P1D7

DGND2

P2D0

DGND2

P1D6

P2D1

P1D5

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

P2D2

P1D4

P2D3

P1D3
P1D2
P1D1
P1D0

DGND2
DV

CC2

DV

CC1

DGND1
P2D7

P2D6
P2D5
P2D4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

4-1378

File Number

4246

Block Diagram

11

V

RT

R1

9

V

RM3

7

V

RM2

R/2
R

R

R

R

R

R

R

R

HI3026A

AV

CC

5 8 44 30 12

1

63

64

65

126

127

2

.
.
.

.
.
.

6 BITS

6 BITS

INV

8 BITS

DV

CC1

8 BITS

LATCHA

DV

CC2

19 31 42

DGND3

TTLOUT

(MSB)

40

P1D7

39

P1D6

38

P1D5

37

P1D4

36

P1D3

35

P1D2

34

P1D1

33

P1D0
(LSB)

V

V

RM1

V

RB

CLK/T

CLK/E

CLKN/E

RESETN/T

6

IN

4

2

15

13

14

46

R

R

R

R

R

R

R/2

R2

128

129

191

192

193

254

255

.
.
.

.
.
.

ENCODER

6 BITS

6 BITS

DELAY

DQ

Q

6-BIT LATCH + ENCODER

SELECT

LATCHB

TTLOUT

28

27

26

25

24

23

22

21

16
17
18

43

(MSB)
P2D7

P2D6

P2D5

P2D4

P2D3

P2D2

P2D1

P2D0
(LSB)

NC

CLKOUT

RESETN/E

RESET/E

48

47

3 10 45 29 20 32 41 1
AGND

DGND2DGND1SELECT

DV

EE3

4-1379

HI3026A

Absolute Maximum Ratings T

Supply Voltage

AVCC, DV

DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

DV

EE3

DGND3 - DV

Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . .VRT - 2.7V to AV

, DV

CC1

. . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

CC2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

EE3

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

MQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

CC

(MQFP - Lead Tips Only)

Reference Input Voltage

VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to AV

VRB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AV

CC
CC

|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V

Digital Input Voltage

ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . .DV

EE3

to 0.5V

PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3

TTL (***/T, INV). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV

Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV

CC1
CC1

VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . .2.7V

Recommended Operating Conditions

WITH A SINGLE POWER SUPPLY MIN TYP MAX

Supply Voltage

DV

CC1

, DV

, AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V

DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

EE3

Analog Input Voltage (VIN) . . . . . . . . . . . . . . V

RB

-V

Reference Input Voltage

VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V

|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V

Digital Input Voltage

PECL (***/E) VIH. . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V

PECL (***/E) VIL. . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V

TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . . 2.0V - -

TTL (***/T, INV) VIL. . . . . . . . . . . . . . . . . . - - 0.8V

Other (SELECT) VIH. . . . . . . . . . . . . . . . . - DV

CC1

Other (SELECT) VIL. . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 3) (|***/E- ***N/E|). . . . . . . . . . . 0.4 0.8 -

Max Conversion Rate (fC, Straight Mode) . . . 100 - -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS

Max Conversion Rate (fC, DMUX Mode) . . . . 140 - -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. ***/E and ***T indicate CLK/E and CLK/T, etc. for the pin name.

3. VID: Input Voltage Differential.

WITH DUAL POWER SUPPLIES MIN TYP MAX

Supply Voltage

DV

CC1

, DV

, AVCC . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

DGND1, DGND2, AGND. . . . . . . . . . . . . -0.05 0 +0.05V

DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V

EE3

Analog Input Voltage (VIN) . . . . . . . . . . . . . V

RT

RB

Reference Input Voltage

VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V

|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V

Digital Input Voltage

ECL (***/E) VIH DGND3 . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V

ECL (***/E) VIL DGND3. . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V

TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . 2.0V - -

TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . - - 0.8V

-

Other (SELECT) VIH . . . . . . . . . . . . . . . . - DV

Other (SELECT) VIL . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 -

Max Conversion Rate (fC, Straight Mode). . . 100 - -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS

Max Conversion Rate (fC, DMUX Mode). . . . 140 - -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC

-V

CC1

RT

-

Electrical Specifications DV

TA = 25oC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Resolution

DC CHARACTERISTICS

Integral Linearity Error
Differential Linearity Error

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

E

E

DL

VIN = 2V

IL

, fC = 5 MSPS - - ±0.5 LSB

P-P

4-1380

= 0V, VRT = 4V, VRB = 2V,

EE3

- 8 - Bits

--±0.5 LSB

HI3026A

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

= 0V, VRT = 4V, VRB = 2V,

EE3

TA = 25oC (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT

Analog Input Capacitance C
Analog Input Resistance R
Analog Input Current I

VIN = +3.0V + 0.07V

IN

IN

IN

RMS

-21-pF
4 - 50 kΩ
0 - 500 µA

REFERENCE INPUT

Reference Resistance (Note 4) R
Reference Current (Note 5) I
Offset Voltage, V
Offset Voltage, V

Side EOT 2 - 15 mV

RT

Side EOB 2 - 10 mV

RB

REF

REF

75 115 155 Ω

9.7 17.4 28 mA

DIGITAL INPUT (ECL, PECL)

Digital Input Voltage: High V
Digital Input Voltage: Low V
Threshold Voltage V
Digital Input Current: High I
Digital Input Current: Low I

IH

IL

TH

VIH = DGND3 - 0.8V -50 - +50 µA

IH

VIL = DGND3 - 1.6V -75 - 0 µA

IL

DGND3 - 1.05 - DGND3 - 0.5 V

DGND3 - 3.2 - DGND3 - 1.4 V

- DGND3 - 1.2 - V

Digital Input Capacitance - - 5 pF

DIGITAL INPUT (TTL)

Digital Input Voltage: High V
Digital Input Voltage: Low V
Threshold Voltage V
Digital Input Current: High I
Digital Input Current: Low I

IH

IL

TH

VIH = 3.5V -50 - 0 µA

IH

VIL = 0.2V -500 - 0 µA

IL

2.0 - - V

- - 0.8 V

- 1.5 - V

Digital Input Capacitance - - 5 pF

DIGITAL OUTPUT (TTL)

Digital Output Voltage: High V
Digital Output Voltage: Low V

IOH = -2mA 2.4 - - V

OH

IOL = 1mA - - 0.5 V

OL

SWITCHING CHARACTERISTICS

Maximum Conversion Rate f
Aperture Jitter t
Sampling Delay t
Clock High Pulse Width t
Clock Low Pulse Width t
Reset Pulse Width (Note 6) t
RESETN_CLK Setup t_
CLKOUT Output Delay t

DCLK

Data Output Delay (Note 6) t

t
Output Rise Time t
Output Fall Time t

DS
PW1
PW0

PWR

RST

DO1
DO2

DMUX Mode 140 - - MSPS

C

AJ

-10-ps

3 4.5 6 ns
CLK 2.8 - - ns
CLK 2.8 - - ns
RESETN t x 2 - - ns
RESETN-CLK 3.5 - - ns
(CL = 5pF) 3.5 7 9 ns
DMUX Mode (CL = 5pF) t t + 1 t + 2 ns
(CL = 5pF) 4.5 8 10 ns

0.8V to 2.0V (CL = 5pF) - 2 - ns

r

0.8V to 2.0V (CL = 5pF) - 2 - ns

f

DYNAMIC CHARACTERISTICS

Input Bandwidth V
S/N Ratio f

= 2V

IN

= 140 MSPS, fIN = 1kHz

C

, -3dB 150 - - MHz

P-P

-46-dB

Full Scale, DMUX Mode

= 140 MSPS, fIN = 34.999MHz

f

C

-40-dB

Full Scale, DMUX Mode

4-1381

HI3026A

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

TA = 25oC (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Error Rate fC = 140 MSPS, fIN = 1kHz

Full Scale, DMUX Mode,
Error > 16 LSB

= 140 MSPS,

f

C

fIN = 34.999MHz Full Scale,
DMUX Mode, Error > 16 LSB

= 100 MSPS,

f

C

fIN = 24.999MHz Full Scale,
Straight Mode, Error > 16 LSB

POWER SUPPLY

Supply Current I
Supply Current I
Power Consumption (Note 8) P

CC
EE

D

NOTES:

4.

R

: Resistance value between VRT and VRB.

REF

REF

VRTVRB–

-----------------------------=

R

1

-----=

.

f

C

REF

.

I

5.

t

6.

7. TPS = Times Per Sample.

2

–()

V

P

8. .

DICCIEE

+()VCC•

RTVRB

-------------------------------------+=

V

REF

= 0V, VRT = 4V, VRB = 2V,

EE3

--

--

--

10

10

10

-12

-9

-9

TPS

TPS

TPS

(Note 7)

130 150 190 mA

0.4 0.6 0.8 mA

690 790 990 mW

Timing Waveforms

V

IN

CLK

P1D0 TO D7

P2D0 TO D7

CLK OUT

N - 1

t

DS

4.5ns
t

t

PW1tPW0

t

DCLK

7ns

2.0V

0.8V

N + 2

N

N + 1

N - 2

N - 3

t

DO2

8ns

t

T + 1ns

2.0V

0.8V

DO1

N + 3

2.0V

0.8V

2.0V

0.8V

N

N - 1

N + 2

N + 1

RESET PULSE

t

PWR

FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC)

4-1382

Timing Waveforms (Continued)

HI3026A

V

CLK

P1D0 TO D7

P2D0 TO D7

CLK OUT

(CLK IS INVERTED AND OUTPUT)

RESET PULSE

N - 1

IN

t

t

PW1

DS

N - 4

N - 5

t

t

DCLK

DO2

t

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

t

PW0

N

N - 3

N - 4

N + 1

N - 2

N - 3

FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)

N + 2

N - 1

N - 2

N + 3

N

N - 1

DGND3

(MAX)

V

IH

V

IL

VTH (DGND3 -1.2V)

V

ID

V

IH

VIL (MIN)

FIGURE 3. ECL AND PECL SWITCHING LEVEL

Pin Descriptions

TYPICAL

VOLTAGE

PIN NO SYMBOL I/O

3, 10 AGND GND Analog Ground. Separated from the digital

5, 8 AV

20, 29
32, 41

19, 30
31, 42

CC

DGND1
DGND2

DV

CC1

DV

CC2

LEVEL EQUIVALENT CIRCUIT DESCRIPTION

ground.

+5V (Typ) Analog Power Supply. Separated from the

digital power supply.

GND Digital Ground.

+5V (Typ) Digital Power Supply.

4-1383

HI3026A

Pin Descriptions (Continued)

TYPICAL

VOLTAGE

PIN NO SYMBOL I/O

12 DGND3 +5V (Typ) (With a

1DV

16, 17,

EE3

NC No Connect pin. Not connected with the

18
13 CLK/E I ECL/PECL Clock Input.
14 CLKN/E I CLK/E Complementary Input. When left

48 RESETN/E I Reset Input. When the input is set to low

47 RESET/E I RESETN/E Complementary Input. When left

15 CLK/T I TTL Clock Input.
46 RESETN/T I Reset Input. When left open, this input

LEVEL EQUIVALENT CIRCUIT DESCRIPTION

Digital Power Supply. Ground for ECL

Single Power

input. +5V for PECL and TTL input.

Supply)
GND (With Dual

Power Supplies)
GND (With a Single

Power Supply)

Digital Power Supply. -5V for ECL input.
Ground for PECL and TTL Input

-5V (Typ) (With
Dual Power
Supplies)

internal circuits.

DGND3

open, this pin goes to the threshold

RR

13 48

4714

potential. Only CLK/E can be used for
operation, but complementary input is
recommended to attain fast and stable
operation.

level, the built-in CLK frequency divider
circuit can be reset.

DV

DV

1.2V

EE3

CC1

RR

R/2

open, this pin goes to the threshold voltage.
Only RESETN/E can be used for operation.

goes to high level. When the input is set to
low level, the b uilt-in CLK frequency divider
circuit can be reset.

4615

DGND1

DV

EE3

44 INV I TTL Data Output Polarity Inversion Input. When

DV

CC1

1.5V

R

left open, this input goes to high level. (See
Table 1, I/O Correspondence Table.)

44

DGND1

DV

EE3

4-1384

HI3026A

Pin Descriptions (Continued)

TYPICAL

VOLTAGE

PIN NO SYMBOL I/O

45 SELECT VCC or GND Data Output Mode Selection. (See Table 2,

LEVEL EQUIVALENT CIRCUIT DESCRIPTION

DV

CC1

45

DGND1

DV

EE3

Operating Mode Table.)

11 V

9V

7V

4V

RT

RM3

RM2

RM1

2VRBI 2.0V (Typ) Bottom Reference Voltage. Bypass to

6VINIVRT to V

I 4.0V (Typ) Top Reference Voltage. By-pass to AGND

VRB +

3

-- -

(VRT - VRB)

4

VRB +

2

-- -

(VRT - VRB)

4

VRB +

1

(VRT - VRB)

-- -

4

RB

AV

R1

11

R/2

R

COMPARATOR 1

R

9

7

4

2

R2

CC

COMPARATOR 63

R

COMPARATOR 64
COMPARATOR 127

R

COMPARATOR 128
COMPARATOR 191

R

COMPARATOR 192

R

COMPARATOR 255

R2

COMPARATOR

AV

CC

with a 1µF tantal capacitor and a 0.1µF
chip capacitor.

Reference Voltage Mid Point. Bypass to
AGND with a 0.1µF chip capacitor.

Reference Voltage Mid Point. Bypass to
AGND with a 0.1µF chip capacitor.

Reference Voltage Mid Point. Bypass to
AGND with a 0.1µF chip capacitor.

AGND with a 1µF tantal capacitor and a

0.1µF chip capacitor.

Analog Input.

6

AGND

DV

EE3

33 to 40 P1D0 to

P1D7

21 to 28 P2D0 to

O TTL Port 1 Side Data Output.

DV

CC1

O Port 2 Side Data Output.

P2D7

43 CLKOUT O Clock Output. (See Table 2, Operating

V

REF

DV

CC2

21

TO

334340

TO

28

Mode Table.)

100K

DGND1

DGND2
DV

EE3

4-1385

HI3026A

TABLE 1. A/D CODE TABLE

INV

10

V

V

V

V

IN

RT

RM2

RB

STEP

D7 D0 D7 D0

255 1111111100000000
254 1111111000000001

•

•

•
128 1000000001111111
127 0111111110000000

•

•

•

1 0000000111111110
0 0000000011111111

•

•

•

•

•

•

•

•

•

•

•

•

Notes On Operation

• The HI3026A is a high-speed A/D converter which is
capable of TTL, ECL and PECL level clock input. Charac­teristic impedance should be properly matched to ensure
optimum performance during high-speed operation.

• The power supply and grounding have a profound
influence on converter performance. The power supply
and grounding method are particularly important during
high-speed operation. General points for caution are as
follows:

- The ground pattern should be as large as possible. It is

recommended to make the power supply and ground

patterns wider at an inner layer using a multi-lay er board.

- To prevent interference between AGND and DGND and
between A V

and DVCC, make sure the respective pat-

CC

terns are separated. To prevent a DC offset in the power
supply pattern, connect the AV

and DVCC lines at one

CC

point each via a ferrite-bead filter. Shorting the AGND
and DGND patterns in one place immediately under the
A/D converter improves A/D converter performance.

- Ground the power supply pins (AV
DV

) as close to each pin as possible with a 0.1µF or

EE3

larger ceramic chip capacitor. (Connect the AV
the AGND pattern and the DV

CC1

CC

, DV

, DV

CC2

CC1

, DV

, DV

CC

EE3

CC2

pin to

pins

to the DGND pattern.)

- The digital output wiring should be as short as possible.
If the digital output wiring is long, the wiring capacitance
will increase, deteriorating the output slew rate and
resulting in reflection to the output waveform since the
original output slew rate is quite fast.

• The analog input pin V

has an input capacitance of

IN

approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent per­formance deterioration due to parasitic capacitance or
parasitic inductance by using a large capacity drive circuit,
keeping wiring as short as possible, and using chip parts
for resistors and capacitors, etc.

• The V

and VRB pins must have adequate bypass to

RT

protect them from high-frequency noise. Bypass them to
AGND with approximately 1µF tantal capacitor and, 0.1µF
capacitor as short as possible.

• When the digital input level is ECL or PECL level, ***/E
pins should be used and ***/T pins left open. When the
digital input level is TTL, ***/T pins should be used and
III/E pins left open.

,

Test Circuits

5V 5V

I

A A

CC

AV

4V

1.95V

2V

FIGURE 4. CURRENT CONSUMPTION MEASUREMENT

V

RT

V

IN

V

RB

CIRCUIT

CC

DV

CC1

DV

CC2

DGND2
DGND1
AGND

DGND3

CLK/E

DV

EE3

I

EE

5MHz PECL

+V

S2

-

+

-V
A < B A > B

V

IN

HI3026A BUFFER

DVM

FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL

LINEARITY ERROR MEASUREMENT CIRCUIT

COMPARATOR

8

“0”

CONTROLLER

S1: ON WHEN A < B
S2: ON WHEN A > B

S1

A8

B8

TO

TO

A1

B1
B0A0

8

“1”

000...00
TO

111..10

4-1386

Test Circuits (Continued)

HI3026A

SIGNAL

SOURCE

f

C

-1kHz

4

2V

SINE WAVE

P-P

SIGNAL

SOURCE

V

IN

f

C

HI3026A LATCH

CLK CLK

8

1

/

8

FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT

100MHz

OSC1

φ: VARIABLE

f

R

OSC2

100MHz

AMP

V

CLK

ECL
BUFFER

IN

HI3026A

8

FIGURE 7. SAMPLING DELAY/APERTURE JITTER

MEASUREMENT CIRCUIT

16 LSB

LOGIC

ALALYZER

1024

SAMPLES

A

COMPARATOR

A > B

B

V

CLK

V

CLK

LATCH

IN

IN

∆V
∆t

129
128

127
126
125

SAMPLING TIMING FLUCTUATION

(= APERTURE JITTER)

+

PULSE

COUNTER

V

RT

V

RM2

V

RB

(LSB)

σ

NOTE: Whereσ (LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter, tAJ is:

tAJ=

σ/∆V



------------- -



∆t

256



--------- -

= σ/

x2πf



2

.

FIGURE 8. APERTURE JITTER MEASUREMENT METHOD

Operating Modes

The HI3026A has two types of operating modes which are selected with Pin 45 (SELECT).

TABLE 2. OPERATING MODE TABLE

OPERATING

MODE SELECT

DMUX Mode V

CC

Straight Mode GND 100 MSPS Straight Output 100 Mbps The input clock is inverted and

DMUX Mode (See Application Circuits, Figures 18, 19, 20)

Set the SELECT pin to V

for this mode. In this mode, the

CC

clock frequency is divided by 2 in the IC, and the data is out­put after being demultiplexed by this
clock. The

1

/2 frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.

When using multiple HI3026A units in parallel in this mode,
differences in the start timing of the

1

/2 frequency divided clock
may cause operation as shown in the figure below. As a
countermeasure, the HI3026A is equipped with a function

MAXIMUM

CONVERSION RATE DATA OUTPUT CLOCK OUTPUT

140 MSPS Demultiplexed Output 70 Mbps The input clock is1/2 frequency

divided and output at 70MHz.

output at 100MHz.

which resets the

1

/2 frequency divided clock. When resetting
this clock, the RESET pulse must be input to the RESET pin.
See the Timing Charts for the RESET pulse input timing. The

1

/2 frequency divided

A/D converter can operate at f
mode.

(Min) = 140 MSPS in this

C

Straight Mode (See Application Circuits, Figures 21, 22, 23)

Set the SELECT pin to GND for this mode. In this mode, data
output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.

4-1387

HI3026A

The A/D converter can operate at f

(Min) = 100 MSPS in

C

this mode.

Digital Input Level and Supply Voltage Settings

The logic input level for the HI3026A supports ECL, PECL
and TTL levels.

The power supplies (DV

, DGND3) for the logic input

EE3

block must be set to match the logic input (CLK and RESET
signals) level.

CLK

CLK

CLK

HI3026A

CLK

RESETN

HI3026A

CLK

RESETN

A

B

HI3026A

CLK

RESETN

8 BITS

8 BITS

FIGURE 9. WHEN THE RESET PULSE IS NOT USED

A

CLKOUT

DAT A

CLKOUT

DAT A

CLK
RESET

PULSE
CLKOUT

8 BITS

DAT A

TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY

SETTINGS

DIGITAL

INPUT

LEVEL DV

EE3

DGND3

SUPPLY

VOLTAGE

APPLICATION

CIRCUITS

(FIGURE)

ECL -5V 0V ±5V (18) (21)

PECL 0V +5V +5V (19) (22)

TTL 0V +5V +5V (20) (23)

HI3026A

CLK

RESET PULSE

RESETN

B

8 BITS

FIGURE 10. WHEN THE RESET PULSE IS USED

Typical Performance Curves

170

160

150

140

CURRENT CONSUMPTION (mA)

130

-25 25 75
AMBIENT TEMPERATURE (

FIGURE 11. CURRENT CONSUMPTION vs AMBIENT

TEMPERATURE CHARACTERISTICS

o

C)

CLKOUT

DAT A

170

160

150

f

CLK

140

CURRENT CONSUMPTION (mA)

130

0 70 140

CONVERSION RATE (MSPS)

fIN =

DMUX MODE

= 5pF

C

L

-1kHz

4

FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE

CHARACTERISTICS RESPONSE

4-1388

Typical Performance Curves (Continued)

HI3026A

200

VRT = 4V

= 2V

V

RB

100

ANALOG INPUT CURRENT (µA)

0

234

ANALOG INPUT VOLTAGE (V)

FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT

REFERENCE CURRENT (mA)

FIGURE 14. REFERENCE CURRENT vs AMBIENT

VOLTAGE CHARACTERISTICS

50

fC = 140 MSPS

40

20

15

10

-25 25 75
AMBIENT TEMPERATURE (

o

C)

TEMPERATURE CHARACTERISTICS

-6

10

-7

10

f

fIN =
ERROR > 16 LSB

CLK

4

-1kHz

-8

10

SNR (dB)

30

20

135103050

INPUT FREQUENCY (MHz)

-9

10

ERROR RATE (TPS)

-10

10

140 160 180

CONVERSION RATE (MSPS)

FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATE vs CONVERSION RATE

CHARACTERISTICS

180

170

160

150

MAXIMUM CONVERSION (MSPS)

140

-25 25 75

f

CLK

fIN =

ERROR > 16 LSB
ERROR RATE: 10

-1kHz

4

AMBIENT TEMPERATURE (C

-9

TPS

o

)

FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS

4-1389

Typical Application Circuits

ECL RESET PULSE

HI3026A

+5V (D)

DG

-5V (D)
AG

AG

+5V (A)

AG

+5V (A)

AG
AG

DG

ECL - CLK

4V

2V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 18. DMUX ECL INPUT

+5V (D)

DG

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26
25

DG
+5V (D)

DG

P2D0 TO P2D7
8-BIT DIGITAL DATA

8-BIT DIGITAL DATA

LATCH

8-BIT DIGITAL DATA

LATCH

PECL RESET PULSE

DG
AG

AG

+5V (A)

AG

+5V (A)

AG
AG

+5V (D)

PECL - CLK

4V

2V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 19. DMUX PECL INPUT

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26
25

DG

+5V (D)

DG

P2D0 TO P2D7
8-BIT DIGITAL DATA

8-BIT DIGITAL DATA

LATCH

8-BIT DIGITAL DATA

LATCH

4-1390

Typical Application Circuits (Continued)

+5V (D)

TTL RESET PULSE

HI3026A

DG

DG
AG

AG

+5V (A)

AG

+5V (A)

AG
AG

+5V (D)

TTL - CLK

2V

4V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 20. DMUX TTL INPUT

DG

+5V (D)

DG

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26

25

DG
+5V (D)

DG

P2D0 TO P2D7
8-BIT DIGITAL DATA

8-BIT DIGITAL DATA

LATCH

8-BIT DIGITAL DATA

LATCH

-5V (D)
AG

AG

+5V (A)

AG

+5V (A)

AG
AG

DG

ECL - CLK

4V

2V

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

+5V (D)

FIGURE 21. STRAIGHT ECL INPUT

4-1391

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26

25

ECL - TTL

DG
+5V (D)

DG

8-BIT DIGITAL DATA

LATCH

Typical Application Circuits (Continued)

HI3026A

DG

AG
AG

+5V (A)

AG

+5V (A)

AG
AG

+5V(D)

PECL - CLK

4V

2V

DG

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

+5V (D)

DG

DG

+5V (D)

FIGURE 22. STRAIGHT PECL INPUT

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26

25

PECL - TTL

DG
+5V (D)

DG

8-BIT DIGITAL DATA

LATCH

DG

AG
AG

+5V (A)

AG

+5V (A)

AG
AG

+5V(D)

TTL - CLK

2V

4V

+5V (D)

DG

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11

12

13 14 15 16 17 18 19 20 21 22 23 24

DG

DG

+5V (D)

FIGURE 23. STRAIGHT TTL INPUT

36

P1D0 TO P1D7
8-BIT DIGITAL DATA

35
34
33
32
31
30
29
28
27
26

25

DG

+5V (D)

DG

8-BIT DIGITAL DATA

LATCH

4-1392

Typical Application Circuits (Continued)

10µF

4V

+5V

+

+

-

DG(D)

13

+

1µF

AG

SHORT
SHORT

12 11 10 9 8 7 6 5 4 3 2 1

RT

V

DGND3

CLK/E

HI3026A

AG +5V(A)

+

10µF

RM3

V

AGND

AV

CC

AG

AG

RM2

V

+ -

ANALOG
INPUT

IN

V

AV

CC

1µF

RM1

V

+

AG

AGND

+

-

RB

V

DV

RESETN/E

2V

EE3

48

TTL CLK

14

15

16

17

18

19

20

21

22

23

24

CLKN/E

CLK/T

NC

NC

NC

DV

CC2

DGND2

P2D0

P2D1

P2D2

P2D3

P2D4

P2D5

P2D6

25 26 27 28 29 30 31 32 33 34 35 36

P2D7

DGND1

CC1DVCC2

DV

DGND2

P1D0

P1D1

RESET/E

RESETN/T

SELECT

CLKOUT

P1D2

P1D3

INV

DV

CC2

DGND2

P1D7

P1D6

P1D5

P1D4

47

46

45

44

43

42

41

40

39

38

37

P1D1

P2D1

(LSB) P2D0

P2D2

P2D3

SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY
UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION.

IS THE CHIP CAPACITOR OF 0.1µF.

P2D4

P2D5

P2D6

(MSB) P2D7

(LSB) P1D0

P1D2

FIGURE 24. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED)

4-1393

P1D3

P1D4

P1D5

P1D6

(MSB) P1D7

HI3026A

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

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