Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
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January 1995 2
Philips Semiconductors Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4555B
MSI
DESCRIPTION
The HEF4555B is a dual 1-of-4 decoder/demultiplexer.
Each has two address inputs (A0and A1), an active LOW
enable input (E) and four mutually exclusive outputs which
are active HIGH (O0to O3). When used as a decoder,
E when HIGH, forces O0to O3LOW. When used as a
demultiplexer, the appropriate output is selected by the
information on A0and A1with E as data input. All
unselected outputs are LOW.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
HEF4555BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4555BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4555BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
E enable inputs (active LOW)
A
0
and A1address inputs
O
0
to O
3
outputs (active HIGH)
Fig.2 Pinning diagram.
Page 3
January 1995 3
Philips Semiconductors Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4555B
MSI
TRUTH TABLE
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
INPUTS OUTPUTS
EA0A1O0O1O2O
3
LL L H L L L
LH L L H L L
LL H L L H L
LH H L L L H
HX X L L L L
Fig.3 Logic diagram (one decoder/multiplexer).
Page 4
January 1995 4
Philips Semiconductors Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4555B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤20 ns
APPLICATION INFORMATION
Some examples of applications for the HEF4555B are:
• Code conversion.
• Address decoding.
• Demultiplexing: when using the enable input as data input.
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
An→ O
n
5 115 230 ns 88 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
45 90 ns 34 ns + (0,23 ns/pF) C
L
15 30 65 ns 22 ns + (0,16 ns/pF) C
L
5 140 280 ns 113 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
55 105 ns 44 ns + (0,23 ns/pF) C
L
15 40 75 ns 32 ns + (0,16 ns/pF) C
L
En→ O
n
5 125 250 ns 98 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
50 95 ns 39 ns + (0,23 ns/pF) C
L
15 30 65 ns 22 ns + (0,16 ns/pF) C
L
5 150 295 ns 123 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
55 110 ns 44 ns + (0,23 ns/pF) C
L
15 40 75 ns 32 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + ((1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 4500 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 18 800 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 45 700 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
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