Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4522B
MSI
Programmable 4-bit BCD down
counter
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
DESCRIPTION
The HEF4522B is a synchronous programmable 4-bit
BCD down counter with an active HIGH and an active
LOW clock input (CP0, CP1), an asynchronous parallel
load input (PL), four parallel inputs (P0to P3), a cascade
feedback input (CF), four buffered parallel outputs (O0to
O3), a terminal count output (TC) and an overriding
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
HEF4522B
MSI
Information on P
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL andCP1are LOW, the
counter advances on a LOW to HIGH transition of CP0.
When PL is LOW and CP0 is HIGH, the counter advances
on a HIGH to LOW transition of CP1. TC is HIGH when the
counter is in the zero state (O0=O1=O2=O3= LOW)
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O0to O3= LOW) independent of other input
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
to P3 is loaded into the counter while PL
0
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Page 3
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
Fig.2 Pinning diagram.
PINNING
PL parallel load input
P
to P
0
3
CF cascade feedback input
CP
0
CP
1
MR asynchronous master reset input
TC terminal count output
O
to O
0
parallel inputs
clock input (LOW to HIGH, triggered)
clock input (HIGH to LOW, triggered)
buffered parallel outputs
3
HEF4522B
MSI
HEF4522BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4522BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4522BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
COUNTING MODE
CF = HIGH; PL = LOW; MR = LOW
OUTPUTS
COUNT
O
3
O
2
O
1
O
0
9HLLH
8HLLL
7LHHH
6LHHL
5LHLH
4LHLL
3LLHH
2LLHL
1LLLH
0LLLL
January 1995 3
FUNCTION TABLE
MR PL CP
CP
0
1
MODE
H X X X reset (asynchronous)
L H X X preset (asynchronous)
L L H no change
L L L no change
L L X no change
L L X no change
L L L counter advances
L L H counter advances
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
Page 4
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
SINGLE STAGE OPERATION
Divide-by-n; MR = LOW; CF = HIGH;
PL P
LXXX X 10
TC H H H H 15
TC H H H L 14
TC H H L H 13
TC H H L L 12
TC H L H H 11
TC H L H L 10
TC H L L H 9
TC H L L L 8
TC L H H H 7
TC L H H L 6
TC L H L H 5
TC L H L L 4
TC L L H H 3
TC L L H L 2
TC L L L H 1
TC L L L L no operation
P
3
P
2
1
CP1= LOW
P
0
DIVIDE
BY
HEF4522B
MSI
TC OUTPUT
PULSE WIDTH
one clock
period
clock pulse
HIGH
Fig.3 State diagram.
January 1995 4
Page 5
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January 1995 5
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
Fig.4 Logic diagram.
HEF4522B
MSI
Page 6
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
HEF4522B
MSI
AC CHARACTERISTICS
V
= 0 V; T
SS
Dynamic power 5 1000 f
dissipation per 10 4000 f
package (P) 15 10 000 f
AC CHARACTERISTICS
=0V; T
V
SS
Propagation delays
CP0, CP1→ O
HIGH to LOW 10 t
LOW to HIGH 10 t
CP0, CP1→ TC 5 210 420 ns 183 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
PL → O
HIGH to LOW 10 t
LOW to HIGH 10 t
MR → O
HIGH to LOW 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
TYPICAL FORMULA FOR P (µW)
i
i
i
SYMBOL MIN. TYP. MAX.
5 150 300 ns 123 ns + (0,55 ns/pF) C
PHL
15 50 100 ns 42 ns + (0,16 ns/pF) C
5 150 300 ns 123 ns + (0,55 ns/pF) C
PLH
15 50 100 ns 42 ns + (0,16 ns/pF) C
PHL
15 70 140 ns 62 ns + (0,16 ns/pF) C
5 210 420 ns 183 ns + (0,55 ns/pF) C
PLH
15 70 140 ns 62 ns + (0,16 ns/pF) C
n
5 200 400 ns 173 ns + (0,55 ns/pF) C
PHL
15 60 120 ns 52 ns + (0,16 ns/pF) C
5 180 360 ns 153 ns + (0,55 ns/pF) C
PLH
15 50 100 ns 42 ns + (0,16 ns/pF) C
n
5 140 280 ns 113 ns + (0,55 ns/pF) C
PHL
15 40 80 ns 32 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
+∑(foCL) × V
+∑(foCL) × V
+∑(foCL) × V
65 130 ns 54 ns + (0,23 ns/pF) C
65 130 ns 54 ns + (0,23 ns/pF) C
90 180 ns 79 ns + (0,23 ns/pF) C
90 180 ns 79 ns + (0,23 ns/pF) C
80 160 ns 69 ns + (0,23 ns/pF) C
70 140 ns 59 ns + (0,23 ns/pF) C
55 110 ns 44 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
DD
DD
DD
2
where
2
fi= input freq. (MHz)
2
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑ (f
oCL
V
= supply voltage (V)
DD
) = sum of outputs
TYPICAL EXTRAPOLATION
FORMULA
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 6
Page 7
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
AC CHARACTERISTICS
V
=0V; T
SS
Minimum clock 5 80 40 ns
pulse width; CP
LOW 15 30 15 ns
Minimum clock 5 80 40 ns
pulse width;
HIGH 15 30 15 ns
Minimum PL 5 100 50 ns
pulse width; HIGH 10 t
Minimum MR 5 130 65 ns
pulse width; HIGH 10 t
Hold time 5 30 5 ns
P
→ PL 10 t
n
Set-up time 5 30 0 ns
P
→ PL 10 t
n
Maximum clock 5 6 12 MHz
PL = LOW 15 16 32 MHz
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
CP
DD
V
0
1
10 t
10 t
SYMBOL MIN. TYP. MAX.
WCPL
WCPH
WPLH
15 32 16 ns
WMRH
15 40 20 ns
hold
15 15 5 ns
su
15 15 0 ns
max
40 20 ns
40 20 ns
40 20 ns
50 25 ns
20 5 ns
20 0 ns
12 25 MHz
HEF4522B
MSI
see also waveforms
Figs 5 and 6
see note 1pulse frequency 10 f
Note
1. In the divide-by-n mode (PL connected to TC), one has to observe the maximum HIGH to LOW propagation delay
for CP to TC, before applying the next clock pulse.
January 1995 7
Page 8
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
HEF4522B
MSI
Fig.5 Waveforms showing minimum PL pulse width, propagation delays for PL, Pnto Onand hold time for PL to Pn.
Fig.6 Waveforms showing minimum CP0and CP1pulse widths, propagation delays for CP0, CP1to Onand TC.
January 1995 8
Page 9
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
APPLICATION INFORMATION
Some examples of applications for the HEF4522B are:
• Divide-by-n counter
• Programmable frequency divider
HEF4522B
MSI
Counting cycle:
Fig.7 Typical application of two HEF4522B circuits in a 2-stage programmable down counter (one cycle). S are
thumbwheel switches; when open: LOW state.
January 1995 9
Page 10
Philips Semiconductors Product specification
Programmable 4-bit BCD down counter
HEF4522B
MSI
Counting cycle:
Fig.8 Typical application of two HEF4522B circuits in a 2-stage programmable frequency divider. S are
thumbwheel switches; when open: LOW state.
January 1995 10
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