Datasheet HEF4094BP, HEF4094BT, HEF4094BTS, HEF4094BTT Specification

Page 1

HEF4094B

8-stage shift-and-store register

Rev. 11 — 29 August 2013 Product data sheet

1. General description

The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to par allel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH.

Two serial ou tputs (QS1 and QS2) are available for cascading a number of HEF4094B devices. Serial data is available at QS1 on positive -going clock e dges to allow high -speed operation in cascaded systems with a fast clock rise time. The same seri al data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4094B devices when the clock has a slow rise time.

It operates over a recommended V (usually ground). Unused inputs must be connected to V

power supply range of 3 V to 15 V referenced to VSS

, VSS, or another input.

2. Features and benefits

 Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specifie d from 40 C to +85 C and 40 C to +125 C  Complies with JEDEC standard JESD 13-B

3. Ordering information

Table 1. Ordering information

All types operate from 40C to +125C.

Type number Package

HEF4094BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4094BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4094BTS SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 HEF4094BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

Name Description Version

Page 2

NXP Semiconductors

001aaf119

8-STAGE SHIFT

8-BIT STORAGE

3-STATE OUTPUTS

QS2

QS1

QP0

4 5 6 7 14 13 12 11

QP1 QP2 QP3 QP4 QP5 QP6 QP7

STR

2OED

CP STR

QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7

QS1 QS2910

4 5

6 7 14 13 12 11

001aaf111

001aag799

FF 0

DLEQ

LATCH 0

DCPQ

FF 7

DLEQ

LATCH 7

STAGES 1 TO 6STAGE 0 STAGE 7

QP2

QP0

D QS2

QS1

LATCH

QP1

QP4

QP3

QP6

QP5

QP7

STR

4. Functional diagram

HEF4094B

8-stage shift-and-store register

Fig 1. Functional diagram Fig 2. Logic symbol

Product data sheet Rev. 11 — 29 August 2013 2 of 20

Fig 3. Logic diagram

Page 3

NXP Semiconductors

HEF4094B

STR V

DOE

CP QP4

QP0 QP5

QP1 QP6

QP2 QP7

QP3 QS2

QS1

001aae662

+()%

675 9

' 2(

3 43

43 43

43 43

43 43

43 46

46

DDD

































5. Pinning information

5.1 Pinning

HEF4094B

8-stage shift-and-store register

Fig 4. Pin configuration SOT38-4 and SOT109-1 Fig 5. Pin configuration SOT338-1 and SOT403-1

5.2 Pin description

Table 2. Pin de scription

Symbol Pin Description

STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output V

QS1 9 serial output QS2 10 serial output OE 15 output enable input V

8 ground supply voltage

16 supply voltage

Product data sheet Rev. 11 — 29 August 2013 3 of 20

Page 4

NXP Semiconductors

001aaf117

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

INTERNAL Q6S (FF 6)

OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2

Z-state

HEF4094B

8-stage shift-and-store register

6. Functional description

Table 3. Function table

Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2

 LXXZZQ6SNC  LXXZZNCQ7S  HLXNCNCQ6SNC  HHLLQPn 1Q6S NC  HHHHQPn 1Q6S NC  H H H NCNCNCQ7S

[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

[1]

Fig 6. Timing diagram

Product data sheet Rev. 11 — 29 August 2013 4 of 20

Page 5

NXP Semiconductors

7. Limiting values

HEF4094B

8-stage shift-and-store register

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS= 0 V (ground).

Symbol Parameter Conditions Min Max Unit

I/O

stg

amb

tot

supply voltage 0.5 +18 V input clamping current VI< 0.5 V or VI>VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V output clamping current VO< 0.5 V or VO>VDD + 0.5 V - 10 mA input/output current - 10 mA supply current - 50 mA storage temperature 65 +150 C ambient temperature 40 +125 C total power dissipation DIP16

SO16, SSOP16 and TSSOP16

[1]

- 750 mW

[2]

- 500 mW

P power dissipation per output - 100 mW

[1] For DIP16 packages: above T [2] For SO16 package: P

For (T)SSOP16 package: P

derates linearly with 8 mW/K above 70 C.

tot

= 70 C, P

amb

derates linearly with 5.5 mW/K above 60 C.

tot

derates linearly with 12 mW/K.

tot

8. Recommended operating conditions

Table 5. Re commended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

amb

t/V input transition rise and fall rate V

supply voltage 3 - 15 V input voltage 0 - V

ambient temperature in free air 40 - +125 C

= 5 V --3.75s/V

= 10 V --0.5s/V

= 15 V --0.08s/V

Product data sheet Rev. 11 — 29 August 2013 5 of 20

Page 6

NXP Semiconductors

9. Static characteristics

HEF4094B

8-stage shift-and-store register

Table 6. Static characteristics

VSS = 0 V; VI=VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions V

HIGH-level

IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

input voltage

10 V7.0-7.0-7.0-7.0 -V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

LOW-level input voltage

IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V

HIGH-level output voltage

IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.9 5 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V

LOW-level output voltage

IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V

HIGH-level output current

LOW-level output current

OFF-state output current

input leakage

VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

QPn output

15 V - 0.4 - 0.4 - 12 - 12 A

is HIGH;

=15V

15 V - 0.1 - 0.1 - 1.0 - 1.0 A

current

supply current al l valid input

combinations; IO=0A

5 V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A

input capacitance

= 40 C T

amb

= +25 C T

amb

= +85 C T

amb

= +125 C Unit

amb

Min Max Min Max Min Max Min Max

---7.5--- -pF

Product data sheet Rev. 11 — 29 August 2013 6 of 20

Page 7

NXP Semiconductors

10. Dynamic characteristics

HEF4094B

8-stage shift-and-store register

Table 7. Dynamic characteristics

VSS = 0 V; T

= 25 C; for test circuit see Figure 11; unless otherwise specified.

amb

Symbol Parameter Conditions V

PHL

HIGH to LOW propagation delay

CP to QS1; see Figure 7

CP to QS2; see Figure 7

CP to QPn; see Figure 7

STR to QPn; see Figure 8

PLH

LOW to HIGH propagation delay,

CP to QS1; see Figure 7

CP to QS2; see Figure 7

CP to QPn; see Figure 7

STR to QPn; see Figure 8

PZH

PZL

PHZ

transition time 5 V

OFF-state to HIGH propagation delay

OFF-state to LOW propagation delay

HIGH to OFF-state propagation delay

OE to QPn; see Figure 9

5 V 10 V 54 ns + (0.23 ns/pF)C 15 V 42 ns + (0.16 ns/pF)C

5 V 78 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 138 ns + (0.55 ns/pF)C 10 V 64 ns + (0.23 ns/pF)C 15 V 47 ns + (0.16 ns/pF)C

5 V 83 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 27 ns + (0.16 ns/pF)C

5 V 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 78 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 123 ns + (0.55 ns/pF)C 10 V 59 ns + (0.23 ns/pF)C 15 V 47 ns + (0.16 ns/pF)C

5 V 73 ns + (0.55 ns/pF)C 10 V 34 ns + (0.23 ns/pF)C 15 V 27 ns + (0.16 ns/pF)C

10 V 9 ns + (0.42 ns/pF)C 15 V 6 ns + (0.28 ns/pF)C

Extrapolation formula Min Typ Max Unit

[1]

108 ns + (0.55 ns/pF)C

[1]

78 ns + (0.55 ns/pF)C

[1]

10 ns + (1.00 ns/pF)C

- 135 270 ns

- 65 130 ns

- 50 100 ns

- 105 210 ns

- 50 100 ns

-4080ns

- 165 330 ns

- 75 150 ns

- 55 110 ns

- 110 220 ns

- 50 100 ns

-3570ns

- 105 210 ns

- 50 100 ns

-4080ns

- 105 210 ns

- 50 100 ns

-4080ns

- 150 300 ns

- 70 140 ns

- 55 110 ns

- 100 200 ns

-4590ns

-3570ns

- 60 120 ns

-3060ns

-2040ns

5 V - 40 80 ns 10 V - 25 50 ns 15 V - 20 40 ns

5 V - 75 150 ns 10 V - 40 80 ns 15 V - 30 60 ns

Product data sheet Rev. 11 — 29 August 2013 7 of 20

Page 8

NXP Semiconductors

HEF4094B

8-stage shift-and-store register

Table 7. Dynamic characteristics

VSS = 0 V; T

= 25 C; for test circuit see Figure 11; unless otherwise specified.

amb

…continued

Symbol Parameter Conditions V

PLZ

LOW to OFF-state propagation delay

OE to QPn; see Figure 9

set-up time D to CP;

see Figure 10

hold time D to CP;

see Figure 10

pulse width minimum LOW

clock pulse; see Figure 7

minimum HIGH strobe pulse; see Figure 8

max

maximum frequency see Figure 7 5 V 5 10 - MHz

Extrapolation formula Min Typ Max Unit

5 V - 80 160 ns 10 V - 40 80 ns 15 V - 30 60 ns

5 V 6030- ns 10 V 20 10 - ns 15 V 15 5 - ns

5 V +5 15 - ns 10 V 20 5 - ns 15 V 20 5 - ns

5 V 6030- ns 10 V 30 15 - ns 15 V 24 12 - ns

5 V 4020- ns 10 V 30 15 - ns 15 V 24 12 - ns

10 V 11 22 - MHz 15 V 1428- MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 8. Dy namic power dissipation

VSS = 0 V; tr = tf  20 ns; T

Symbol Parameter V

dynamic power dissipation

= 25 C.

amb

Typical formula for PD (W) where:

5 V PD = 2100  fi + (fo  CL)  V

10 V P

= 9700  fi + (fo  CL)  V

15 V PD = 26000  fi + (fo  CL)  V

DD DD

2 2

fi = input frequency in MHz, f

= output frequency in MHz,

= output load capacitance in pF,

= supply voltage in V,

(f

 CL) = sum of the outputs.

Product data sheet Rev. 11 — 29 August 2013 8 of 20

Page 9

NXP Semiconductors

1/f

max

PHL

PLH

GND

QPn, QS1 output

CP input

001aaf113

PHL

PLH

QS2 output

PHL

PLH

GND

QPn output

STR input

001aaj058

8-stage shift-and-store register

11. Waveforms

Measurement points are given in Table 9. Logic levels: V

Fig 7. Clock to outputs propagation delays, and clock pulse width and maximum frequency

and VOH are typical output voltage levels that occur with the output load.

HEF4094B

Table 9. Measur ement points

Supply voltage Input Output V

5 V to 15 V 0.5V

Measurement points are given in Table 9. Logic levels: V

and VOH are typical output voltage levels that occur with the output load.

0.5V

0.1V

0.9V

Fig 8. Strobe to output propagation delays, and strobe pulse width, set up and hold times

Product data sheet Rev. 11 — 29 August 2013 9 of 20

Page 10

NXP Semiconductors

001aai545

PLZ

PHZ

outputs

disabled

outputs enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output HIGH-to-OFF OFF-to-HIGH

OE input

GND

PZL

PZH

GND

001aaf115

GND

QPn, QS1, QS2 output

CP input

D input

Measurement points are given in Table 9. Logic levels: V

Fig 9. 3-state output enable and disable times for OE input

and VOH are typical output voltage levels that occur with the output load.

HEF4094B

8-stage shift-and-store register

Fig 10. Data input data set up and hold times

Product data sheet Rev. 11 — 29 August 2013 10 of 20

Measurement points are given in Table 9. Logic levels: V

and VOH are typical output voltage levels that occur with the output load.

Page 11

NXP Semiconductors

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

001aaj915

EXT

DUT

a. Input waveform

HEF4094B

8-stage shift-and-store register

b. Test circuit

Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test.

= load capacitance including jig and probe capacitance.

= load resistance.

= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 11. Test circuit

Table 10. Test data

Supply voltage Input V V

5 V to 15 V VSS or V

tr, t

 20 ns open V

PHL

EXT

, t

PLH

PHZ

, t

PZH

PLZ

, t

PZL

Load C

50 pF 1 k

Product data sheet Rev. 11 — 29 August 2013 11 of 20

Page 12

NXP Semiconductors

001aae666

DIGITALLY CONTROLLED

EQUIPMENT

(REQUIRES CONTINUOUS

DIGITAL CONTROL)

CONTROL

AND

SYNC

CIRCUITRY

data clock

from remote

control panel

HEF4094B

QP0

STR

D QS2

QP7

DIGITALLY CONTROLLED

EQUIPMENT

HEF4094B

QP0

STR

D QS2

QP7

DIGITALLY CONTROLLED

EQUIPMENT

HEF4094B

QP0

STR

QP7

12. Application information

Some examples of applications for the HEF4094B are:

• Serial-to-parallel data conversion

• Remote control holding register

HEF4094B

8-stage shift-and-store register

Fig 12. Remote control holding register

Product data sheet Rev. 11 — 29 August 2013 12 of 20

Page 13

NXP Semiconductors

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT38-4

95-01-14 03-02-13

(e )

seating plane

w M

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT

max.

(1) (1)

(1)

cD E e M

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.1 0.3

0.32

0.31

0.39

0.33

0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

13. Package outline

HEF4094B

8-stage shift-and-store register

Fig 13. Package outline SOT38-4 (DIP16)

Product data sheet Rev. 11 — 29 August 2013 13 of 20

Page 14

NXP Semiconductors

w M

detail X

v M

(A )

pin 1 index

UNIT

max.

1A2

A3b

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8 0

o o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1

99-12-27 03-02-19

076E07 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

HEF4094B

8-stage shift-and-store register

Fig 14. Package outline SOT109-1 (SO16)

Product data sheet Rev. 11 — 29 August 2013 14 of 20

Page 15

NXP Semiconductors

UNIT A1A2A3b

(1)E(1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.21

0.05

1.80

1.65

0.25

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

0.65 1.25

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

8 0

o o

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1

99-12-27 03-02-19

(1)

w M

v M

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

max.

HEF4094B

8-stage shift-and-store register

Fig 15. Package outline SOT338-1 (SSOP16)

Product data sheet Rev. 11 — 29 August 2013 15 of 20

Page 16

NXP Semiconductors

UNIT A1A2A3b

(1)E(2) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

0.65

6.6

6.2

0.4

0.3

0.40

0.06

8 0

o o

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153

99-12-27 03-02-18

w M

0.25

detail X

(A )

v M

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

max.

1.1

pin 1 index

HEF4094B

8-stage shift-and-store register

Fig 16. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 11 — 29 August 2013 16 of 20

Page 17

NXP Semiconductors

HEF4094B

8-stage shift-and-store register

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4094B v.11 20130829 Product data sheet - HEF4094B v.10 Modifications: HEF4094B v.10 20130625 Product data sheet - HEF4094B v.9 Modifications: HEF4094B v.9 20111116 Product da ta sheet - HEF4094B v.8 Modifications: HEF4094B v.8 20100402 Product data sheet - HEF4094B v.7 HEF4094B v.7 20091216 Product data sheet - HEF4094B v.6 HEF4094B v.6 20091103 Product data sheet - HEF4094B v.5 HEF4094B v.5 20090728 Product data sheet - HEF4094B v.4 HEF4094B v.4 20081030 Product data sheet - HEF4094B_CNV v.3 HEF4094B_CNV v.3 19950101 Product specification - HEF4094B_CNV v.2 HEF4094B_CNV v.2 19950101 Product specification - -

• Table 4: Table note corrected (errata).

• added type number HEF4094BTT.

• Table 6: I

minimum values changed to maximum

Product data sheet Rev. 11 — 29 August 2013 17 of 20

Page 18

NXP Semiconductors

HEF4094B

8-stage shift-and-store register

15. Legal information

15.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cust omer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

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17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Application information. . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

15 Legal information . . . . . . . . . . . . . . . . . . . . . . . 18

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16 Contact information. . . . . . . . . . . . . . . . . . . . . 19

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Date of release: 29 August 2013

Document identifier: HEF4094B