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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4094B
MSI
8-stage shift-and-store bus register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
8-stage shift-and-store bus register
DESCRIPTION
The HEF4094B is an 8-stage serial shift register having a
storage latch associated with each stage for strobing data
from the serial input to parallel buffered 3-state outputs
O0to O7. The parallel outputs may be connected directly
to common bus lines. Data is shifted on positive-going
clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR)
input is HIGH. Data in the storage register appears at the
outputs whenever the output enable (EO) signal is HIGH.
HEF4094B
MSI
Two serial outputs (O
a number of HEF4094B devices. Data is available at Oson
positive-going clock edges to allow high-speed operation
in cascaded systems in which the clock rise time is fast.
The same serial information is available at O’son the next
negative-going clock edge and provides cascading
HEF4094B devices when the clock rise time is slow.
and O’s) are available for cascading
s
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4094BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4094BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4094BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D data input EO output enable input
CP clock input O
STR strobe input O
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
, O’
s
to O7parallel outputs
0
serial outputs
s
January 1995 2
Page 3
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January 1995 3
Philips Semiconductors Product specification
8-stage shift-and-store bus register
Fig.3 Logic diagram.
Fig.4 One D-latch.
HEF4094B
MSI
Page 4
Philips Semiconductors Product specification
8-stage shift-and-store bus register
FUNCTION TABLE
INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS
CP EO STR D O
LXX Z Z O’
LXX Z Z nc O
HLX nc nc O’
HH L L O
HHH H O
HHH nc nc nc O
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. = positive-going transition
5. = negative-going transition
6. Z = high impedance off state
7. nc = no change
8. O’
= the information in the seventh shift register stage
6
0
HEF4094B
MSI
O
n
n-1
n-1
O
O’
O’
s
6
6
6
6
O’
nc
7
nc
nc
nc
7
s
At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the
Osoutput.
AC CHARACTERISTICS
= 0 V; T
V
SS
Dynamic power 5 2100 f
dissipation per 10 9700 f
package (P) 15 26 000 f
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
V
) = sum of outputs
oCL
= supply voltage (V)
DD
January 1995 4
Page 5
Philips Semiconductors Product specification
8-stage shift-and-store bus register
HEF4094B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
CP → O’
HIGH to LOW 10 t
LOW to HIGH 10 t
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
STR → O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
s
5 135 270 ns 108 ns + (0,55 ns/pF) C
SYMBOL TYP. MAX.
PHL
15 50 100 ns 42 ns + (0,16 ns/pF) C
5 105 210 ns 78 ns + (0,55 ns/pF) C
PLH
15 40 80 ns 32 ns + (0,16 ns/pF) C
s
5 105 210 ns 78 ns + (0,55 ns/pF) C
PHL
15 40 80 ns 32 ns + (0,16 ns/pF) C
5 105 210 ns 78 ns + (0,55 ns/pF) C
PLH
15 40 80 ns 32 ns + (0,16 ns/pF) C
n
5 165 330 ns 138 ns + (0,55 ns/pF) C
PHL
15 55 110 ns 47 ns + (0,16 ns/pF) C
5 150 300 ns 123 ns + (0,55 ns/pF) C
PLH
15 55 110 ns 47 ns + (0,16 ns/pF) C
n
5 110 220 ns 83 ns + (0,55 ns/pF) C
PHL
15 35 70 ns 27 ns + (0,16 ns/pF) C
5 100 200 ns 73 ns + (0,55 ns/pF) C
PLH
15 35 70 ns 27 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLATION
FORMULA
65 130 ns 54 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
75 150 ns 64 ns + (0,23 ns/pF) C
70 140 ns 59 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
45 90 ns 34 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 5
Page 6
Philips Semiconductors Product specification
8-stage shift-and-store bus register
AC CHARACTERISTICS
V
= 0 V; T
SS
3-state propagation delays
Output enable times 5 40 80 ns
EO → O
HIGH 15 20 40 ns
LOW 10 t
Output disable times 5 75 150 ns
EO → O
HIGH 15 30 60 ns
LOW 10 t
Minimum clock 5 60 30 ns
pulse width 10 t
LOW 15 24 12 ns
Minimum strobe 5 40 20 ns
pulse width 10 t
HIGH 15 24 12 ns
Set-up times 5 60 30 ns
D → CP 10 t
Hold times 5 5 −15 ns
D → CP 10 t
Maximum clock 5 5 10 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
10 t
SYMBOL MIN. TYP. MAX.
PZH
54080ns
PZL
15 20 40 ns
n
10 t
PHZ
5 80 160 ns
PLZ
15 30 60 ns
WCPL
WSTRH
su
15 15 5 ns
hold
15 20 5 ns
max
15 14 28 MHz
25 50 ns
25 50 ns
40 80 ns
40 80 ns
30 15 ns
30 15 ns
20 10 ns
20 5 ns
11 22 MHz
HEF4094B
MSI
January 1995 6
Page 7
Philips Semiconductors Product specification
8-stage shift-and-store bus register
Fig.5 Timing diagram.
HEF4094B
MSI
APPLICATION INFORMATION
Some examples of applications for the HEF4094B are:
• Serial-to-parallel data conversion
• Remote control holding register
Fig.6 Remote control holding register.
January 1995 7
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