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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4042B
MSI
Quadruple D-latch
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Quadruple D-latch
DESCRIPTION
The HEF4042B is a 4-bit latch with four data inputs (D0to
D3), four buffered latch outputs (O0to O3), four buffered
complementary latch outputs (O0to O3) and two common
enable inputs (E0and E1). Information on D0to D3is
transferred to O0to O3while both E0and E1are in the
same state, either HIGH or LOW. O0to O3follow D0to
D3as long as both E0and E1remain in the same state.
When E0and E1are different, D0to D3do not affect O0to
O3 and the information in the latch is stored.
O0to O3are always the complement of O0to O3. The
exclusive-OR input structure allows the choice of either
polarity for E0and E1. With one enable input HIGH, the
other enable input is active HIGH; with one enable input
LOW, the other enable input is active LOW.
HEF4042B
MSI
Fig.2 Pinning diagram.
HEF4042BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4042BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4042BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.1 Functional diagram.
PINNING
D
to D
0
E
and E
0
to O
O
0
O0to O
3
3
3
data inputs
enable inputs
1
parallel latch outputs
complementary parallel latch outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4042B are:
• Buffer storage
• Holding register
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
January 1995 2
Page 3
Philips Semiconductors Product specification
Quadruple D-latch
HEF4042B
FUNCTION TABLE
E
0
LL D
L H latched
H L latched
HH D
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage).
E
1
OUTPUT O
n
n
MSI
n
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
January 1995 3
Page 4
Philips Semiconductors Product specification
Quadruple D-latch
HEF4042B
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
D → O,
HIGH to LOW 10 t
LOW to HIGH 10 t
E → O, O 5 130 260 ns 102 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition
times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Set-up time 5 30 10 ns
D → E10t
Hold time 5 15 −5ns
D→E10t
Minimum enable 5 90 45 ns
pulse width 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
O 5 95 190 ns 67 ns + (0,55 ns/pF) C
PHL
40 80 ns 28 ns + (0,23 ns/pF) C
15 30 55 ns 22 ns + (0,16 ns/pF) C
5 85 175 ns 57 ns + (0,55 ns/pF) C
PLH
40 75 ns 28 ns + (0,23 ns/pF) C
15 30 60 ns 22 ns + (0,16 ns/pF) C
PHL
50 105 ns 38 ns + (0,23 ns/pF) C
15 35 75 ns 27 ns + (0,16 ns/pF) C
5 120 245 ns 92 ns + (0,55 ns/pF) C
PLH
50 105 ns 38 ns + (0,23 ns/pF) C
15 35 75 ns 27 ns + (0,16 ns/pF) C
THL
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
su
20 5 ns
15 20 5 ns
hold
15 0 ns
see also waveforms
Figs 5 and 6
15 15 0 ns
WE
40 20 ns
15 30 15 ns
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
Dynamic power 5 3800 f
dissipation per 10 15 700 f
package (P) 15 41 100 f
TYPICAL FORMULA FOR P (W)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
January 1995 4
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
) = sum of outputs
∑ (f
oCL
V
= supply voltage (V)
DD
Page 5
Philips Semiconductors Product specification
Quadruple D-latch
HEF4042B
MSI
Either E0or E1is held HIGH or LOW while the other enable input is pulsed as
the function table shows.
Fig.5 Waveforms showing propagation delays for D to O, with latch enabled.
January 1995 5
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Philips Semiconductors Product specification
Quadruple D-latch
HEF4042B
Fig.6 Waveforms showing minimum enable pulse width, set-up time and hold time for E and D. Set-up and
hold-times are shown as positive values but may be specified as negative values.
MSI
January 1995 6
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