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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4022B
MSI
4-stage divide-by-8 Johnson
counter
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
DESCRIPTION
The HEF4022B is a 4-stage divide-by-8 Johnson counter
with eight spike-free decoded active HIGH outputs (O0 to
O7), an active LOW output from the most significant
flip-flop (O
(CP0, CP1) and an overriding asynchronous master reset
input (MR).
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table). Either CP
), active HIGH and active LOW clock inputs
4-7
or CP1 may be used as clock input to the
0
HEF4022B
MSI
counter and the other clock input may be used as a clock
O
enable input. When cascading counters, the
which is LOW while the counter is in states, 4, 5, 6 and 7,
can be used to drive the CP0input of the next counter.
A HIGH on MR resets the counter to zero
(O0= O
= HIGH; O1 to O7 = LOW) independent of the
4-7
clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an
internal circuit, following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
output,
4-7
Fig.2 Pinning diagram.
PINNING
CP
CP
O
1
clock input (LOW to HIGH; edge-triggered)
clock input (HIGH to LOW; edge-triggered)
MR master reset input
O
O
to O
0
4-7
7
decoded outputs
carry output (active LOW)
Fig.1 Functional diagram.
HEF4022BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4022BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4022BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
January 1995 2
Page 3
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January 1995 3
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
Fig.3 Logic diagram.
HEF4022B
MSI
Page 4
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
HEF4022B
FUNCTION TABLE
MR CP
HXXO
CP
0
1
OPERATION
=O
0
4-7
= H; O1 to O7=L
L H Counter advances
L L Counter advances
L L X No change
L X H No change
L H No change
L L No change
AC CHARACTERISTICS
V
= 0 V; T
SS
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
Propagation delays
CP0, CP1→ O
n
HIGH to LOW 10 t
5 195 390 ns 168 ns + (0,55 ns/pF) C
PHL
15 50 100 ns 42 ns + (0,16 ns/pF) C
5 245 485 ns 218 ns + (0,55 ns/pF) C
LOW to HIGH 10 t
PLH
15 60 125 ns 52 ns + (0,16 ns/pF) C
CP0, CP1→ O
4-7
HIGH to LOW 10 t
5 245 485 ns 218 ns + (0,55 ns/pF) C
PHL
15 60 120 ns 52 ns + (0,16 ns/pF) C
5 190 380 ns 163 ns + (0,55 ns/pF) C
LOW to HIGH 10 t
PLH
15 50 105 ns 42 ns + (0,16 ns/pF) C
MR → O1to O
7
HIGH to LOW 10 t
5 130 260 ns 103 ns + (0,55 ns/pF) C
PHL
15 40 75 ns 32 ns + (0,16 ns/pF) C
MR → O
0
LOW to HIGH 10 t
5 130 260 ns 103 ns + (0,55 ns/pF) C
PLH
15 40 75 ns 32 ns + (0,16 ns/pF) C
MR → O
4-7
LOW to HIGH 10 t
5 110 220 ns 83 ns + (0,55 ns/pF) C
PLH
15 35 70 ns 27 ns + (0,16 ns/pF) C
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
LOW to HIGH 10 t
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
TYPICAL EXTRAPOLATION
FORMULA
75 145 ns 64 ns + (0,23 ns/pF) C
95 195 ns 84 ns + (0,23 ns/pF) C
90 185 ns 79 ns + (0,23 ns/pF) C
75 145 ns 64 ns + (0,23 ns/pF) C
55 105 ns 44 ns + (0,23 ns/pF) C
55 105 ns 44 ns + (0,23 ns/pF) C
45 90 ns 34 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 4
Page 5
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
AC CHARACTERISTICS
V
= 0 V; T
SS
Hold times 5 140 70 ns
CP0→ CP
CP1→ CP
Minimum clock 5 75 35 ns
pulse width 10 t
Minimum MR 5 70 35 ns
pulse width; HIGH 10 t
Recovery time 5 30 10 ns
for MR 10 t
Maximum clock 5 3 6 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
1
10 t
SYMBOL MIN. TYP. MAX.
hold
15 30 15 ns
5 170 85 ns
0
10 t
hold
15 40 20 ns
WCP
15 20 10 ns
WMRH
15 20 10 ns
RMR
15 10 5 ns
max
15 12 24 MHz
50 25 ns
60 30 ns
30 15 ns
30 15 ns
15 5 ns
8 16 MHz
HEF4022B
MSI
see also waveforms
Figs 4 and 5
V
DD
V
Dynamic power 5 475 f
dissipation per 10 2400 f
package (P) 15 6700 f
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
January 1995 5
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= total load capacitance (pF)
C
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
Page 6
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
HEF4022B
MSI
Fig.4 Waveforms showing hold times for CP0to CP1 and CP1 to CP0. Hold times are shown as positive values,
but may be specified as negative values.
Conditions: CP1= LOW while CP0 is triggered on a LOW to HIGH transition.
and t
t
WCP
a HIGH to LOW transition.
also apply when CP0= HIGH and CP1 is triggered on
RMR
Fig.5 Waveforms showing recovery time for MR; minimum CP0and MR pulse widths.
January 1995 6
Page 7
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
HEF4022B
MSI
Fig.6 Timing diagram.
January 1995 7
Page 8
Philips Semiconductors Product specification
4-stage divide-by-8 Johnson counter
HEF4022B
MSI
APPLICATION INFORMATION
Some of the features of the HEF4022B are:
• High speed
• Spike-free decoded outputs
• Carry output for cascading
Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Fig.7 Counter expansion.
January 1995 8
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