Datasheet HEF4021BP, HEF4021BT, HEF4021BTT Specification

Page 1

HEF4021B

8-bit static shift register

Rev. 9 — 30 August 2013 Product data sheet

1. General description

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7).

Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.

It operates over a recommended V (usually ground). Unused inputs must be connected to V

power supply range of 3 V to 15 V referenced to VSS

, VSS, or another input.

2. Features and benefits

 Tolerant of slower rise and fall times  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specifie d from 40 C to +125 C  Complies with JEDEC standard JESD 13-B

3. Ordering information

Table 1. Ordering information

All types operate from

Type number Package Version

HEF4021BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4021BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4021BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

40

C to +125C.

Name Description

Page 2

NXP Semiconductors

001aae608

D CP

SHIFT REGISTER

8-BITS

1110DS

9PL

SD/CD

7 D0

6D15D24D313D414D515D61

2Q512Q63

D CP

FF 1

D CP

FF 6

D CP

FF 7

D CP

FF 8

Q5 Q6

001aae610

4. Functional diagram

Fig 1. Functional diagram

HEF4021B

8-bit static shif t register

Fig 2. Logic diagram

Product data sheet Rev. 9 — 30 August 2013 2 of 16

Page 3

NXP Semiconductors

HEF4021B

D7 V

Q5 D6

Q7 D5

D3 D4

D2 Q6

D1 DS

D0 CP

001aae609

5. Pinning information

5.1 Pinning

HEF4021B

8-bit static shif t register

Fig 3. Pin configuration

Table 2. Pin description

Symbol Pin Description

Q5 to Q7 2, 12, 3 buffered parallel output from the last three stages D0 to D7 7, 6, 5, 4, 13, 14,15, 1 parallel data input V

PL 9 parallel load input CP 10 clock input (LOW-to-HIGH edge-triggered) DS 11 serial data input V

6. Functional description

Table 3. Function table

Number of clock transitions

Serial operation

1  data 1 L X X X 2  data 2 L X X X 3  data 3 L X X X 6  XLdata1XX 7  X L data 2 data 1 X

5.2 Pin description

8 ground supply voltage

16 supply voltage

[1]

Inputs Outputs CP DS PL Q5 Q6 Q7

Product data sheet Rev. 9 — 30 August 2013 3 of 16

Page 4

NXP Semiconductors

HEF4021B

8-bit static shif t register

[1]

Table 3. Function table

Number of clock transitions

Inputs Outputs CP DS PL Q5 Q6 Q7

…continued

8  X L data 3 data 2 data 1

 X L no change no change no change

Parallel operation

X X H D5 D6 D7

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = LOW to HIGH clock transition; = HIGH to LOW clock transition; data n = data (HIGH or LOW) on the DS input at the n

 CP transition.

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

I/O

stg

amb

tot

supply voltage 0.5 +18 V input clamping current VI< 0.5 V or VI>VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V output clamping current VO< 0.5 V or VO>VDD + 0.5 V - 10 mA input/output current - 10 mA supply current - 50 mA storage temperature 65 +150 C ambient temperature 40 +125 C total power dissipation T

40 C to +125 C

amb

DIP16 package SO16 and TSSOP16 package

[1]

-750mW

[2]

-500mW

P power dissipation per output - 100 mW

[1] For DIP16 package: P [2] For SO16 package: P

For TSSOP16 package: P

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

derates linearly with 5.5 mW/K above 60 C.

tot

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

amb

t/V input transition rise and fall rate V

Product data sheet Rev. 9 — 30 August 2013 4 of 16

supply voltage 3 - 15 V input voltage 0 - V

ambient temperature in free air 40 - +125 C

= 5 V --3.75s/V

= 10 V --0.5s/V

= 15 V --0.08s/V

Page 5

NXP Semiconductors

9. Static characteristics

HEF4021B

8-bit static shif t register

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions V

HIGH-level

IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

input voltage

10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V

LOW-level input voltage

IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V

HIGH-level output voltage

LOW-level output voltage

HIGH-level output current

LOW-level output current

input leakage

IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V

IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V

VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

VDD = 15 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

current

supply current

IO = 0 A 5 V - 5 - 5 - 150 - 150 A

10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A

input

- ---7.5----pF

capacitance

= 40 C T

amb

= 25 C T

amb

= 85 C T

amb

= 125 C Unit

amb

Min Max Min Max Min Max Min Max

10. Dynamic characteristics

Table 7. Dynamic characteristics

= 0 V; T

= 25 C; for test circuit see Figure 7; unless otherwise specified.

amb

Symbol Parameter Conditions V

PHL

HIGH to LOW propagation delay

Product data sheet Rev. 9 — 30 August 2013 5 of 16

Extrapolation formula Min Typ Max Unit

[1]

98 ns + (0.55 ns/pF)C

L L L L L L

- 125 250 ns

-55110ns

-4080ns

- 120 240 ns

-55110ns

-4080ns

CP to Qn see Figure 4

PL to Qn see Figure 4

5 V 10 V 44 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 93 ns + (0.55 ns/pF)C 10 V 44 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

Page 6

NXP Semiconductors

HEF4021B

8-bit static shif t register

Table 7. Dynamic characteristics

VSS = 0 V; T

= 25 C; for test circuit see Figure 7; unless otherwise specified.

amb

…continued

Symbol Parameter Conditions V

PLH

LOW to HIGH propagation delay

CP to Qn see Figure 4

PL to Qn see Figure 4

transition time Qn; see Figure 4 5 V

set-up time DS to CP;

see Figure 5

Dn to PL; see Figure 6

hold time DS to CP;

see Figure 5

Dn to PL; see Figure 6

pulse width CP = LOW;

minimum width; see Figure 5

PL = HIGH; minimum width; see Figure 6

rec

recovery time PL input;

see Figure 6

clk(max)

maximum clock frequency

CP input; see Figure 5

5 V 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

5 V 78 ns + (0.55 ns/pF)C 10 V 39 ns + (0.23 ns/pF)C 15 V 32 ns + (0.16 ns/pF)C

10 V 9 ns + (0.42 ns/pF)C 15 V 6 ns + (0.28 ns/pF)C

Extrapolation formula Min Typ Max Unit

[1]

88 ns + (0.55 ns/pF)C

[1]

10 ns + (1.00 ns/pF)C

L L L L L L L L L

- 115 230 ns

- 50 100 ns

-4080ns

- 105 210 ns

- 50 100 ns

-4080ns

- 60 120 ns

-3060ns

-2040ns

5 V +25 15 - ns 10 V +25 10 - ns 15 V +15 5- ns

5 V 50 25 - ns 10 V 30 10 - ns 15 V 20 5 - ns

5 V 40 20 - ns 10 V 20 10 - ns 15 V 15 8 - ns

5 V +15 10 - ns 10 V 15 0 - ns 15 V 15 0 - ns

5 V 70 35 - ns 10 V 30 15 - ns 15 V 24 12 - ns

5 V 50 10 - ns 10 V 40 5 - ns 15 V 35 5 - ns

5 V 6 13 - MHz 10 V 15 30 - MHz 15 V 20 40 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Product data sheet Rev. 9 — 30 August 2013 6 of 16

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NXP Semiconductors

001aaj060

CP or PL INPUT

Qn OUTPUT V

PHL

PLH

001aae611

1 / f

clk(max)

CP INPUT

DS INPUT

HEF4021B

8-bit static shif t register

Table 8. Dynamic power dissipation P

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; T

Symbol Parameter V

dynamic power dissipation

5 V PD = 900  fi + (fo  CL)  V

10 V P

Typical formula for PD (W) where:

= 4300  fi + (fo  CL)  V

15 V PD = 12000  fi + (fo  CL)  V

11. Waveforms

amb

= 25 C.

fi = input frequency in MHz, f

= output frequency in MHz,

CL = output load capacitance in pF, V

= supply voltage in V,

(f

 CL) = sum of the outputs.

Fig 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times

Fig 5. Waveforms showing minimum cloc k puls e width, set-up time, and hold time for CP and DS.

Product data sheet Rev. 9 — 30 August 2013 7 of 16

Page 8

NXP Semiconductors

001aae612

rec

CP INPUT

PL INPUT

Dn INPUT

10 %

90 %

HEF4021B

8-bit static shif t register

Set-up times and hold times are shown as positive values but may be specified as negative values; Measurement points are given in Table 9

Fig 6. Waveforms showing minimum puls e width and recovery time for PL; set-up and hold times for Dn to PL.

Table 9. Measurement points

Supply voltage Input Output V

5 V to 15 V 0.5V

0.5V

0.1V

0.9V

Product data sheet Rev. 9 — 30 August 2013 8 of 16

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NXP Semiconductors

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

001aag182

DUT

a. Input waveform

HEF4021B

8-bit static shif t register

b. Test circuit

Test data is given in Table10. Definitions for test circuit: DUT = Device Under Test.

= load capacitance including jig and probe capacitance.

= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 7. Test circuit for measuring switching times

Table 10. Test data

Supply voltage Input Load V

5 V to 15 V VSS or V

tr, t

 20 ns 50 pF

Product data sheet Rev. 9 — 30 August 2013 9 of 16

Page 10

NXP Semiconductors

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT38-4

95-01-14 03-02-13

(e )

seating plane

w M

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT

max.

(1) (1)

(1)

cD E e M

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.1 0.3

0.32

0.31

0.39

0.33

0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

12. Package outline

HEF4021B

8-bit static shif t register

Fig 8. Package outline SOT38-4 (DIP16)

Product data sheet Rev. 9 — 30 August 2013 10 of 16

Page 11

NXP Semiconductors

w M

detail X

v M

(A )

pin 1 index

UNIT

max.

A2A3b

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8 0

o o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1

99-12-27 03-02-19

076E07 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

HEF4021B

8-bit static shif t register

Fig 9. Package outline SOT109-1 (SO16)

Product data sheet Rev. 9 — 30 August 2013 11 of 16

Page 12

NXP Semiconductors

UNIT A

A2A3b

(1)E(2) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

0.65

6.6

6.2

0.4

0.3

0.40

0.06

8 0

o o

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153

99-12-27 03-02-18

w M

0.25

detail X

(A )

v M

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

max.

1.1

pin 1 index

HEF4021B

8-bit static shif t register

Fig 10. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 9 — 30 August 2013 12 of 16

Page 13

NXP Semiconductors

HEF4021B

8-bit static shif t register

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4021B v.9 20130830 Product data sheet - HEF4021B v.8 Modifications: HEF4021B v.8 20111118 Produc t data sheet - HEF4021B v.7 Modifications:

HEF4021B v.7 2011101 0 P roduct data sheet - HEF4021B v.6 HEF4021B v.6 20091127 Product data sheet - HEF4021B v.5 HEF4021B v.5 20090707 Product data sheet - HEF4021B v.4 HEF4021B v.4 20081110 Product data sheet - HEF4021B_CNV v.3 HEF4021B_CNV v.3 19950101 Product specification - HEF4021B_CNV v.2 HEF4021B_CNV v.2 19950101 Product specification - -

• added type number HEF4021BTT.

• Legal pag es updated.

• Changes in “General description” and “Features and benefits”.

• Section “Applications” removed.

Product data sheet Rev. 9 — 30 August 2013 13 of 16

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NXP Semiconductors

HEF4021B

8-bit static shif t register

14. Legal information

14.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained i n section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cust omer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 9 — 30 August 2013 14 of 16

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NXP Semiconductors

HEF4021B

8-bit static shif t register

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

15. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Product data sheet Rev. 9 — 30 August 2013 15 of 16

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NXP Semiconductors

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15 Contact information. . . . . . . . . . . . . . . . . . . . . 15

16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HEF4021B

8-bit static shif t register

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Date of release: 30 August 2013 Document identifier: HEF4021B