Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4016B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
Quadruple bilateral switches
DESCRIPTION
The HEF4016B has four independent analogue switches
(transmission gates). Each switch has two input/output
terminals (Y/Z) and an active HIGH enable input (E). When
E is connected to VDDa low impedance bidirectional path
between Y and Z is established (ON condition). When E is
connected to VSSthe switch is disabled and a high
HEF4016B
gates
impedance between Y and Z is established (OFF
condition). Current through a switch will not cause
additional V
terminals of the switch is maintained within the supply
voltage range; VDD≥ (VY, VZ) ≥ VSS. Inputs Y and Z are
electrically equivalent terminals.
current provided the voltage at the
DD
Fig.1 Functional diagram.
PINNING
to E
E
0
Y
to Y
0
to Z
Z
0
enable inputs
3
input/output terminals
3
input/output terminals
3
APPLICATION INFORMATION
Some examples of applications for the HEF4016B are:
• Signal gating
• Modulation
• Demodulation
• Chopper
Fig.2 Pinning diagram.
HEF4016BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4016BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)
HEF4016BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
Fig.3 Schematic diagram
(one switch).
January 1995 2
Page 3
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4016B
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
DC CHARACTERISTICS
=25°C; VSS= 0 V (unless otherwise specified)
T
amb
V
PARAMETER
DD
V
5 8000 −ΩE
ON resistance 10 R
15 115 350 Ω
5 140 425 Ω Enat VIH; Vis=VSS; see Fig.4
ON resistance 10 R
15 50 145 Ω
5 170 515 Ω Enat VIH; Vis=VDD; see Fig.4
ON resistance 10 R
15 75 220 Ω
‘∆’ ON resistance 5 200 −ΩE
between any two 10 ∆R
channels 15 10 −Ω
SYMBOL TYP. MAX. UNIT CONDITIONS
at VIH; Vis= 0 to VDD; see Fig.4
n
ON
ON
ON
ON
230 690 Ω
65 195 Ω
95 285 Ω
15 −Ω
at VIH; Vis= 0 to VDD; see Fig.4
n
gates
T
(°C)
amb
UNIT−40 + 25 + 85 CONDITION
PARAMETER
V
DD
V SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
Quiescent 5 − 1,0 − 1,0 − 7,5 µAV
device 10 I
DD
− 2,0 − 2,0 − 15,0 µA
current 15 − 4,0 − 4,0 − 30,0 µA
Input leakage
current at E
n
15 ± I
IN
−−−300 − 1000
nA E
= 0; all valid
SS
input combinations;
VI=VSSor V
at VSSor V
n
OFF-state leakage 5 −−−−−−nA Enat VIL;
current, any 10 I
OZ
−−−−−−nA
channel OFF 15 −−−200 −−nA
input 5 − 1,5 − 1,5 − 1,5 V switch OFF; see
E
n
voltage LOW 10 V
IL
− 3,0 − 3,0 − 3,0 V
Vis=VSSor VDD;
Vos=VDDor V
Fig.9 for I
15 − 4,0 − 4,0 − 4,0 V
E
input 5 3,5 − 3,5 − 3,5 − V low-impedance
n
voltage HIGH 10 V
15 11,0 − 11,0 − 11,0 − V
IH
7,0 − 7,0 − 7,0 − V
between Y and Z (ON
condition)
see RONswitch
DD
DD
SS
OZ
January 1995 3
Page 4
Philips Semiconductors Product specification
Quadruple bilateral switches
Fig.4 Test set-up for measuring RON.
HEF4016B
gates
En> V
IH
Iis= 100 µA
VSS=0 V
Fig.5 Typical RONas a function of input voltage.
January 1995 4
Page 5
Philips Semiconductors Product specification
Quadruple bilateral switches
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
Vis→ V
Output disable times
E
→ V
n
Output enable times
E
→ V
n
Distortion, sine-wave 5 − %
Crosstalk between 5 − MHz
Crosstalk; enable 5 − mV
OFF-state 5 − MHz
ON-state frequency 5 − MHz
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
os
52550ns
PHL
15 5 10 ns
52040ns
PLH
15 5 10 ns
os
5 90 130 ns
PHZ
15 75 100 ns
5 85 120 ns
PLZ
15 75 100 ns
os
54080ns
PZH
15 15 30 ns
54080ns
PZL
15 15 30 ns
15 0,04 %
15 − MHz
15 − mV
15 − MHz
15 − MHz
SYMBOL TYP. MAX.
10 20 ns
10 20 ns
80 110 ns
75 100 ns
20 40 ns
20 40 ns
HEF4016B
gates
note 1HIGH to LOW 10 t
note 1LOW to HIGH 10 t
note 2HIGH 10 t
note 2LOW 10 t
note 2HIGH 10 t
note 2LOW 10 t
note 3response 10 0,08 %
note 4any two channels 10 1 MHz
note 5input to output 10 50 mV
note 6feed-through 10 1 MHz
note 7response 10 90 MHz
January 1995 5
Page 6
Philips Semiconductors Product specification
Quadruple bilateral switches
Notes
Visis the input voltage at a Y or Z terminal, whichever is assigned as input.
Vosis the output voltage at a Y or Z terminal, whichever is assigned as output.
1. RL= 10 kΩ to VSS; CL= 50 pF to VSS; En=VDD; Vis=VDD(square-wave); see Figs 6 and 10.
2. RL= 10 kΩ; CL= 50 pF to VSS; En=VDD(square-wave);
Vis=VDDand RLto VSSfor t
Vis=VSSand RLto VDDfor t
3. RL= 10 kΩ; CL= 15 pF; En=VDD; Vis=1⁄2V
fis= 1 kHz; see Fig.7.
4. RL=1 kΩ; Vis=1⁄2V
(B)
V
os
-------------------
20 log
V
(A)
is
DD(p-p)
50 dB; E
5. RL= 10 kΩ to VSS; CL= 15 pF to VSS; En=VDD (square-wave); crosstalk is Vos (peak value);
see Fig.6.
6. RL=1 kΩ; CL= 5 pF; En=VSS;Vis=1⁄2V
PHZ
PLZ
and t
and t
;
PZH
; see Figs 6 and 11.
PZL
(sine-wave, symmetrical about1⁄2VDD);
DD(p-p)
(sine-wave, symmetrical about1⁄2VDD);
(A) VSSE;n(B)=–= VDDsee Fig. 8.;=
n
(sine-wave, symmetrical about1⁄2VDD);
DD(p-p)
HEF4016B
gates
V
os
20 log
7. R
20 log
-------- -
V
=1 kΩ; CL= 5 pF; En=VDD;Vis=1⁄2V
L
V
-------- -
V
os
50 dB; see Fig. 7.–=
is
3 dB; see Fig. 7.–=
is
V
DD
V
TYPICAL FORMULA FOR P (µW)
DD(p-p)
Dynamic power 5 550 f
dissipation per 10 2 600 f
package (P)
(1)
15 6 500 fi+∑(foCL) × V
Note
1. All enable inputs switching.
(sine-wave, symmetrical about1⁄2VDD);
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
January 1995 6
Page 7
Philips Semiconductors Product specification
Quadruple bilateral switches
Fig.6 Fig.7
HEF4016B
gates
Fig.8
Fig.9
January 1995 7
Page 8
Philips Semiconductors Product specification
Quadruple bilateral switches
Fig.10 Waveforms showing propagation delays from Visto Vos.
HEF4016B
gates
(1) Visat V
(2) Visat V
January 1995 8
DD
SS
Fig.11 Waveforms showing output disable and enable times.
Loading...