Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40163B
MSI
4-bit synchronous binary counter
with synchronous reset
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
DESCRIPTION
The HEF40163B is a fully synchronous edge-triggered
4-bit binary counter with a clock input (CP), four
synchronous parallel data inputs (P0to P3), four
synchronous mode control inputs (parallel enable (PE),
count enable parallel (CEP), count enable trickle (CET)
and synchronous reset (SR)), buffered outputs from all
four bit positions (O0to O3) and a terminal count output
(TC).
Operation is fully synchronous and occurs on the LOW to
HIGH transition of CP. When
HIGH transition of CP loads data into the counter from
P0to P3. When PE is HIGH, the next LOW to HIGH
PE is LOW, the next LOW to
HEF40163B
MSI
transition of CP advances the counter to its next state only
if both CEP and CET are HIGH; otherwise no change
occurs in the state of the counter. TC is HIGH when the
state of the counter is 15 (O
CET is HIGH. A LOW on SR sets all outputs (O0to O3and
TC) LOW on the next LOW to HIGH transition of CP,
independent of the state of all other synchronous mode
control inputs (CEP, CET and PE). Multistage
synchronous counting is possible without additional
components by using a carry look-ahead counting
technique; in this case, TC is used to enable successive
cascaded stages. CEP, CET, PE and SR must be stable
only during the set-up time before the LOW to HIGH
transition of CP.
to O3= HIGH) and when
0
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Page 3
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January 1995 3
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
Fig.2 Logic diagram.
HEF40163B
MSI
Page 4
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
Fig.3 Pinning diagram.
HEF40163BP(N): 16-lead DIL; plastic (SOT38-1)
HEF40163BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF40163BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
HEF40163B
MSI
PINNING
PE parallel enable input
P
to P3parallel data inputs
0
CEP count enable parallel input
CET count enable trickle input
CP clock input (LOW to HIGH, edge-triggered)
SR synchronous reset input (active LOW)
O
to O3parallel outputs
0
TC terminal count output
SYNCHRONOUS MODE SELECTION
SR PE CEP CET MODE
H L X X preset
H H L X no change
H H X L no change
H H H H count
L X X X reset
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
TERMINAL COUNT GENERATION
CET (O0⋅ O1⋅ O2⋅ O3)TC
LLL
LHL
HLL
HHH
Note
1. TC = CET ⋅ O0⋅ O1⋅ O2⋅ O
3
January 1995 4
Fig.4 State diagram.
Page 5
Philips Semiconductors Product specification
4-bit synchronous binary counter with
HEF40163B
synchronous reset
AC CHARACTERISTICS
V
= 0 V; T
SS
Dynamic power 5 1 200 f
dissipation per 10 5 600 f
package (P) 15 16 000 f
AC CHARACTERISTICS
= 0 V; T
V
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
CP → TC 5 130 260 ns 103 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
CET → TC 5 105 210 ns 78 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; input transition times ≤ 20 ns
amb
V
DD
V
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
5 110 220 ns 83 ns + (0,55 ns/pF) C
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
SYMBOL MIN. TYP. MAX.
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
5 115 230 ns 88 ns + (0,55 ns/pF) C
PLH
15 35 65 ns 27 ns + (0,16 ns/pF) C
PHL
15 35 75 ns 27 ns + (0,16 ns/pF) C
5 140 280 ns 113 ns + (0,55 ns/pF) C
PLH
15 40 80 ns 32 ns + (0,16 ns/pF) C
PHL
15 35 75 ns 27 ns + (0,16 ns/pF) C
5 90 185 ns 63 ns + (0,55 ns/pF) C
PLH
15 25 50 ns 17 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
TYPICAL EXTRAPOLATION
FORMULA
45 90 ns 34 ns + (0,23 ns/pF) C
45 95 ns 34 ns + (0,23 ns/pF) C
55 105 ns 44 ns + (0,23 ns/pF) C
55 115 ns 44 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 5
Page 6
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
AC CHARACTERISTICS
V
= 0 V; T
SS
Minimum clock 5 100 50 ns
pulse width; LOW 10 t
Set-up times 5 110 55 ns
P
→ CP 10 t
n
PE → CP 10 t
CEP, CET → CP 10 t
SR → CP 10 t
Hold times 5 20 −35 ns
P
→ CP 10 t
n
PE → CP 10 t
CEP, CET → CP 10 t
SR → CP 10 t
Maximum clock 5 2,5 5 MHz
pulse frequency 10 f
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
WCPL
15 30 15 ns
su
15 30 15 ns
5 120 60 ns
su
15 25 10 ns
5 260 130 ns
su
15 70 35 ns
55025ns
su
15 15 10 ns
hold
15 5 −10 ns
515−45 ns
hold
15 5 −10 ns
525−105 ns
hold
15 10 −25 ns
515−10 ns
hold
15 5 0 ns
max
15 9 18 MHz
40 20 ns
40 20 ns
40 20 ns
100 50 ns
20 10 ns
10 −10 ns
5 −15 ns
15 −35 ns
5 −5ns
7 14 MHz
HEF40163B
MSI
see also waveforms
Figs 5, 6, 7 and 8
January 1995 6
Page 7
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
Conditions
PE = LOW
P0 to P3= HIGH
Fig.5 Waveforms showing
set-up and hold times
for SR input and
minimum CP pulse
width.
HEF40163B
MSI
Condition:
PE = SR = HIGH.
Fig.6 Waveforms showing set-up times and hold times for CEP and CET inputs.
January 1995 7
Page 8
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
Conditions
PE = LOW
SR = HIGH
HEF40163B
MSI
Condition
SR = HIGH
Fig.7 Waveforms showing set-up times and hold times for Pninputs.
Fig.8 Waveforms showing set-up times and hold times for PE input.
Note
Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995 8
Page 9
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
HEF40163B
MSI
Fig.9 Timing diagram.
APPLICATION INFORMATION
An example of an application for the HEF40163B is:
• Programmable binary counter.
January 1995 9
Page 10
Philips Semiconductors Product specification
4-bit synchronous binary counter with
synchronous reset
HEF40163B
MSI
NOTE
On the TC outputs, glitches can
occur during counting. In totally
synchronous mode they will not
have any adverse affect. However
the TC output in asynchronous
mode can cause problems.
Fig.10 Synchronous multi-stage counting scheme.
January 1995 10
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