Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40160B
MSI
4-bit synchronous decade counter
with asynchronous reset
Product specification
File under Integrated Circuits, IC04
January 1995
Page 2
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
DESCRIPTION
The HEF40160B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0to P3regardless of the levels
of CEP and CET inputs.
HEF40160B
MSI
PE is HIGH, the next LOW to HIGH transition of CP
When
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
9 (O0=O3= HIGH, O1=O2= LOW) and when CET is
HIGH. A LOW on MR sets all outputs (O0to O3and TC)
LOW, independent of the state of all other inputs.
Multistage synchronous counting is possible without
additional components by using a carry look-ahead
counting technique; in this case, TC is used to enable
successive cascaded stages. CEP, CET and PE must be
stable only during the set-up time before the LOW to HIGH
transition of CP.
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Page 3
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January 1995 3
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
Fig.2 Logic diagram.
HEF40160B
MSI
Page 4
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
Fig.3 Pinning diagram.
HEF40160B
MSI
PINNING
PE parallel enable input
to P3parallel data inputs
P
0
CEP count enable parallel input
CET count enable trickle input
CP clock input (LOW to HIGH, edge-triggered)
MR master reset input (active LOW)
O
to O3parallel outputs
0
TC terminal count output
HEF40160BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40160BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40160BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
SYNCHRONOUS MODE SELECTION
PE CEP CET MODE
L X X preset
H L X no change
H X L no change
H H H count
Notes
1.
MR = HIGH
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
TERMINAL COUNT GENERATION
CET (O0⋅ O1⋅ O2⋅ O3)TC
LLL
LHL
HLL
HHH
Note
1. TC = CET . O0. O1. O2. O
3
January 1995 4
Fig.4 State diagram.
Page 5
Philips Semiconductors Product specification
4-bit synchronous decade counter with
HEF40160B
asynchronous reset
AC CHARACTERISTICS
V
= 0 V; T
SS
Dynamic power 5 1 200 f
dissipation per 10 5 600 f
package (P) 15 16 000 f
AC CHARACTERISTICS
= 0 V; T
V
SS
Propagation delays
CP → O
HIGH to LOW 10 t
LOW to HIGH 10 t
CP → TC 5 130 260 ns 103 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
CET → TC 5 105 210 ns 78 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
MR → O
HIGH to LOW 10 t
MR → TC 5 145 295 ns 118 ns + (0,55 ns/pF) C
HIGH to LOW 10 t
=25°C; input transition times≤ 20 ns
amb
V
DD
V
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
5 110 220 ns 83 ns + (0,55 ns/pF) C
TYPICAL FORMULA FOR P (µW)
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
SYMBOL MIN. TYP. MAX.
PHL
15 30 60 ns 22 ns + (0,16 ns/pF) C
5 115 230 ns 88 ns + (0,55 ns/pF) C
PLH
15 35 65 ns 27 ns + (0,16 ns/pF) C
PHL
15 35 75 ns 27 ns + (0,16 ns/pF) C
5 140 280 ns 113 ns + (0,55 ns/pF) C
PLH
15 40 80 ns 32 ns + (0,16 ns/pF) C
PHL
15 35 75 ns 27 ns + (0,16 ns/pF) C
5 90 185 ns 63 ns + (0,55 ns/pF) C
PLH
15 25 50 ns 17 ns + (0,16 ns/pF) C
n
5 120 245 ns 93 ns + (0,55 ns/pF) C
PHL
15 35 70 ns 27 ns + (0,16 ns/pF) C
PHL
15 45 85 ns 37 ns + (0,16 ns/pF) C
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑ (f
) = sum of outputs
oCL
V
= supply voltage (V)
DD
TYPICAL EXTRAPOLATION
FORMULA
45 90 ns 34 ns + (0,23 ns/pF) C
45 95 ns 34 ns + (0,23 ns/pF) C
55 105 ns 44 ns + (0,23 ns/pF) C
55 115 ns 44 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
35 70 ns 24 ns + (0,23 ns/pF) C
50 100 ns 39 ns + (0,23 ns/pF) C
60 120 ns 49 ns + (0,23 ns/pF) C
MSI
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
January 1995 5
Page 6
Philips Semiconductors Product specification
4-bit synchronous decade counter with
HEF40160B
asynchronous reset
V
DD
V
SYMBOL MIN. TYP. MAX.
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
15 20 40 ns 6 ns + (0,28 ns/pF) C
AC CHARACTERISTICS
V
= 0 V; T
SS
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
SYMBOL MIN. TYP. MAX.
Minimum clock 5 100 50 ns
pulse width; LOW 10 t
WCPL
40 20 ns
15 30 15 ns
Minimum
pulse width; LOW 10 t
MR 5 100 50 ns
WMRL
40 20 ns
15 30 15 ns
Recovery time 5 25 0 ns
for
MR 10 t
RMR
15 0 ns
15 10 0 ns
Set-up times 5 110 55 ns
P
→ CP 10 t
n
su
40 20 ns
15 30 15 ns
5 120 60 ns
PE → CP 10 t
su
40 20 ns
15 25 10 ns
5 260 130 ns
CEP, CET → CP 10 t
su
100 50 ns
15 70 35 ns
Hold times 5 20 −35 ns
P
→ CP 10 t
n
hold
10 −10 ns
15 5 −10 ns
515−45 ns
PE → CP 10 t
hold
5 −15 ns
15 5 −10 ns
525−105 ns
CEP, CET → CP 10 t
hold
15 −35 ns
15 10 −25 ns
TYPICAL EXTRAPOLATION
FORMULA
see also waveforms
Figs 5, 6, 7 and 8
MSI
L
L
L
L
L
L
January 1995 6
Page 7
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
V
DD
V
Maximum clock 5 2,5 5 MHz
pulse frequency 10 f
15 9 18 MHz
Conditions
PE = LOW
P0 to P3= HIGH
SYMBOL MIN. TYP. MAX.
max
7 14 MHz
HEF40160B
MSI
Fig.5 Waveforms showing
minimum CP and MR pulse
widths and MR to CP
recovery time.
Conditions: PE = MR = HIGH.
Fig.6 Waveforms
showing
set-up times
and hold times
for CEP and
CET inputs.
January 1995 7
Page 8
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
Conditions
PE = LOW
MR = HIGH
HEF40160B
MSI
Condition
MR = HIGH
Fig.7 Waveforms showing set-up times and hold times for Pninputs.
Fig.8 Waveforms showing set-up times and hold times for PE inputs.
Note
Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995 8
Page 9
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
Fig.9 Timing diagram.
APPLICATION INFORMATION
An example of an application for the HEF40160B is:
• Programmable decade counter.
January 1995 9
Page 10
Philips Semiconductors Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
NOTE
On the TC outputs, glitches can occur
during counting. In totally synchronous
mode they will not have any adverse
affect. However the TC output in
asynchronous mode can cause
problems.
Fig.10 Synchronous multi-stage counting scheme.
January 1995 10
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