Datasheet HDMP-1636, HDMP-1646 Datasheet (HP)

711

HDMP-1636 Transceiver
HDMP-1646 Transceiver

Features

• IEEE 802.3z Gbit Ethernet
Compatible, Supports 1250
MBd Gigabit Ethernet

• Based on X3T11 “10 Bit
Specification”

• Low Power Consumption

• Transmitter and Receiver
Functions Incorporated onto
a Single IC

• Two Package Sizes
Available:

– 10 mm PQFP (HDMP-1636)
– 14 mm PQFP (HDMP-1646)

• 10-Bit Wide Parallel TTL
Compatible I/Os

• Single +3.3 V Power Supply

• 5-Volt Tolerant I/Os

• 2 KV ESD Protection

Applications

• 1250 MBd Gigabit Ethernet
Interface

• High Speed Proprietary
Interface

• Backplane Serialization

• Bus Extender

Description

The HDMP-1636/46 transceiver is
a single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It

Gigabit Ethernet Transceiver Chip

Preliminary Technical Data

provides complete Serialize/
Deserialize for copper transmis­sion, incorporating both the
Gigabit Ethernet transmit and
receive functions into a single
device.

This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.

The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or equiv­alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).

The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is
then multiplied by 10, to gener­ate the 1250 MHz serial signal
clock used to generate the high
speed output. The high speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber optic module for
optical transmission.

The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.

The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.

For test purposes, the transceiver
provides for on-chip local loop­back functionality, controlled
through an external input pin.
Additionally, the byte

(5/97)

712

± DOUT

TX

PLL/CLOCK

GENERATOR

REFCLK

± DIN

RXCAP0
RXCAP1

RBC0
RBC1

BYTSYNC ENBYTSYNC

OUTPUT

DRIVER

INTERNAL
TX CLOCKS

INPUT

LATCH

DATA BYTE

RX[0-9]

TXCAP1

TXCAP0

DATA BYTE

TX[0-9]

INTERNAL

RX CLOCKS

LOOPEN

INTERNAL

LOOPBACK

OUTPUT
SELECT

FRAME

MUX

RX
PLL/CLOCK
RECOVERY

INPUT

SELECT

FRAME
DEMUX

AND

BYTE SYNC

INPUT

SAMPLER

HDMP-16x6

PROTOCOL DEVICE

SERIAL DATA OUT

RECEIVER SECTION

PLL

TRANSMITTER SECTION

BYTSYNC

ENBYTSYNC

REFCLK

SERIAL DATA IN

PLL

Figure 1. Typical Application Using the HDMP-16x6.

Figure 2. HDMP-16x6 Transceiver Block Diagram.

713

synchronization feature may be
disabled. This may be useful in
proprietary applications which
use alternative methods to align
the parallel data.

HDMP-1636/46 Block
Diagram

The HDMP-1636/46 was
designed to transmit and receive
10-bit wide parallel data over a
single high-speed line. The
parallel data applied to the trans­mitter is expected to be encoded
per the Gigabit Ethernet specifi­cation, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order
to accomplish this task, the
HDMP-1636/46 incorporates the
following:

• TTL Parallel I/O’s

• High Speed Phase Lock Loops

• Clock Generation/Recovery
Circuitry

• Parallel to Serial Converter

• High Speed Serial Clock and
Data Recovery Circuitry

• Comma Character Recognition
Circuitry

• Byte Alignment Circuitry

• Serial to Parallel Converter

INPUT LATCH

The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.

TX PLL/CLOCK GENERATOR

The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is
used as both the frequency
reference clock for the PLL and
the transmit byte clock for the
incoming data latches. It is
expected to be 125 MHz and
properly aligned to the incoming
parallel data (see Figure 3). This
clock is then multiplied by 10 to
generate the 1250 MHz clock
necessary for the high speed
serial outputs.

FRAME MUX

The FRAME MUX accepts the 10­bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the 1250 MBd serial data stream.
The data bits are transmitted
sequentially, from the least
significant bit (TX[0]) to the
most significant bit (TX[9]).

OUTPUT SELECT

The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal, for testing purposes.

In normal operation, LOOPEN is
set low and the serial data stream
is placed at +/- DOUT. When
wrap-mode is activated by setting

LOOPEN high, the +/- DOUT
pins are held static at logic 1 and
the serial output signal is
internally wrapped to the INPUT
SELECT box of the receiver
section.

INPUT SELECT

The INPUT SELECT block
determines whether the signal at
+/- DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
+/- DIN. When LOOPEN is set
high, the high speed serial signal
is internally looped-back from the
transmitter section to the
receiver section. This feature
allows for loop back testing
exclusive of the transmission
medium.

RX PLL/CLOCK RECOVERY

The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the
incoming serial data stream and
recovering the bit and byte
clocks. An automatic locking
feature allows the Rx PLL to lock
onto the input data stream
without external controls. It does
this by continually frequency
locking onto the 125 MHz clock,
and then phase locking onto the
input data stream. An internal
signal detection circuit monitors
the presence of the input, and
invokes the phase detection as
the data stream appears. Once bit
locked, the receiver generates the
high speed sampling clock at
1250 MHz for the input sampler,
and recovers the two 62.5 Mhz

714

HDMP-1636/46 (Transmitter Section)

Timing Characteristics

TA = 0°C to +60°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Units Min. Typ. Max.

t

setup

Setup Time nsec 2

t

hold

Hold Time nsec 1

t_txlat

[1]

Transmitter Latency nsec TBD

bits TBD

Note:

1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered

by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).

receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock the 10-bit parallel
output data.

INPUT SAMPLER

The INPUT SAMPLER is respon­sible for converting the serial
input signal into a re-timed serial
bit stream. In order to accom­plish this, it uses the high speed
serial clock recovered from the
RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.

FRAME DEMUX AND BYTE
SYNC

The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the

next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 2-byte ordered set. The
second comma character
received shall be aligned with the
rising edge of RBC1. Comma
characters should not be trans­mitted in consecutive bytes to
allow the receiver byte clocks to
maintain their proper recovered
frequencies.

OUTPUT DRIVERS

The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide TTL
compatible signals.

715

Figure 3. Transmitter Section Timing.

Figure 4. Transmitter Latency.

DATA DATA

TX[0]-TX[9]

t

SETUP

t

HOLD

REFCLK

DATA

DATA DATA

1.4 V

2.0 V

0.8 V

DATA BYTE B DATA BYTE C

TX[0]-TX[9]

DATA BYTE A

± DOUT

1.4 V

DATA BYTE B

t_TXLAT

T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5

REFCLK

716

HDMP-1636/46 (Receiver Section)

Timing Characteristics

TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Units Min. Typ. Max.

b_sync

[1,2]

Bit Sync Time bits 2500

t

valid_before

Time Data Valid Before Rising Edge of RBC nsec 2.5 TBD

t

valid_after

Time Data Valid After Rising Edge of RBC nsec 1.5 TBD

t

duty

RBC Duty Cycle % 40 60

t

A-B

Rising Edge Time Difference nsec 7.5 7.9 8.5

t_rxlat

[3]

Receiver Latency nsec 22.4

bits 28

Notes:

1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.

2. Tested using C

PLL

= 0.1 µF.

3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word

(defined as the first edge of the first serial) and the clocking out of that parallel word (defined by the rising edge of the receive byte
clock, either RBC1 or RBC0).

DATA DATA

X[0]-RX[9]

t

valid_before

t

valid_after

RBC1

,

K28.5

DATA DATA

1.4 V

2.0 V

0.8 V

BYTSYNC

RBC0

t

A-B

2.0 V

0.8 V

1.4 V

Figure 6. Receiver Latency.

Figure 5. Receiver Section Timing.

717

HDMP-1636/46 (TRx)
Absolute Maximum Ratings

TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent
damage to this device.

Symbol Parameter Units Min. Max.

V

CC

Supply Voltage V -0.5 5.0

V

IN,TTL

TTL Input Voltage V -0.7 VCC + 0.7

V

IN,HS_IN

HS_IN Input Voltage V 2.0 V

CC

I

O,TTL

TTL Output Source Current mA 13

T

stg

Storage Temperature °C -40 +130

T

j

Junction Operating Temperature °C 0 +130

HDMP-1636/46 (TRx)
DC Electrical Specifications

TA= 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Unit Min. Typ. Max.

V

IH,TTL

TTL Input High Voltage Level, Guaranteed High Signal V 2 V

CC

for All Inputs

V

IL,TTL

TTL Input Low Voltage Level, Guaranteed Low Signal for V 0 0.8
All Inputs

V

OH,TTL

TTL Output High Voltage Level, IOH = -400 µA V 2.2 V

CC

V

OL,TTL

TTL Output Low Voltage Level, IOL = 1 mA V 0 0.6

I

IH,TTL

Input High Current (Magnitude), VIN = V

CC

µA 0.003 40

I

IL-TTL

Input Low Current (Magnitude), VIN = 0 Volts µA -366 -600

I

CC,TRx

[1,2]

Transceiver VCC Supply Current, TA = 25°C mA 205

Notes:

1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial BERT with both DOUT outputs biased with

150 Ω resistors.

2. Typical specified with VCC = 3.3 volts, maximum specified with VCC = 3.45 volts.

HDMP-1636/46 (TRx)
Transceiver Reference Clock Requirements

TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Unit Min. Typ. Max.

f Nominal Frequency (for Gigabit Ethernet Compliance) MHz 125

F

tol

Frequency Tolerance ppm -100 +100

Symm Symmetry (Duty Cycle) % 40 60

HDMP-1636/46 (TRx)
Guaranteed Operating Rates

T

A

= 0°C to +70°C, VCC = 3.15 V to 3.45 V

Parallel Clock Rate (MHz) Serial Baud Rate (MBaud)

Min. Max. Min. Max.

124.0 126.0 1240 1260

718

HDMP-1636/46 (TRx)
AC Electrical Specifications

TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Units Min. Typ. Max.

t

r,TTLin

Input TTL Rise Time, 0.8 to 2.0 Volts nsec 2

t

f,TTLin

Input TTL Fall Time, 2.0 to 0.8 Volts nsec 2

t

r,TTLout

Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load nsec 1.5 2.4

t

f,TTLout

Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load nsec 1.1 2.4

t

rs,HS_OUT

HS_OUT Single-Ended (+DOUT) Rise Time psec 85 TBD 327

t

fs,HS_OUT

HS_OUT Single-Ended (+DOUT) Fall Time psec 85 TBD 327

t

rd,HS_OUT

HS_OUT Differential Rise Time psec 85 327

t

fd,HS_OUT

HS_OUT Differential Fall Time psec 85 327

V

IP,HS_IN

HS_IN Input Peak-to-Peak Differential Voltage mV 200 1200 2000

V

OP,HS_OUT

[1]

HS_OUT Output Peak-to-Peak Differential Voltage mV 1200 1580 2200

Note:

1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.

a. Differential HS_OUT Output (Dout+ Minus Dout-).

Figure 7. Transmitter DOUT Eye Diagrams.

b. Single-Ended HS_OUT Output (Dout+).

Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1636/46
as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 27-1.

22.0680 ns Yaxis = 400 mV/DIV

22.0680 ns Yaxis = 200 mV/DIV

719

HP70841B
PATTERN

GENERATOR

HP83480A

OSCILLOSCOPE

HDMP-1636

HP70311A

CLOCK SOURCE

+ DATA

- DATA

+K28.5, -K28.5

TRIGGER

CH1 CH2

+DOUT -DOUT

REFCLK LOOPEN

Tx[0..9]

1.25 GHz

125 MHz

ENBYTSYNC

Rx[0..9]

-DIN

+DIN

DIVIDE

BY 2

CIRCUIT

DIVIDE

BY 10

CIRCUIT

(DUAL

OUTPUT)

VARIABLE

DELAY

TTL

HDMP-1636/46 (Transmitter Section)
Output Jitter Characteristics

TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Units Typ.

RJ

[1]

Random Jitter at DOUT, the High Speed Electrical Data Port, specified as ps 8
1 sigma deviation of the 50% crossing point (RMS)

DJ

[1]

Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk) ps 15

Note:

1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method
shown in Figure 8.

HDMP-1636/46 (TRx)
Thermal and Power Temperature Characteristics

TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V

Symbol Parameter Units Typ. Max.

P

D,TRx

[1,2]

Transceiver Power Dissipation, Outputs Open, Parallel Data mW 630 850
has 5 Ones and 5 Zeroes

P

D,TRx

[1,2,3]

Transceiver Power Dissipation, Outputs Connected per mW 685 900
Recommended Bias Terminations with Idle Pattern

Θ

jc

[4]

Thermal Resistance, Junction to Case HDMP-1636 °C/Watt 10

HDMP-1646 7

Notes:

1. PD is obtained by multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed
bias resistors.

2. Typical value specified with VCC = 3.3 volts, maximum value specified with VCC = 3.45 volts.

3. Specified with high speed outputs biased with 150 Ω resistors and receiver TTL outputs driving 10 pF loads.

4. Based on independent package testing by HP. Θja for these devices is 48°C/Watt for the HDMP-1636 and 44°C/Watt for the
HDMP-1646. Θja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature
in a given application, use the value as described as follows: Tj = TC + (Θjc x Pd), where TC is the case temperature measured on
the top center of the package and PD is the power being dissipated.

Figure 8. Transmitter Jitter Measurement Method.

a. Block Diagram of RJ Measurement Method. b. Block Diagram of DJ Measurement Method.

HP70841B
PATTERN

GENERATOR*

HP83480A

OSCILLOSCOPE

HDMP-1636

HP70311A

CLOCK SOURCE

+ DATA

- DATA

0000011111

TRIGGER

CH1 CH2

+DOUT -DOUT

REFCLK

LOOPEN

Tx[0..9]

BIAS

TEE

1.4 V

0011111000

(STATIC K28.7)

1.25 GHz

125 MHz

* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.

720

I/O Type Definitions

I/O Type Definition

I-TTL Input TTL, Floats High When Left Open

O-TTL Output TTL

HS_OUT High Speed Output, ECL Compatible

HS_IN High Speed Input

C External Circuit Node
S Power Supply or Ground

HDMP-1636/46 (TRx)
Pin Input Capacitance

Symbol Parameter Units Typ. Max.

C

INPUT

Input Capacitance on TTL Input Pins pF 1.6

Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic.
Notes:

1. HS_IN inputs should never be connected to ground as permanent damage to the device may result.

2. The optional series padding resistors (Rpad) help dampen load reflections. Typical Rpad values for mismatched loads range
between 25-75 Ω.

Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.

VCC_TTL

R

V

BB

1.4 V

R

GND_TTL

VCC_TX

or

V

CC

_RX

ESD

PROTECTION

GND_TTL

V

CC

_TTL

R

RR

O_TTL I_TTL

GND

ESD

PROTECTION

VCC_TX

HS_OUT

R

0.01

0.01

Zo = 75 Ω

Zo = 75 Ω

VCC_TXHS
VCC_TXECL

GND

ESD

PROTECTION

-DOUT

+DOUT

150

150

R

PAD

R

PAD

GND_TXHS

+DIN

-DIN

ESD

PROTECTION

R

+
–

+
–

HS_IN

150

VCC_RX

GND

GND_RXHS

VCC_RXHS

721

RXCAP0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

GND_TXHS

HDMP-16x6

xxxx-x Rz.zz

S YYWW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BYTSYNC
GND_RXTTL
RX[0]
RX[1]
RX[2]
V

CC

_RXTTL
RX[3]
RX[4]
RX[5]
RX[6]
V

CC

_RXTTL
RX[7]
RX[8]
RX[9]
GND_RXTTL

GND_TXTTL

TX[0]
TX[1]
TX[2]

V

CC

_TXTTL

TX[3]
TX[4]
TX[5]
TX[6]

V

CC

_TXTTL

TX[7]
TX[8]
TX[9]

GND_TXTTL

GND_TXA

TXCAP1

V

CC

_TXHS

+DOUT

-DOUT

V

CC

_TXECL

V

CC

_TX

GND

V

CC

_RX

GND_RXHS

V

CC

_RXHS

+DIN

V

CC

_RXHS

-DIN

GND_RXA

V

CC

_RXA

RXCAP1

TXCAP0

V

CC

_TXA

LOOPEN

V

CC

_TX

GND

REFCLK

V

CC

_RX

ENBYTSYNC

GND

N/C

*

V

CC

_RX

V

CC

_RXTTL

RBC1

RBC0

GND_RXTTL

xxxx-x = WAFER LOT NUMBER–BUILD NUMBER
Rzz.zz = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
(MARKED ON BACK OF DEVICE)

N/C

*

Figure 11. HDMP-1636/46 (TRx) Package Layout and Marking, Top View.

*Note: Pins 26 and 27 are designated as “no connect” pins and must be left unconnected.

722

TRx I/O Definition

Name Pin Type Signal

BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of

a comma character (0011111XXX). It is only active when
ENBYTSYNC is enabled.

-DIN 52 HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the

+DIN 54 ± DIN inputs when LOOPEN is low.

-DOUT 61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when

+DOUT 62 LOOPEN is set low. When LOOPEN is set high, these outputs are held

static at logic 1.

ENBYTSYNC 24 I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync

function to allow clock synchronization to a comma character,
(0011111XXX). When the line is low, the function is disabled and will
not reset registers and clocks, or strobe the BYTSYNC line.

GND 21 S Logic Ground: Normally 0 volts. This ground is used for internal PECL

25 logic. It should be isolated from the noisy TTL ground as well as possible.
58

GND_RXA 51 S Analog Ground: Normally 0 volts. Used to provide a clean ground

plane for the receiver PLL and high-speed analog cells.

GND_RXHS 56 S Ground: Normally 0 volts.

GND_RXTTL 32 S TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells

33 of the receiver section.
46

GND_TXA 15 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane

for the PLL and high-speed analog cells.

GND_TXHS 64 S Ground: Normally 0 volts.

GND_TXTTL 1 S TTL Transmitter Ground: Normally 0 volts. Used for the TTL input

14 cells of the transmitter section.

LOOPEN 19 I-TTL Loopback Enable Input: When set high, the high-speed serial signal is

internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static at logic 1. When set low, ± DOUT outputs
and ± DIN inputs are active.

RBC1 30 O-TTL Receiver Byte Clocks: The receiver section recovers two 62.5 MHz
RBC0 31 receive byte clocks. These two clocks are 180 degrees out of phase.

The receiver parallel data outputs are alternately clocked on the
rising edge of these clocks. The rising edge of RBC1 aligns with the
output of the comma character (for byte alignment) when detected.

REFCLK 22 I-TTL Reference Clock and Transmit Byte Clock: A 125 MHz clock

supplied by the host system. The transmitter section accepts this signal
as the frequency reference clock. It is multiplied by 10 to generate the
serial bit clock and other internal clocks. The transmit side also uses this
clock as the transmit byte clock for the incoming parallel data
TX[0]..TX[9]. It also serves as the reference clock for the receive
portion of the transceiver.

N/C 26,27 These pins are factory test pins and must be left unconnected.

723

TRx I/O Definition (cont’d.)

Name Pin Type Signal

RX[0] 45 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received.
RX[1] 44 RX[0] is the least significant bit.
RX[2] 43
RX[3] 41
RX[4] 40
RX[5] 39
RX[6] 38
RX[7] 36
RX[8] 35
RX[9] 34

RXCAP0 48 C Loop Filter Capacitor: A loop filter capacitor for the internal PLL must
RXCAP1 49 be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 µF).

TX[0] 2 I-TTL Data Inputs: One 10 bit, 8B/10B-encoded data byte. TX[0] is the first
TX[1] 3 bit transmitted. TX[0] is the least significant bit.
TX[2] 4
TX[3] 6
TX[4] 7
TX[5] 8
TX[6] 9
TX[7] 11
TX[8] 12
TX[9] 13

TXCAP1 16 C Loop Filter Capacitor: A loop filter capacitor must be connected across
TXCAP0 17 the TXCAP1 and TXCAP0 pins (typical value = 0.1 µF).

VCC_RX 23 S Logic Power Supply: Normally 3.3 volts. Used for internal receiver

28 PECL logic. It should be isolated from the noisy TTL supply as well as
57 possible.

VCC_RXA 50 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean

supply line for the PLL and high-speed analog cells.

VCC_RXHS 53 S High-Speed Supply: Normally 3.3 volts. Used only for the high-speed

55 receiver cell (HS_IN). Noise on this line should be minimized for best

operation.

VCC_RXTTL 29 S TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver output

37 buffer cells.
42

VCC_TX 20 S Logic Power Supply: Normally 3.3 volts. Used for internal transmitter PECL

59 logic. It should be isolated from the noisy TTL supply as well as possible.

VCC_TXA 18 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean

supply line for the PLL and high-speed analog cells.

VCC_TXECL 60 S High-Speed ECL Supply: Normally 3.3 volts. Used only for the last stage

of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 10. Due to high current transitions, this VCC should be well
bypassed to a ground plane.

VCC_TXHS 63 S High-Speed Supply: Normally 3.3 volts. Used by the transmitter side for the

high-speed circuitry. Noise on this line should be minimized for best operation.

VCC_TXTTL 5 S TTL Power Supply: Normally 3.3 volts. Used for all TTL

10 transmitter input buffer cells.

724

RXCAP0

V

CC

_RXTTL

V

CC

_RXTTL

GND_TXHS

TOP VIEW

GND_RXTTL

GND_TXTTL

V

CC

_TXTTL

V

CC

_TXTTL

GND_TXTTL
GND_TXA

TXCAP1

V

CC

_TXHS

V

CC

_TXECL

V

CC

_TX

GND

V

CC

_RX

GND_RXHS

V

CC

_RXHS

V

CC

_RXHS

GND_RXA

V

CC

_RXA

RXCAP1

* SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
AND PLL FILTER CAPACITORS ARE 0.1 µF.

V

CC

_TX

GND

V

CC

VCC*

V

CC

GND_RXTTL

TXCAP0

V

CC

_TXA

GND

V

CC

_RX

GND_RXTTL

V

CC

_RXTTL

V

CC

_RX

C

PLLT

VCC*

C

PLLR

Figure 12. Power Supply Bypass.

Start-up Procedure:

The transceiver start-up
procedure(s) use the following
conditions: VCC = +3.3 V ± 5%
and REFCLK = 125 MHz ± 100
ppm.

After the above conditions have
been met, apply valid data using a
balanced code such as 8B/10B.
Frequency lock occurs within
500 µs. After frequency lock,
phase lock occurs within 2500 bit
times.

Transceiver Power
Supply Bypass and Loop
Filter Capacitors

Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate

power supply pins of the
HDMP-1636/46 as shown on the
schematic of Figure 12. All
bypass chip capacitors are

0.1 µF. The VCC_RXA and
VCC_TXA pins are the analog
power supply pins for the PLL
sections. The voltage into these
pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 12. Notice that only two
capacitors are required: C

PLLT

for

the transmitter and C

PLLR

for the

receiver. Nominal capacitance is

0.1 µF. The voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP­1636/46. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.

PRE-RELEASE PRODUCT

DISCLAIMER:

This product is in development at
the Hewlett-Packard CSSD in San
Jose, California. Until Hewlett­Packard releases this product for
general sales, HP reserves the right to
alter specifications, features,
capabilities, functions, manufacturing
release dates, and even general
availability of the product at any time.

725

Package Information

Item Details

Package Material Plastic
Lead Finish Material 85% Tin, 15% Lead
Lead Finish Thickness 300-800 µm
Lead Coplanarity HDMP-1636 0.08 mm max

HDMP-1646 0.10 mm max

Mechanical Dimensions

Figure 13. Mechanical Dimensions of HDMP-1636/46.

A1

A2

PIN #1 ID

A1
A2

B1

B4

B3

C1

C2

B2

ALL DIMENSIONS ARE IN MILLIMETERS.

B5

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

HDMP-16x6

TOP VIEW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C3

PART NUMBER A1 A2 B1 B2 B3 B4 B5 C1 C2 C3

HDMP-1636 10.00 13.20 0.22 0.50 0.60 0.17 0.25 2.00

0.25

MIN.

2.45

HDMP-1646 14.00 17.20 0.35 0.80 0.88 0.17 0.25 2.00

0.25

MAX.

2.35

TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/

– 0.10

MAX.

+ 0.10/

– 0.05

MAX.