Datasheet HD74ALVCH16260 Datasheet (HIT)

HD74ALVCH16260

12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs

ADE-205-135B (Z)

3rd. Edition

December 1999

Description

The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two
separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical
applications include multiplexing and / or demultiplexing of address and data information in
microprocessor or bus interface applications. This device is also useful in memory interleaving
applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and /
or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and / or data
information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is
transparent. When the latch enable input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high. Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±24 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

HD74ALVCH16260

Function Table

Inputs Output A
1B 2B SEL LE1B LE2B OEA

HX HH XL H
LX HH XL L
XX HL XL A
XH LX HL H
XL LX HL L
XX LX LL A
XX XX XH Z

B-to-A (OEB = H)

Inputs Outputs
A LEA1B LEA2B OE1B OE2B 1B 2B

HH HL LH H
LH HL LL L
HH LL LH 2B
LH LL LL 2B
HL HL L1B
LL HL L1B
XL LL L1B

*1

0

*1

0

*1

0

XX XH HZ Z
X X X L H Active Z
X X X H L Z Active
X X X L L Active Active

A-to-B (OEA = H)

0

0

*1

*1

H
L
2B

*1

0

*1

0

*1

0

H : High level
L : Low level
X : Immaterial
Z : High impedance
Note: 1. Output level before the indicated steady state input conditions were established.

2

Pin Arrangement

HD74ALVCH16260

OEA

LE1B

2B3

GND

2B2
2B1

V

CC

A1
A2

A3

GND

A4
A5

A6
A7

A8
A9

GND

A10
A11
A12
V

CC

1B1
1B2

GND

1B3

LE2B

SEL

10
11

12
13
14

15
16

17
18

19

20
21
22
23
24
25
26
27
28

OE2B

1
2

3
4
5

6
7

8

9

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

LEA2B
2B4
GND
2B5
2B6

V

CC

2B7
2B8

2B9
GND

2B10
2B11

2B12
1B12
1B11

1B10
GND
1B9
1B8
1B7
V

CC

1B6
1B5
GND
1B4
LEA1B

OE1B

(Top view)

3

HD74ALVCH16260

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage

Output voltage

*1, 2

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation

at Ta = 55°C (in still air)

*3

CC

V

I

V

O

IK

OK

O

GND

P

T

Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 4.6 V Except I/O ports
–0.5 to VCC +0.5 I/O ports
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100 mA
1 W TSSOP

CC

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage V
Input voltage V
Output voltage V
High level output current I

Low level output current I

CC

I

O

OH

OL

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

4

2.3 3.6 V
0VCCV
0VCCV
— –12 mA VCC = 2.3 V
— –12 VCC = 2.7 V
— –24 VCC = 3.0 V
—12mAV
—12 V
—24 V

= 2.3 V

CC

= 2.7 V

CC

= 3.0 V

CC

Logic Diagram

HD74ALVCH16260

LE1B

LE2B
LEA1B
LEA2B

OE2B

OE1B

OEA

SEL

A1

2
27
30
55

56

29

1

28

8

G1

1

1

C1

1D

C1

1D

C1

1D

C1

1D

23

1B1

6

2B1

To eleven other channels

5

HD74ALVCH16260

Electrical Characteristics (Ta = –40 to 85°C)

Item Symbol V

Input voltage V

IH

(V) *1Min Max Unit Test Conditions

CC

2.3 to 2.7 1.7 — V

2.7 to 3.6 2.0 —

V

IL

2.3 to 2.7 — 0.7

2.7 to 3.6 — 0.8

Output voltage V

OH

Min to Max VCC–0.2 — V IOH = –100 µA

2.3 2.0 — IOH = –6 mA, VIH = 1.7 V

2.3 1.7 — IOH = –12 mA, VIH = 1.7 V

2.7 2.2 — IOH = –12 mA, VIH = 2.0 V

3.0 2.4 — IOH = –12 mA, VIH = 2.0 V

3.0 2.0 — IOH = –24 mA, VIH = 2.0 V

V

OL

Min to Max — 0.2 IOL = 100 µA

2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V

2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V

2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V

3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V

Input current I

IN

I

IN (hold)

3.6 — ±5 µAVIN = VCC or GND

2.3 45 — VIN = 0.7 V

2.3 –45 — VIN = 1.7 V

3.0 75 — VIN = 0.8 V

3.0 –75 — VIN = 2.0 V

3.6 — ±500 VIN = 0 to 3.6 V
Off state output current *2I
Quiescent supply current I

OZ

CC

∆I

3.6 — ±10 µAV

= VCC or GND

OUT

3.6 — 40 µAVIN = VCC or GND

3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6) V,

CC

other inputs at V

or GND

CC

Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

2. For I/O ports, the parameter I

includes the input leakage current.

OZ

6

HD74ALVCH16260

Switching Characteristics (Ta = –40 to 85°C)

Item Symbol VCC (V) Min Typ Max Unit FROM

(Input)TO(Output)

Maximum clock frequency f

Propagation delay time t

Output enable time t

Output disable time t

Setup time t

Hold time t

Pulse width t

Input capacitance C
Output capacitance C

max

PLH

t

PHL

ZH

t

ZL

HZ

t

LZ

su

h

w

IN

IN / O

2.5±0.2 150 — — MHz

2.7 150 — —

3.3±0.3 150 — —

2.5±0.2 1.2 — 5.6 ns A or B B or A

2.7 — — 5.1

3.3±0.3 1.2 — 4.3

2.5±0.2 1.0 — 6.2 LE A or B

2.7 — — 5.2

3.3±0.3 1.0 — 4.4

2.5±0.2 1.2 — 6.9 SEL A

2.7 — — 6.6

3.3±0.3 1.1 — 5.6

2.5±0.2 1.0 — 6.7 ns OE A or B

2.7 — — 6.4

3.3±0.3 1.0 — 5.4

2.5±0.2 1.7 — 5.7 ns OE A or B

2.7 — — 5.0

3.3±0.3 1.3 — 4.6

2.5±0.2 1.4 — — ns

2.7 1.1 — —

3.3±0.3 1.1 — —

2.5±0.2 1.6 — — ns

2.7 1.9 — —

3.3±0.3 1.5 — —

2.5±0.2 3.3 — — ns

2.7 3.3 — —

3.3±0.3 3.3 — —

3.3 — 3.5 — pF Control inputs

3.3 — 9.0 — pF A or B ports

7

HD74ALVCH16260

• Test Circuit

500 Ω

See under table

S1

OPEN

*1

L

500 ΩC = 50 pF

GND

Load Circuit for Outputs

Symbol

t / t

PLH PHL

t / t / t

su h w

t / t

ZH HZ

t / t

ZL LZ

Note: 1. C includes probe and jig capacitance.

L

Vcc=2.5±0.2V

OPEN

GND

4.6 V 6.0 V

Vcc=2.7V,

3.3±0.3V

OPEN

GND

8

HD74ALVCH16260

• Waveforms – 1

Input

Output

• Waveforms – 2

Timing Input

Data Input

Input

10 %

90 %

tf

V

IH

V

ref

10 %

t

PHL

V

ref

GND

V

OH

V

OL

tr

90 %

V

ref

t

PLH

V

ref

tr

V

90 %

V

ref

10 %

t

su

V

ref

t

h

V

ref

IH

GND

V

IH

GND

t

w

V

IH

V

ref

V

ref

GND

9

HD74ALVCH16260

• Waveforms – 3

trtf

Output
Control

Waveform - A

Waveform - B

90 %

V

ref

10 % 10 %

t

ZL

V

ref

t

ZH

V

ref

Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

V

90 %

ref

t

t

HZ

LZ

TEST

V

IH

V

ref

V

OH1

V

OL1

V + 0.3 V

OL

V – 0.3 V

OH

Vcc=2.5±0.2V

2.3 V 2.7 V

1.2 V 1.5 V

2.3 V 3.0 V
GND

V

GND

≈V

V
V

≈V

Vcc=2.7V,

3.3±0.3V

GND

IH

OH1

OL

OH

OL1

10

Package Dimensions

14.00

+0.3
–0.1

HD74ALVCH16260

Unit : mm

2956

+0.3

–0.1

6.10

128

+0.1

0.20

–0.05

0.50

0.08

M

0.40 Max

0.10

0.05 Min

1.20 max

8.10 ± 0.3

0.15 ± 0.05

JEDEC code

Hitachi code

EIAJ code

10° Max

0.50 ± 0.1

TTP-56D

—
—

11

HD74ALVCH16260

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

12

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