Datasheet HD74ALVCH162270 Datasheet (HIT)

HD74ALVCH162270

12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs

ADE-205-178A (Z)

2nd. Edition

March 1998

Description

The HD74ALVCH162270 is used in applications where data must be transferred from a narrow high speed
bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the
appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data
transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage
register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to
be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output
enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with
CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All
outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and
undershoot.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±12 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.

HD74ALVCH162270

Function Table

Inputs Outputs
CLK OEA OEB A 1B, 2B

↑ HHZZ
↑H L Z Active
↑ L H Active Z
↑ L L Active Active

Output enable

Inputs Outputs
CLKENA1 CLKENA2 CLK A 1B 2B

XH↑L1B
XH↑H1B
LL↑LL

*1, 2

0

*1, 2

0

*2

LL↑HH *2H
HL↑L1B
HL↑H1B
HHXX1B

*1L

0

*1H

0

*12B0

0

A-to-B storage (OEB = L)

2B0
2B0
L

*1

*1

*1

Note: This functional table describes the case of transferring the same data for A to 1B path. For the case

of transferring different data, see logic diagrams.

2

HD74ALVCH162270

Inputs Output A
CLKEN1B CLKEN2B CLK SEL 1B 2B

HXXHXXA
XHXLXXA
LX↑HL XL
LX↑HHXH
XL ↑LXLL
XL ↑LXHH

B-to-A storage (OEA = L)

H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.

2. Two CLK edges are needed to propagate data.

*1

0

*1

0

3

HD74ALVCH162270

Pin Arrangement

OEA

CLKEN1B

2B3

GND

2B2
2B1

V

CC

A1
A2

A3

GND

A4
A5

A6
A7

A8
A9

GND

A10
A11
A12
V

CC

1B1
1B2

GND

1B3

CLKEN2B

SEL

10
11

12
13
14

15
16

17
18

19

20
21
22
23
24
25
26
27
28

OEB

1
2

3
4
5

6
7

8

9

56

CLKENA2

55
54

2B4

53

GND
2B5

52
51

2B6

50

V

2B7

49

2B8

48
47

2B9

46

GND
2B10

45

2B11

44
43

2B12

42

1B12
1B11

41

1B10

40

GND

39
38

1B9
1B8

37

1B7

36
35

V

34

1B6

33

1B5

32

GND

31

1B4

30

CLKENA1

29

CLK

CC

CC

(Top view)

4

HD74ALVCH162270

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage

Output voltage

*1, 2

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation

at Ta = 55°C (in still air)

*3

CC

V

I

V

O

IK

OK

O

GND

P

T

Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 4.6 V Except I/O ports
–0.5 to VCC +0.5 I/O ports
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100 mA
1 W TSSOP

CC

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage V
Input voltage V
Output voltage V
High level output current I

Low level output current I

CC

I

O

OH

OL

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

2.3 3.6 V
0VCCV
0VCCV
—–6mAV
—–8 V

= 2.3 V

CC

= 2.7 V

CC

— –12 VCC = 3.0 V
— 6 mA VCC = 2.3 V
—8 V
—12 V

= 2.7 V

CC

= 3.0 V

CC

5

HD74ALVCH162270

Logic Diagram

29

CLK

CLKEN1B

CLKEN2B

CLKENA1

CLKENA2

OEB

SEL

OEA

A1

2

27

30

55

56

28

1

8

C1

1D

G1

C1

1D

CE

C1

1D

1

1

CE

C1

1D

23

1B1

6

2B1

CE

C1

1D

1 of 12 Channels

CE

C1

1D

CE

C1

1D

6

Electrical Characteristics (Ta = –40 to 85°C)

HD74ALVCH162270

Item Symbol V

Input voltage V

IH

(V) Min Max Unit Test Conditions

CC

2.3 to 2.7 1.7 — V

2.7 to 3.6 2.0 —

V

IL

2.3 to 2.7 — 0.7

2.7 to 3.6 — 0.8

Output voltage V

OH

2.3 to 3.6 VCC–0.2 — V IOH = –100 µA

2.3 1.9 — IOH = –4 mA, VIH = 1.7 V

2.3 1.7 — IOH = –6 mA, VIH = 1.7 V

3.0 2.4 — IOH = –6 mA, VIH = 2.0 V

2.7 2.0 — IOH = –8 mA, VIH = 2.0 V

3.0 2.0 — IOH = –12 mA, VIH = 2.0 V

V

OL

2.3 to 3.6 — 0.2 IOL = 100 µA

2.3 — 0.4 IOL = 4 mA, VIL = 0.7 V

2.3 — 0.55 IOL = 6 mA, VIL = 0.7 V

3.0 — 0.55 IOL = 6 mA, VIL = 0.8 V

2.7 — 0.6 IOL = 8 mA, VIL = 0.8 V

3.0 — 0.8 IOL = 12 mA, VIL = 0.8 V

Input current I

IN

I

IN (hold)

3.6 — ±5 µAVIN = VCC or GND

2.3 45 — VIN = 0.7 V

2.3 –45 — VIN = 1.7 V

3.0 75 — VIN = 0.8 V

3.0 –75 — VIN = 2.0 V

*1

or GND

CC

Off state output current I
Quiescent supply current I

∆I

3.6 — ±500 VIN = 0 to 3.6 V

OZ

CC

CC

3.6 — ±10 µAV

3.6 — 40 µAVIN = VCC or GND

3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6) V,

= VCC or GND

OUT

other inputs at V

Note: 1. This is the bus hold maximum dynamic current required to switch the input from one state to

another.

7

HD74ALVCH162270

Switching Characteristics (Ta = –40 to 85°C)

Item Symbol VCC (V) Min Typ Max Unit FROM

(Input)

Maximum clock frequency f

max

2.5±0.2 135 — — MHz

2.7 135 — —

3.3±0.3 135 — —

Propagation delay time t

PLH

t

PHL

2.5±0.2 2.5 — 6.9 ns CLK B

2.7 — — 6.4

3.3±0.3 1.7 — 5.6

2.5±0.2 2.2 — 6.4 CLK A

2.7 — — 6.0

3.3±0.3 1.6 — 5.2

2.5±0.2 2.4 — 7.2 SEL A

2.7 — — 7.0

3.3±0.3 1.6 — 6.0

Output enable time t

ZH

t

ZL

2.5±0.2 2.1 — 7.9 ns CLK A or B

2.7 — — 7.4

3.3±0.3 1.6 — 6.5

Output disable time t

HZ

t

LZ

2.5±0.2 3.0 — 7.8 ns CLK A or B

2.7 — — 7.1

3.3±0.3 1.7 — 6.2
Input capacitance C
Output capacitance C

IN

IN / O

3.3 — 3.5 — pF Control inputs

3.3 — 9.0 — pF A or B ports

TO
(Output)

8

HD74ALVCH162270

Switching Characteristics (Ta = –40 to 85°C) (cont)

Item Symbol VCC (V) Min Typ Max Unit FROM (Input)

Setup time t

Hold time t

Pulse width t

su

h

w

2.5±0.2 4.1 — — ns A data before CLK↑

2.7 3.8 — —

3.3±0.3 3.1 — —

2.5±0.2 0.9 — — B data before CLK↑

2.7 1.2 — —

3.3±0.3 0.9 — —

2.5±0.2 3.5 — — CLKENA1 or

2.7 3.2 — — CLKENA2 before CLK↑

3.3±0.3 2.7 — —

2.5±0.2 3.4 — — CLKEN1B or

2.7 3.0 — — CLKEN2B before CLK↑

3.3±0.3 2.6 — —

2.5±0.2 4.4 — — OE before CLK↑

2.7 3.9 — —

3.3±0.3 3.2 — —

2.5±0.2 0 — — ns A data after CLK↑

2.7 0 — —

3.3±0.3 0.2 — —

2.5±0.2 1.4 — — B data after CLK↑

2.7 1.0 — —

3.3±0.3 1.7 — —

2.5±0.2 0 — — CLKENA1 or

2.7 0.1 — — CLKENA2 after CLK↑

3.3±0.3 0.3 — —

2.5±0.2 0 — — CLKEN1B or

2.7 0 — — CLKEN2B after CLK↑

3.3±0.3 0.6 — —

2.5±0.2 0 — — OE after CLK↑

2.7 0 — —

3.3±0.3 0.1 — —

2.5±0.2 3.3 — — ns CLK “H” or “L”

2.7 3.3 — —

3.3±0.3 3.3 — —

9

HD74ALVCH162270

• Test Circuit

500 Ω

See under table

S1

OPEN

*1

L

500 ΩC = 50 pF

GND

Load Circuit for Outputs

Symbol

t / t

PLH PHL

t / t / t

su h w

t / t

ZH HZ

t / t

ZL LZ

Note: 1. C includes probe and jig capacitance.

L

Vcc=2.5±0.2V

OPEN

GND

4.6 V 6.0 V

Vcc=2.7V,

3.3±0.3V

OPEN

GND

10

HD74ALVCH162270

• Waveforms – 1

Input

Output

• Waveforms – 2

Timing Input

Data Input

Input

10 %

90 %

t

t

f

V

IH

V

ref

10 %

t

PHL

V

ref

r

90 %

V

ref

GND

V

OH

V

OL

V

IH

GND

t

h

V

IH

V

ref

t

r

90 %

V

ref

t

PLH

V

ref

10 %

t

su

V

ref

GND

t

w

V

IH

V

ref

V

ref

GND

11

HD74ALVCH162270

• Waveforms – 3

t

f

Output
Control

Waveform - A

Waveform - B

90 %

V

ref

10 % 10 %

t

ZL

V

ref

t

ZH

V

ref

Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

t

r

90 %

V

ref

t

LZ

V + 0.3 V

OL

t

HZ

V – 0.3 V

OH

IH

ref
OH1
OL1

Vcc=2.5±0.2V

2.3 V 2.7 V

1.2 V 1.5 V

2.3 V 3.0 V
GND

TEST

V

V
V
V

V

GND

≈V

V
V

≈V

Vcc=2.7V,

3.3±0.3V

GND

IH

OH1

OL

OH

OL1

12

Package Dimensions

14.00

+0.3
–0.1

HD74ALVCH162270

Unit : mm

2956

+0.3

–0.1

6.10

128

+0.1

0.20

–0.05

0.50

0.08

M

0.40 Max

0.10

0.05 Min

1.20 max

8.10 ± 0.3

0.15 ± 0.05

JEDEC code

Hitachi code

EIAJ code

10° Max

0.50 ± 0.1

TTP-56D

—
—

13

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