Datasheet HD74ALVCH162244 Datasheet (HIT)

HD74ALVCH162244

16-bit Buffers / Drivers with 3-state Outputs

ADE-205-173A (Z)

Preliminary

2nd. Edition

January 1998

Description

The HD74ALVCH162244 is designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus oriented receivers and transmitters. The device can be used
as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical
active-low output-enable (OE) inputs.

To ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and

undershoot.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±12 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.

HD74ALVCH162244

Function Table

Inputs Output Y
OE A

LHH
LLL
HXZ

H : High level
L : Low level
X : Immaterial
Z : High impedance

2

Pin Arrangement

1OE

1Y1
1Y2

GND

1Y3
1Y4

V

CC

2Y1
2Y2

GND

2Y3
2Y4

3Y1
3Y2

GND

3Y3
3Y4
V

CC

4Y1
4Y2

GND

4Y3
4Y4

4OE

10
11

12
13
14
15
16
17
18

19

20
21
22
23
24

HD74ALVCH162244

2OE

1
2

3
4
5

6
7

8

9

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1A1
1A2
GND
1A3
1A4

V

CC

2A1
2A2

GND
2A3

2A4
3A1

3A2
GND
3A3

3A4
V

CC

4A1
4A2

GND
4A3

4A4
3OE

(Top view)

3

HD74ALVCH162244

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage
Output voltage

*1

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation

at Ta = 55°C (in still air)

*3

CC

V

I

V

O

IK

OK

O

GND

P

T

Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100 mA

0.85 W TSSOP

CC

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage V
Input voltage V
Output voltage V
High level output current I

Low level output current I

CC

I

O

OH

OL

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

2.3 3.6 V
0VCCV
0VCCV
—–6mAV
—–8 V

= 2.3 V

CC

= 2.7 V

CC

— –12 VCC = 3.0 V
— 6 mA VCC = 2.3 V
—8 V
—12 V

= 2.7 V

CC

= 3.0 V

CC

4

Logic Diagram

HD74ALVCH162244

1OE

1A1

1A2

1A3

1A4

3OE

3A1

3A2

3A3

47

46

44

43

25

36

35

33

1

2

1Y1

3

1Y2

5

1Y3

6

1Y4

13

3Y1

14

3Y2

16

3Y3

2OE

2A1

2A2

2A3

2A4

4OE

4A1

4A2

4A3

48

41

40

38

37

24

30

29

27

11

12

19

20

22

8

2Y1

9

2Y2

2Y3

2Y4

4Y1

4Y2

4Y3

3A4

32

17

3Y4

4A4

26

23

4Y4

5

HD74ALVCH162244

Electrical Characteristics (Ta = –40 to 85°C)

Item Symbol V

Input voltage V

IH

(V) Min Max Unit Test Conditions

CC

2.3 to 2.7 1.7 — V

2.7 to 3.6 2.0 —

V

IL

2.3 to 2.7 — 0.7

2.7 to 3.6 — 0.8

Output voltage V

OH

2.3 to 3.6 VCC–0.2 — V IOH = –100 µA

2.3 1.9 — IOH = –4 mA, VIH = 1.7 V

2.3 1.7 — IOH = –6 mA, VIH = 1.7 V

3.0 2.4 — IOH = –6 mA, VIH = 2.0 V

2.7 2.0 — IOH = –8 mA, VIH = 2.0 V

3.0 2.0 — IOH = –12 mA, VIH = 2.0 V

V

OL

2.3 to 3.6 — 0.2 IOL = 100 µA

2.3 — 0.4 IOL = 4 mA, VIL = 0.7 V

2.3 — 0.55 IOL = 6 mA, VIL = 0.7 V

3.0 — 0.55 IOL = 6 mA, VIL = 0.8 V

2.7 — 0.6 IOL = 8 mA, VIL = 0.8 V

3.0 — 0.8 IOL = 12 mA, VIL = 0.8 V

Input current I

IN

I

IN (hold)

3.6 — ±5 µAVIN = VCC or GND

2.3 45 — VIN = 0.7 V

2.3 –45 — VIN = 1.7 V

3.0 75 — VIN = 0.8 V

3.0 –75 — VIN = 2.0 V

*1

or GND

CC

Off state output current I
Quiescent supply current I

∆I

3.6 — ±500 VIN = 0 to 3.6 V

OZ

CC

CC

3.6 — ±10 µAV

3.6 — 40 µAVIN = VCC or GND

3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6) V,

= VCC or GND

OUT

other inputs at V

Notes: 1. This is the bus hold maximum dynamic current required to switch the input from one state to

another.

6

Switching Characteristics (Ta = –40 to 85°C)

HD74ALVCH162244

Item Symbol VCC (V) Min Typ Max Unit FROM

(Input)

Propagation delay time t

PLH

t

PHL

2.5±0.2 1.0 — 4.9 ns A Y

2.7 — — 4.7

3.3±0.3 1.0 — 4.2

Output enable time t

ZH

t

ZL

2.5±0.2 1.0 — 6.8 ns OE Y

2.7 — — 6.7

3.3±0.3 1.0 — 5.6

Output disable time t

HZ

t

LZ

2.5±0.2 1.0 — 6.3 ns OE Y

2.7 — — 5.7

3.3±0.3 1.0 — 5.5

Input capacitance C

IN

3.3 — 3.0 — pF Control inputs

3.3 — 6.0 — Data inputs

Output capacitance C

O

3.3 — 7.0 — pF Outputs

Test Circuit

See under table

500 Ω

S1

OPEN

TO
(Output)

*1

L

500 ΩC = 50 pF

Load Circuit for Outputs

Symbol

t / t

PLH PHL

t / t

ZH HZ

t / t

ZL LZ

Vcc=2.5±0.2V

2 × V 6.0 V

Note: 1. CL includes probe and jig capacitance.

Vcc=2.7V,

3.3±0.3V

OPEN OPEN

GND

CC

GND

GND

7

HD74ALVCH162244

Waveforms – 1

Input

Output

Waveforms – 2

Output
Control

Waveform - A

Waveform - B

10 %

90 %

t

rf

90 %

V

ref

t

90 %

V

ref

10 %

t

PLH

V

ref

t

f

t

r

t

PHL

90 %

V

ref

V

ref

10 % 10 %

t

ZL

V

ref

t

ZH

V

ref

t

LZ

t

HZ

V

IH

GND

V

OH

V

ref

V

OL

V

IH

GND

≈V

OH1

V

ref1

V

ref2

V
V

≈V

OL

OH

OL1

CC

Vcc=2.7V,

3.3±0.3V

V +0.3 V

OL

V –0.3 V

OH

TEST

V

IH

V

ref

V

ref1

V

ref2

V

OH1

V

OL1

Vcc=2.5±0.2V

V

CC

1/2 V 1.5 V

V +0.15 V

OL

V –0.15 V

OH

V

CC

GND

Notes: 1. All input pulses are supplied by generators having the following characteristics :

PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)

2. Waveform – A is for an output with internal conditions such that the output is low except

when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high except

when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

8

2.7 V

3.0 V
GND

Package Dimensions

12.50

+0.3
–0.1

HD74ALVCH162244

Unit : mm

2548

+0.3

–0.1

6.10

124

+0.1

0.20

–0.05

0.50

0.08

M

0.65 Max

0.10

0.05 Min

1.20 max

8.10 ± 0.3

0.15 ± 0.05

Hitachi code

EIAJ code

JEDEC code

10° Max

0.50 ± 0.1

TTP-48DC

—
—

9

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