Datasheet HCS20MS Datasheet (Intersil Corporation)

September 1995

HCS20MS

Radiation Hardened

Dual 4-Input NAND Gate

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

2

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

/mg

-9

Errors/Bit-Day

(Typ)

• Dose Rate Survivability: >1 x 10

10

• Dose Rate Upset >10

RAD (Si)/s 20ns Pulse

12

RAD (Si)/s

• Latch-Up Free Under Any Conditions

o

• Military Temperature Range: -55

C to +125oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCS20MS is a Radiation Hardened Dual 4-Input
NAND Gate. A low on any input forces the output to a High state.

The HCS20MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.

Pinouts

14 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-183S CDIP2-T14, LEAD FINISH C

TOP VIEW

A1

1
2

B1

3

NC

4

C1

5

D1

6

Y1

7

GND

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C

TOP VIEW

1A1

B1

NC

C1
D1
Y1

GND

2
3
4
5
6
7

14

VCC

13

D2

12

C2

11

NC

10

B2

9

A2

8

Y2

14
13

12
11
10

9
8

VCC
D2
C2
NC
B2
A2
Y2

The HCS20MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).

Ordering Information

PART

NUMBER

HCS20DMSR -55oC to +125oC Intersil Class

HCS20KMSR -55oC to +125oC Intersil Class

HCS20D/
Sample

HCS20K/
Sample

HCS20HMSR +25oC Die Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

TEMPERATURE

RANGE

+25oC Sample 14 Lead SBDIP

+25oC Sample 14 Lead Ceramic

SCREENING

LEVEL PACKAGE

14 Lead SBDIP

S Equivalent

14 Lead Ceramic

S Equivalent

Flatpack

Flatpack

43

Functional Diagram

(1, 9)

An
Bn

(2, 10)

(4, 12)

Cn
Dn

(5, 13)

An Bn Cn Dn Yn

LXXX H
XLXX H
XXLX H
XXXL H

HHHH L

NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care

TRUTH TABLE

INPUTS OUTPUTS

Spec Number

518761

File Number 3050.1

(6, 8)

Yn

Specifications HCS20MS

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC

Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..

Operating Conditions

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at 4.5V VCC (TR, TF). . . . . . .100ns Max

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W

Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.6mW/oC

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC

Input High Voltage (VIH). . . . . . . . . . . . . . . . . . 70% of VCC to VCC

JA

θ

JC

(NOTE 1)

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V,

Output Current
(Sink)

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V, VIH = 3.15V,

Output Voltage High VOH VCC = 4.5V, VIH = 3.15V,

Input Leakage
Current

IOL VCC = 4.5V, VIH = 4.5V,

IOH VCC = 4.5V, VIH = 4.5V,

IIN VCC = 5.5V, VIN = VCC or

CONDITIONS

VIN = VCC or GND

VOUT = 0.4V, VIL = 0V

VOUT = VCC -0.4V,
VIL = 0V

IOL = 50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V

IOH = -50µA, VIL = 1.35V

VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V

GND

GROUP

A SUB-

GROUPS TEMPERATURE

1 +25oC-10µA

2, 3 +125oC, -55oC - 200 µA

1 +25oC 4.8 - mA

2, 3 +125oC, -55oC 4.0 - mA

1 +25oC -4.8 - mA

2, 3 +125oC, -55oC -4.0 - mA

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC - 0.1 V

1, 2, 3 +25oC, +125oC, -55oC VCC

1, 2, 3 +25oC, +125oC, -55oC VCC

1 +25oC-±0.5 µA

2, 3 +125oC, -55oC-±5.0 µA

LIMITS

-V

-0.1

-V

-0.1

UNITSMIN MAX

Noise Immunity
Functional Test

NOTES:

1. All voltages reference to device GND.

2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

FN VCC = 4.5V,

VIH = 0.70(VCC), (Note 2)
VIL = 0.30(VCC)

7, 8A, 8B +25oC, +125oC, -55oC---

44

Spec Number 518761

Specifications HCS20MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

(NOTES 1, 2)

PARAMETER SYMBOL

Data to Output TPHL VCC = 4.5V 9 +25oC 2 18 ns

Data to Output TPLH VCC = 4.5V 9 +25oC 2 20 ns

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Capacitance Power
Dissipation

Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF

CPD VCC = 5.0V, f = 1MHz 1 +25oC - 38 pF

CONDITIONS

A SUB-

GROUPS TEMPERATURE

10, 11 +125oC, -55oC 2 20 ns

10, 11 +125oC, -55oC 2 22 ns

1 +125oC, -55oC - 45 pF

LIMITS

LIMITS

UNITSMIN MAX

UNITSMIN MAX

1 +125oC, -55oC - 10 pF

Output Transition
Time

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

PARAMETER SYMBOL

Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.2 mA

Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND,

Output Current
(Source)

Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC),

TTHL
TTLH

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

VCC = 4.5V 1 +25oC - 15 ns

1 +125oC, -55oC - 22 ns

(NOTES 1, 2)

CONDITIONS TEMPERATURE

+25oC 4.0 - mA

VOUT = 0.4V

IOH VCC = 4.5V, VIN = VCC or GND,

VOUT = VCC -0.4V

VIL = 0.30(VCC), IOL = 50µA

+25oC -4.0 - mA

+25oC - 0.1 V

200K RAD

LIMITS

UNITSMIN MAX

Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = 0.70(VCC),

VIL = 0.30(VCC), IOH = -50µA

Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC-±5 µA

+25oC VCC

-0.1

-V

Spec Number 518761

45

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL

Specifications HCS20MS

(NOTES 1, 2)

CONDITIONS TEMPERATURE

200K RAD

LIMITS

UNITSMIN MAX

Noise Immunity
Functional Test

Input to Yn TPHL VCC = 4.5V +25oC 2 20 ns

NOTES:

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

FN VCC = 4.5V, VIH = 0.70(VCC),

VIL = 0.30(VCC), (Note 3)

TPLH VCC = 4.5V +25oC 2 22 ns

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)

GROUP B

PARAMETER

ICC 5 3µA

IOL/IOH 5 -15% of 0 Hour

TABLE 6. APPLICABLE SUBGROUPS

SUBGROUP DELTA LIMIT

+25oC 4.0 0.5 V

Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

PDA 100%/5004 1, 7, 9, Deltas

Interim Test III (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H

PDA 100%/5004 1, 7, 9, Deltas

Final Test 100%/5004 2, 3, 8A, 8B, 10, 11

Group A (Note 1) Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample/5005 1, 7, 9

Group D Sample/5005 1, 7, 9

NOTE: 1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.

46

Spec Number 518761

Specifications HCS20MS

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE

GROUPS METHOD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1)

NOTE:

1. Except FN test which will be performed 100% Go/No-Go.

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

PRE RAD POST RAD PRE RAD POST RAD

OSCILLATOR

OPEN GROUND 1/2 VCC = 3V± 0.5V VCC = 6V ± 0.5V

STATIC BURN-IN I TEST CONDITIONS (Note 1)

3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12,

13

STATIC BURN-IN II TEST CONNECTIONS (Note 1)

3, 6, 8, 11 7 - 1, 2, 4, 5, 9, 10, 12,

DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)

- 7 3, 6, 8, 12 14 1, 2, 4, 5, 9, 10,

NOTES:

1. Each pin except VCC and GND will have a resistor of 10KΩ± 5% for static burn-in.

2. Each pin except VCC and GND will have a resistor of 1KΩ± 5% for dynamic burn-in.

TABLE 9. IRRADIATION TEST CONNECTIONS

OPEN GROUND VCC = 5V ± 0.5V

3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14

NOTE: Each pin except VCC and GND will have a resistor of 47KΩ± 5% for irradiation testing.

Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.

-14--

13, 14

50kHz 25kHz

--

-

12, 13

47

Spec Number 518761

HCS20MS

Intersil Space Level Product Flow - ‘MS’

Wafer Lot Acceptance (All Lots) Method 5007

(Includes SEM)

GAMMA Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,

10 Cycles
100% Constant Acceleration, Method 2001, Condition per

Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,

NOTES:

1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.

2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the

3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.

4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.

5. Data Package Contents:

o

C min., Method 1015

+125

failures from subgroup 7.

• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).

• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.

• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.

• X-Ray report and film. Includes penetrometer measurements.

• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).

• Lot Serial Number Sheet (Good units serial number and lot number).

• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.

• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.

100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,

o

C min., Method 1015

+125
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125

o

Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)

C or

48

Spec Number 518761

HCS20MS

AC Timing Diagrams

VIH

VS

VIL

VOH

VOL

VOH

VOL

PARAMETER HCS UNITS

VCC 4.50 V

VIH 4.50 V

VS 2.25 V

VIL 0 V

INPUT

TPLH

VS

TTLH

20%

OUTPUT

80%

OUTPUT

AC VOLTAGE LEVELS

TPHL

80%

20%

TTHL

AC Load Circuit

DUT TEST

CL

CL = 50pF
RL = 500Ω

POINT

RL

GND 0 V

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Spec Number 518761

49

Die Characteristics

DIE DIMENSIONS:

87 x 88 mils

2.20mm x 2.24mm

METALLIZATION:

Type: AlSi
Metal Thickness: 11k

Å ± 1kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 13kÅ ± 2.6kÅ

WORST CASE CURRENT DENSITY:

<2.0 x 10

5

A/cm

2

BOND PAD SIZE:

100µm x 100µm
4 x 4 mils

Metallization Mask Layout

HCS20MS

HCS20MS

A1 VCC D2
(1) (14) (13)

B1 (2)

NC (3)

C1 (4)

D1 (5)

(12) C2

(11) NC

(10) B2

(9) A2

(6) (7) (8)
Y1 GND Y2

50

Spec Number 518761