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HCS138T
Data Sheet July 1999 File Number
Radiation Hardened Inverting 3-to-8 Line
Decoder/Demultiplexer
Intersil‘s Satellite Applications FlowTM (SAF) devices are
fully tested and guaranteed to 100kRAD total dose. These
QML Class T devices are processed to a standard flow
intended to meet the cost and shorter lead-time needs of
large volume satellite manufacturers, while maintaining a
high level of reliability.
The Intersil HCS138T is a Radiation Hardened 3-to-8 Line
Decoder/Demultiplexer. The outputs are active in the low
state. Two active low and one active high enables (
E1, E2,
E3) are provided. If the device is enabled, the binary inputs
(A0, A1, A2) determine which one of the eight normally high
outputs will go to a low logic level.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCS138T are
contained inSMD 5962-95727. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/ne wsafc lasst.asp
Intersil‘s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/spacedefense/ne wsafc lasst.asp
Ordering Information
TEMP.
ORDERING
NUMBER
PART
NUMBER
RANGE
(oC)
4614.1
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
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- Gamma Dose (γ) 1 x 10
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
- Single Event Upset (SEU) Immunity < 2 x 10
2
/mg
-9
Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened SOS CMOS
• Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
-V
= 0.3 VCC Max
IL
-V
= 0.7 VCC Min
IH
• Input Current Levels Ii ≤ 5mA at V
OL
, V
OH
Pinouts
HCS138DTR (SBDIP), CDIP2-T16
TOP VIEW
V
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
16
CC
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
5962R9572701TEC HCS138DTR -55 to 125
5962R9572701TXC HCS138KTR -55 to 125
NOTE:
Minimumorderquantityfor-T is 150 units through
distribution, or 450 units direct.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
HCS138KTR (FLATPACK), CDFP4-F16
TOP VIEW
A0
A1
A2
E1
E2
E3
Y7
GND
www.intersil.com or 407-727-9207
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
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| Copyright © Intersil Corporation 1999
V
Y0
Y1
Y2
Y3
Y4
Y5
Y6
CC
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Functional Diagram
INPUTS
HCS138T
1
A0
2
A1
3
A2
4
E1
5
E2
6
E3
TRUTH TABLE
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
OUTPUTSENABLE
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
XHXXXXHHHHHHHH
HL LLL LLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HL LLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL
H = High Level, L = Low Level, X = Don’t Care
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Die Characteristics
HCS138T
DIE DIMENSIONS:
(2159µm x 2565µm x 533µm ±51µm)
85 x 101 x 21mils ±2mil
METALLIZATION:
Type: Al Si
Thickness: 11.0k
Å ±1kÅ
SUBSTRATE POTENTIAL:
Unbiased Silicon on Sapphire
BACKSIDE FINISH:
Sapphire
Metallization Mask Layout
A2 (3)
HCS138T
A1 A0 V
(2) (1) (16)
CC
PASSIVATION:
Type: Silox (S
Thickness: 13.0k
)
iO2
Å ±2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
264
PROCESS:
CMOS SOS
Y0
(15)
Y1
(14)
NC
NC
Y2
E1 (4)
E2 (5)
E3 (6)
NC
(7)
Y7
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The
mask series for the HCS138 is TA14361A.
(8) (9) (10)
GND
Y6 Y5
(13)
(12)
(11)
NC
Y3
Y4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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