Datasheet HB52F649E1-75B Datasheet (ELPID)

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HB52F649E1-75B

512 MB Registered SDRAM DIMM

64-Mword × 72-bit, 133 MHz Memory Bus, 1-Bank Module

(18 pcs of 64 M × 4 Components)

PC133SDRAM

E0021H20 (Ver. 2.0)

Aug. 20, 2001 (K)

Description

The HB52F649E1 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52F649E1 is a 64M × 72 × 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52F649E1 is 168-pin socket type package (dual lead out). Therefore, the HB52F649E1 makes high density mounting possible without surface mount technology. The HB52F649E1 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features

• Fully compatible with : JEDEC standard outline 8-byte DIMM

• 168-pin socket type package (dual lead out)  Outline: 133.35 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)  Lead pitch: 1.27 mm

• 3.3 V power supply

• Clock frequency: 133 MHz (max)

• LVTTL interface

• Data bus width: × 72 ECC

• Single pulsed RAS

• 4 Banks can operates simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length: 1/2/4/8

• 2 variations of burst sequence  Sequential  Interleave

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

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HB52F649E1-75B

• Programmable CE latency : 4 (133 MHz)

: 3 (100 MHz)

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64 ms

• 2 variations of refresh  Auto refresh  Self refresh

Ordering Information

Type No. Frequency CE latency Package Contact pad

HB52F649E1-75B* Note: 1. 100 MHz operation at CE latency = 3.

Pin Arrangement

133 MHz 4 168-pin dual lead out socket type Gold

1 pin 10 pin11 pin 40 pin 41 pin 84 pin

85 pin 94 pin 95 pin 124 pin 125 pin 168 pin

Data Sheet E0021H10

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HB52F649E1-75B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

43 V

2 DQ0 44 NC 86 DQ32 128 CKE0 3 DQ1 45 S2 87 DQ33 129 NC 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6VCC48 NC 90 V 7 DQ4 49 V

8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 V

54 V

13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 V 18 V

60 DQ20 102 V

19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 CB0 63 NC 105 CB4 147 REGE 22 CB1 64 V 23 V

65 DQ21 107 V

24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 V

68 V

27 W 69 DQ24 111 CE 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 S0 72 DQ27 114 NC 156 DQ59 31 NC 73 V 32 V

74 DQ28 116 V

33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63

85 V

127 V

132 NC

91 DQ36 133 V

96 V

138 V

101 DQ45 143 V

144 DQ52

106 CB5 148 V

149 DQ53

152 V

110 V

115 RE 157 V

158 DQ60

Data Sheet E0021H10

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HB52F649E1-75B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 36 A6 78 V

37 A8 79 CK2 121 A9 163 CK3 38 A10 (AP) 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40 V 41 V

42 CK0 84 V

82 SDA 124 V 83 SCL 125 CK1 167 SA2

Pin Description

Pin name Function

A0 to A12 Address input

BA0/BA1 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output)

S0, S2 Chip select input RE Row enable (RAS) input CE Column enable (CAS) input W Write enable input

DQMB0 to DQMB7 Byte data mask CK0 to CK3 Clock input CKE0 Clock enable input WP Write protect for serial PD

REGE* SDA Data input/output for serial PD SCL Clock input for serial PD SA0 to SA2 Serial address input V

NC No connection Note: 1. REGE ≥ VIH: Register mode.

REGE ≤ V

: Buffer mode.

Primary positive power supply Ground

120 A7 162 V

166 SA1

126 A12 168 V

 Row address A0 to A12  Column address A0 to A9, A11

Data Sheet E0021H10

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HB52F649E1-75B

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0 Number of bytes used by

module manufacturer 1 Total SPD memory size 0000100008 256 byte 2 Memory type 0000010004 SDRAM 3 Number of row addresses bits 000011010D 13 4 Number of column addresses

bits 5 Number of banks 0000000101 1 6 Module data width 0100100048 72 bit 7 Module data width (continued) 0000000000 0 (+) 8 Module interface signal levels 0000000101 LVTTL 9 SDRAM cycle time

(highest CE latency)

7.5 ns

10 SDRAM access from Clock

(highest CE latency)

5.4 ns 11 Module configuration type 0000001002 ECC 12 Refresh rate/type 1000001082 Normal

13 SDRAM width 0000010004 64M × 4 14 Error checking SDRAM width 0000010004 × 4 15 SDRAM device attributes:

minimum clock delay for back-toback random column addresses

16 SDRAM device attributes:

Burst lengths supported

17 SDRAM device attributes:

number of banks on SDRAM device

18 SDRAM device attributes:

CE latency

19 SDRAM device attributes:

S latency

20 SDRAM device attributes:

W latency

21 SDRAM device attributes 000111111F Registered

1000000080 128

000010110B 11

0111010175 CL = 3

0101010054 *

0000000101 1 CLK

000011110F 1, 2, 4, 8

0000010004 4

0000011006 2/3

0000000101 0

(7.8125 µs) Self refresh

Data Sheet E0021H10

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HB52F649E1-75B

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

22 SDRAM device attributes:

000011100E V

General

23 SDRAM cycle time

10100000A0 CL = 2 (2nd highest CE latency) 10 ns

24 SDRAM access from Clock

0110000060 (2nd highest CE latency) 6 ns

25 SDRAM cycle time

0000000000 (3rd highest CE latency) Undefined

26 SDRAM access from Clock (3rd

0000000000 highest CE latency) Undefined

27 Minimum row precharge time 0001010014 20 ns 28 Row active to row active min 000011110F 15 ns 29 RE to CE delay min 0001010014 20 ns 30 Minimum RE pulse width 001011012D 45 ns 31 Density of each bank on module 1000000080 1 bank

32 Address and command signal

0001010115 1.5 ns* input setup time

33 Address and command signal

0000100008 0.8 ns* input hold time

34 Data signal input setup time 0001010115 1.5 ns* 35 Data signal input hold time 0000100008 0.8 ns* 36 to 61 Superset information 0000000000 Future use 62 SPD data revision code 0000001002 JEDEC2 63 Checksum for bytes 0 to 62 10101100AC 172 64 Manufacturer’s JEDEC ID code 0000011107 HITACHI 65 to 71 Manufacturer’s JEDEC ID code 0000000000 72 Manufacturing location ЧЧЧЧЧЧЧЧЧ× *2 (ASCII-

73 Manufacturer’s part number 0100100048 H 74 Manufacturer’s part number 0100001042 B 75 Manufacturer’s part number 0011010135 5 76 Manufacturer’s part number 0011001032 2

± 10%

512M byte

8bit code)

Data Sheet E0021H10

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HB52F649E1-75B

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

77 Manufacturer’s part number 0100011046 F 78 Manufacturer’s part number 0011011036 6 79 Manufacturer’s part 0011010034 4 80 Manufacturer’s part number 0011100139 9 81 Manufacturer’s part number 0100010145 E 82 Manufacturer’s part number 0011000131 1 83 Manufacturer’s part number 001011012D — 84 Manufacturer’s part number 0011011137 7 85 Manufacturer’s part number 0011010135 5 86 Manufacturer’s part number 0100001042 B 87 Manufacturer’s part number 0010000020 (Space) 88 Manufacturer’s part number 0010000020 (Space) 89 Manufacturer’s part number 0010000020 (Space) 90 Manufacturer’s part number 0010000020 (Space) 91 Revision code 0011000030 Initial 92 Revision code 0010000020 (Space) 93 Manufacturing date ЧЧЧЧЧЧЧЧЧ× Year code

(BCD)

94 Manufacturing date ЧЧЧЧЧЧЧЧЧ× Week code

(BCD) 95 to 98 Assembly serial number * 99 to 125 Manufacturer specific data ————————— * 126 Reserved (Intel specification

frequency)

127 Reserved (Intel specification

CE# latency support)

Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”.

2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.)

3. Bytes 95 through 98 are assembly serial number.

4. All bits of 99 through 125 are not defined (“1” or “0”).

5. These specifications are defined based on component specification, not module.

0110010064

1000011187

Data Sheet E0021H10

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HB52F649E1-75B

Block Diagram

DQMB0 to DQMB7

0.0022 µF × 24 pcs

S0, S2

BA0 to BA1

A0 to A12

RE CE

CKE0

10 kΩ

REGE

PLL CK

CK1 to CK3

CK0

RDQMB0

DQ0 to DQ3

DQ4 to DQ7

RDQMB1

DQ8 to DQ11

DQ12 to DQ15

CB0 to CB3

RDQMB2

DQ16 to DQ19

DQ20 to DQ23

RDQMB3

DQ24 to DQ27

DQ28 to DQ31

R E G

I S T E R

10 Ω

12 pF

10 Ω

12 pF

0.22 µF × 18 pcs

RS0

DQMB

4 10 Ω 10 Ω

10 Ω

RS2

10 Ω

RS0, RS2 RDQMB0 to RDQMB7 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17

RRAS -> RAS: SDRAMs D0 to D17 RCAS -> CAS: SDRAMs D0 to D17

RCKE0 -> CKE: SDRAMs D0 to D17 RW -> WE: SDRAMs D0 to D17

PLL

VCC (D0 to D17, U0)

2.2 µF × 2 pcs

VSS (D0 to D17, U0)

I/O0 to I/O3

DQMB I/O0

to I/O3

DQMB I/O0

to I/O3 DQMB

I/O0 to I/O3

DQMB I/O0

to I/O3

DQMB I/O0

to I/O3 DQMB

I/O0 to I/O3

DQMB I/O0

to I/O3 DQMB

I/O0 to I/O3

RDQMB4

DQ32 to DQ35

DQ36 to DQ39

RDQMB5

DQ40 to DQ43

DQ44 to DQ47

CB4 to CB7

RDQMB6

DQ48 to DQ51

DQ52 to DQ55

RDQMB7

DQ56 to DQ59

DQ60 to DQ63

DQMB

10 Ω

SCL

Notes:

1. The SDA pull-up resistor is required due to the open-drain/open-collector output.

2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve

"high" state.

* D0 to D17: HM5225405

PLL: 2510 Register: 162834 U0: 2-k bit EEPROM

I/O0 to I/O3

DQMB

D10

I/O0 to I/O3

DQMB

D11

I/O0 to I/O3

DQMB

D12

I/O0 to I/O3

DQMB

D13

I/O0 to I/O3

DQMB

D14

I/O0 to I/O3

DQMB

D15

I/O0 to I/O3

DQMB

D16

I/O0 to I/O3

DQMB

D17

I/O0 to I/O3

Serial PD

SCL

SDA

A1 A2

SA0 SA1 SA2

SDA

47 kΩ

Data Sheet E0021H10

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HB52F649E1-75B

Absolute Maximum Ratings

Parameter Symbol Value Unit Note

Voltage on any pin relative to V

Supply voltage relative to V

Short circuit output current Iout 50 mA Power dissipation P

Operating temperature Topr 0 to +55 °C Storage temperature Tstg –50 to +100 °C

Note: 1. Respect to V

DC Operating Conditions (Ta = 0 to +55°C)

Parameter Symbol Min Max Unit Notes

Supply voltage V

Input high voltage V Input low voltage V

Notes: 1. All voltage referred to V

2. The supply voltage with all VCC pins must be on the same level.

3. The supply voltage with all V

4. V

(max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.

5. V

(min) = VSS − 2.0 V for pulse width ≤ 3 ns at VSS.

SS pins must be on the same level.

–0.5 to VCC + 0.5

(≤ 4.6 (max)) –0.5 to +4.6 V 1

18.0 W

3.0 3.6 V 1, 2 00V3

2.0 V

V 1, 4

0 0.8 V 1, 5

Data Sheet E0021H10

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HB52F649E1-75B

DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)

HB52F649E1-75B PC133

CE latency = 4

Parameter Symbol Min Max Min Max Unit Test conditions Notes

Operating current I

Standby current in power

CC1

CC2P

— 2675 — 2675 mA Burst length = 1

— 749 — 749 mA CKE = VIL, tCK = 12 ns 6

down Standby current in power

CC2PS

— 731 — 731 mA CKE = VIL, tCK = ∞ 7 down (input signal stable)

Standby current in non

CC2N

— 1055 — 1055 mA CKE, S = VIH, power down

Active standby current in

CC3P

— 767 — 767 mA CKE = VIL, tCK = 12 ns 1, 2, 6 power down

Active standby current in

CC3N

— 1235 — 1235 mA CKE, S = VIH, non power down

Burst operating current I Refresh current I Self refresh current I

Input leakage current I Output leakage current I

Output high voltage V Output low voltage V

CC4

CC5

CC6

— 3035 — 2405 mA tCK = min, BL = 4 1, 2, 5

— 4655 — 4655 mA tRC = min 3

— 749 — 749 mA VIH ≥ VCC – 0.2 V

–10 10 –10 10 µA 0 ≤ Vin ≤ V

–10 10 –10 10 µA 0 ≤ Vout ≤ V

2.4 — 2.4 — VIOH = –4 mA

— 0.4 — 0.4 V IOL = 4 mA

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the

output open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CK operating current.

7. After power down mode, no CK operating current.

8. After self refresh mode set, self refresh current.

PC100 CE latnecy = 3

= min

= 12 ns

≤ 0.2 V

DQ = disable

1, 2, 3

1, 2, 4

Data Sheet E0021H10

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HB52F649E1-75B

Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)

Parameter Symbol Max Unit Notes

Input capacitance (Address) C Input capacitance (RE, CE, W)C Input capacitance (CKE) C Input capacitance (S)C Input capacitance (CK) C Input capacitance (DQMB) C Input/Output capacitance (DQ) C

I/O1

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.

3. DQMB = V

to disable Data-out.

4. This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)

PC100

Parameter Symbol

System clock cycle time t CK high pulse width t CK low pulse width t Access time from CK t Data-out hold time t CK to Data-out low impedance t CK to Data-out high impedance t Data-in setup time t Data in hold time t Address setup time t Address hold time t CKE setup time t CKE setup time for power down exit t CKE hold time t

CKH

CKL

CES

CESP

CEH

Symbol Min Max Min Max Unit Notes

Tclk 7.5 — 10 — ns 1 Tch 3.4 — 4 — ns 1 Tcl 3.4 — 4 — ns 1 Tac — 6.3 — 6.9 ns 1, 2 Toh 1.8 — 2.1 — ns 1, 2

Tsi 2.4 — 2.9 — ns 1 Thi 1.7 — 1.9 — ns 1 Tsi 1.9 — 2.6 — ns 1 Thi 1.5 — 1.6 — ns 1 Tsi 1.9 — 2.6 — ns 1, 5 Tpde 1.9 — 2.6 — ns 1 Thi 1.5 — 1.6 — ns 1

23 pF 1, 2, 4 23 pF 1, 2, 4 23 pF 1, 2, 4 15 pF 1, 2, 4 40 pF 1, 2, 4 15 pF 1, 2, 4 15 pF 1, 2, 3, 4

HB52F649E1-75B PC133

CE latency = 4

PC100 CE latency = 3

1.1 — 1.1 — ns 1, 2, 3 — 6.3 — 6.9 ns 1, 4

Data Sheet E0021H10

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HB52F649E1-75B

AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)

HB52F649E1-75B PC133

CE latency = 4

PC100

Parameter Symbol

Command setup time t Command hold time t Ref/Active to Ref/Active command

Symbol Min Max Min Max Unit Notes

Tsi 1.9 — 2.6 — ns 1 Thi 1.5 — 1.6 — ns 1, 5 Trc 67.5 — 70 — ns 1

period Active to precharge command period t Active command to column

RAS

RCD

Tras 45 120000 50 120000 ns 1 Trcd 20 — 20 — ns 1

command (same bank) Precharge to active command period t Write recovery or data-in to

DPL

Trp 20 — 20 — ns 1 Tdpl 7.5 — 10 — ns 1

precharge lead time Active (a) to Active (b) command

RRD

Trrd 15 — 20 — ns 1

period Transition time (rise to fall) t Refresh period t

REF

1515ns — 64 — 64 ms

Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.

2. Access time is measured at 1.5 V. Load condition is C

3. t

(min) defines the time at which the outputs achieves the low impedance state.

4. t

(max) defines the time at which the outputs achieves the high impedance state.

5. t

defines CKE setup time to CK rising edge except power down exit command.

CES

= 50 pF.

PC100 CE latency = 3

Test Conditions

• Input and output timing reference levels: 1.5 V

• Input waveform and output load: See following figures

2.4 V

0.4 V

2.0 V

0.8 V

Data Sheet E0021H10

input

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HB52F649E1-75B

Relationship Between Frequency and Minimum Latency

HB52F649E1-75B

Parameter 133 100

Frequency (MHz)

tCK (ns) Symbol

Active command to column command (same bank) I Active command to active command (same bank) I

Active command to precharge command (same bank) I Precharge command to active command (same bank) I Write recovery or data-in to precharge command

RCD

RAS

DPL

(same bank) Active command to active command (different bank) I Self refresh exit time I Last data in to active command

RRD

SREX

APW

(Auto precharge, same bank) Self refresh exit to command input I

Precharge command to high impedance I Last data out to active command

SEC

HZP

APR

(auto precharge) (same bank) Last data out to precharge (early precharge) I Column command to column command I Write command to data in latency I DQMB to data in I DQMB to data out I CKE to CK disable I Register set to active command I S to command disable I Power down exit to command input I

Notes: 1. I

RCD

to I

are recommended value.

RRD

CCD

WCD

DID

DOD

CLE

RSA

CDD

PEC

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

CE latency = 4

PC100 Symbol 7.5 10 Notes

321 97= [I

651 321

Tdpl 1 1 1

221 Tsrx 2 2 2 Tdal 4 3 = [I

97= [I

Troh 4 3

–3 –2 Tccd 1 1 Tdwd 1 1 Tdqm 1 1 Tdqz 3 3 Tcke 2 2 Tmrd 1 1

CE latency = 3

+ IRP]

RAS

+ IRP]

DPL

]

Data Sheet E0021H10

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HB52F649E1-75B

Pin Functions

CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK

rising edge.

S0, S2 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.

RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section.

A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is precharged.

BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected.

CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes.

DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z.

Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written.

DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.

VCC (power supply pins): 3.3 V is applied.

VSS (power supply pins): Ground is connected.

Detailed Operation Part

Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).

Data Sheet E0021H10

Page 15

Physical Outline

Front side

3.00 typ

3.00 ± 0.10

1 84

11.43

133.35 ± 0.15

(DATUM -A-)

(63.67)

Component area

(Front)

36.83 54.61

HB52F649E1-75B

Unit: mm

4.00 max

4.00 min

1.27 ± 0.10

Back side

4.00 ±0.10

127.35 ± 0.15

2 – φ 3.00 ± 0.10

Component area

(Back)

(DATUM -A-)

Detail A

1.27

2.50 ± 0.20

1.00 ± 0.05

Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.

Detail B Detail C

R FULL

0.20 ± 0.15

3.125 ± 0.125

168

17.80

(DATUM -A-)

6.35 6.35

2.00 ± 0.10 4.175

1.00

3.125 ± 0.125

R FULL

2.00 ± 0.10

43.18

Data Sheet E0021H10

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HB52F649E1-75B

Cautions

1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc..

7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.

Data Sheet E0021H10