Datasheet GMS87C2120Q, GMS87C2120K, GMS87C2120, GMS81C2112Q, GMS81C2112K Datasheet (HYNIX)

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Page 1

JUNE. 2001 Ver 1.00

HYNIX SEMICONDUCTOR

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112 GMS81C2120

User’s Manual

Page 2

HYNIX SEMICONDUCTOR

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112 GMS81C2120

User’s Manual (Ver. 1.00)

Page 3

Version 1.00 Published by

MCU Application Team



Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory.

HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, HYNIX Semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

Page 4

Page 5

Table of Contents

1. OVERVIEW............................................1

Description .........................................................1

Features ............................... ..............................1

Development Tools ............................................2

Ordering Information



2. BLOCK DIAGRAM.................................3

3. PIN ASSIGNMENT ................................4

4. PACKAGE DIAGRAM............................6

5. PIN FUNCTION......................................8

6. PORT STRUCTURES..........................10

7. ELECTRICAL CHARACTERISTICS....13

Absolute Maximum Ratings .............................13

Recommended Operating Conditions ..............13

A/D Converter Characteristics .........................13

DC Electrical Characteristics for Standard Pins(5V) 14

DC Electrical Characteristics for High-Voltage Pins 15

AC Characteristics ...........................................16

AC Characteristics ...........................................17

Typical Characteristics .....................................18

8. MEMORY ORGANIZATION.................20

Registers ....................... ...................................20

Program Memory ....................... ....... ...............23

Data Memory ...................................................26

Addressing Mode .............................................30

9. I/O PORTS...........................................34

10. BASIC INTERVAL TIMER..................37

11. WATCHDOG TIMER..........................39

12. TIMER/EVENT COUNTER................42

8-bit Timer / Counter Mode ..............................44

16-bit Timer / Counter Mode ............................48

8-bit Compare Output (16-bit) ..........................49

8-bit Capture Mode ......................................... 49

16-bit Capture Mode ....................................... 52

PWM Mode ..................................................... 53

13. ANALOG DIGITAL CONVERTER.....56

14. SERIAL PERIPHERAL INTERFACE.59

Transmission/Recei vi ng Timi ng ........... ........... 61

The method of Serial I/O ................................. 62

The Method to Test Correct Transmission ...... 62

15. BUZZER FUNCTION.........................63

16. INTERRUPTS....................................65

Interrupt Sequence .......................................... 67

Multi Interrupt .................................................. 69

External Interrupt ............................................. 70

17. Power Saving Mode...........................72

Operating Mode .............................................. 73

Stop Mode ....................................................... 74

Wake-up Timer Mode ...................................... 75

Internal RC-Oscillated Watchdog Timer Mode 76

Minimizing Current Consumption .................... 77

18. OSCILLATOR CIRCUIT.....................79

19. RESET...............................................80

External Reset Input ........................................ 80

Watchdog Timer Reset ................................... 80

20. POWER FAIL PROCESSOR.............81

21. OTP PROGRAMMING.......................83

DEVICE CONFIGURATION AREA ...... ...... ..... 83

A. CONTROL REGISTER LIST..................i

B. INSTRUCTION.............. ..... .... ..... ......... iii

Terminology List ................................................iii

Instruction Map ..................................................iv

Instruction Set ....................................................v

C. MASK ORDER SHEET........................xi

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GMS81C2112/GMS81C2120

CMOS Single-Chip 8-Bit Microcontroller

with A/D Converter & VFD Driver

1. OVERVIEW

1.1 Description

The GMS81C2112 and GMS81C2120 are advanced CMOS 8-b it micro contr oller with 12 K/20K bytes of ROM. Thes e are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 12K/20K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, Serial Peripheral Interface, on-chip oscillator and clo ck circuitry. They also come with h igh voltage I/O p ins that can dir ectl y drive a VFD (Vacuum Fluores cent Displ ay). I n addit ion, t he GMS81C21 12 and GMS 81C212 0 suppor t po wer saving modes to reduce power consumption.

Device name ROM Size RAM Size OTP Package

GMS81C2112 12K bytes GMS81C2120 20K bytes GMS87C2120

1.2 Features

• 20K/12K bytes ROM(EPROM)

• 448 Bytes of On-Chip Data RAM (Including STACK Area)

• Minimum Instruction Execution time:

- 1uS at 4MHz (2cycle NOP Instruction)

• One 8-bit Basic Interval Timer

• One 7-bit Watch Dog Timer

• Two 8-bit Timer/Counters

• 10-bit High Speed PWM Output

• One 8-bit Serial Peripheral Interface

• Two External Interrupt Ports

• One Programmable 6-bit Buzzer Driving Port

• 38 I/O Lines

- 34 Programmable I/O pins (Included 21 high-voltage pins Max. 40V)

- Three Input Only pins: 1 high-voltage pin

- One Output Only pin

448 bytes

• 8-Channel 8-bit On-Chip Analog to Digital Converter

• Oscillator:

- Crystal

- Ceramic Resonator

- External R Oscillator

• Low Power Dissipation Modes

- STOP mode

- Wake-up Timer Mode

- Standby Mode

• Operating Voltage: 2.7V ~ 5.5V (at 4.5MHz)

• Operating Frequency: 1MHz ~ 4.5MHz

• Enhanced EMS Improvement Power Fail Processor (Noise Immunity Circuit)Enhanced EMS Improvement Power Fail Processor (Noise Immunity Circuit)

42SDIP, 44MQFP, 40PDIP

• Eight Interrupt Sources

- Two External Sources (INT0, INT1)

- Two Timer/Counter Sources (Timer0, Timer1)

- Four Functional Sources (SPI,ADC,WDT,BIT)

JUNE. 2001 Ver 1.00 1

Page 8

GMS81C2112/GMS81C2120

1.3 Development Tools

The GMS81C21xx are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.

and OTP programmers. There are third diffe rent type program mers such as emulator add-on board type, single type, gang type. For mode detail, Refer to “21. OTP PROGRAMMING” on page 83. Macro assembler operates under the MS-Windows 95/98

Please contact sales part of HynixSemiconductor.

In Circuit

Emulators

Socket Adapter

for OTP

POD

Assembler

OA87C21XX-42SD (42SDIP)

OA87C21XX-44QF (44MQFP)

CHPOD81C21D-42SD (42SDIP) CHPOD81C21D-40PD (40PDIP)

CHOICE-Dr.

HYNIX Macro Assembler

1.4 Ordering Information

Device name ROM Size RAM size Package

Mask version

OTP version

GMS81C2112 K GMS81C2112 Q GMS81C2112 GMS81C2120 K GMS81C2120 Q GMS81C2120

GMS87C2120 K GMS87C2120 Q GMS87C2120

12K bytes 12K bytes 12K bytes 20K bytes 20K bytes 20K bytes

20K bytes OTP 20K bytes OTP 20K bytes OTP

448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes

448 bytes 448 bytes 448 bytes

42SDIP 44MQFP 40PDIP 42SDIP 44MQFP 40PDIP

42SDIP 44MQFP 40PDIP

2 JUNE. 2001 Ver 1.00

Page 9

2. BLOCK DIAGRAM

ADC Power

Supply

AVDDAV

R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0

R20~R27

R30~R34

GMS81C2112/GMS81C2120

Vdisp/RA

PSW

Syst

em controller

System

Clock Controller Timing generator

Cloc k Generator

RESET

OUT

Driver

Buzzer

ALU

8-bit Basic

Interval

Timer

Watchdog

Timer

Power

Supply

X Y

Interrupt Controller

8-bit

Timer/

Counter

Stack Pointer

8-bit serial

Interface

Data Memor y

(448 bytes)

10-bit PWM

R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57

8-bit ADC

Data Table

R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7

Program

Memory

High Voltage Port

JUNE. 2001 Ver 1.00 3

Page 10

GMS81C2112/GMS81C2120

3. PIN ASSIGNMENT

42SDIP

44MQFP

disp

SCLK

SIN

SOUT

PWM1O/T1O

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

RA R53 R54 R55 R56 R57

RESET

XO V

R60 R61 R62 R63 R64 R65 R66 R67

SS SS

DD DD

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16 17 18 19 20 21

SOUT

SIN

SCLK

PWM1O/T1O

GMS81C2112/20

Vdisp

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00

BUZO EC0 INT1 INT0

R57

RESET

AN0

R60

AN1

R61 R62

AN2

R63

AN3

R64

AN4

High Voltage Port

R55

R54

R53RAR34

R33

R32

R31

R02

EC0

R30

R27

R26

R25

R24

R23

R22

R21

R20

R07

R06

R05

R03

R04

BUZO

R56

41403938373635

444342

1 2

3 4

GMS81C2112/20 7 8 9

10 11

1213141516171819202122

DDVDD

R00

AN7

R01

INT0

INT1

R65

AN5

R66

AN6

R67

4 JUNE. 2001 Ver 1.00

Page 11

GMS81C2112/GMS81C2120

40PDIP

disp

SCLK

SIN

SOUT

PWM1O/T1O

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

High Voltage Port

RA R53 R54 R55 R56 R57

RESET

XO V R60 R61 R62 R63 R64 R65 R66 R67 V

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35

GMS81C2112/20

34 33 32 31 30 29 28 27 26 25 24 23 22 21

R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01R00

BUZO EC0 INT1INT0

JUNE. 2001 Ver 1.00 5

Page 12

GMS81C2112/GMS81C2120

4. PACKAGE DIAGRAM

42SDIP

UNIT: INCH

1.470

1.450

0.600 BSC

0.550

0.190 max. min. 0.015

0.530

44MQFP

10.10

13.45

12.95

2.35 max.

.012

0.020

0.016

13.45

12.95

10.10

9.90

0.045

0.035

0.070 BSC 0-15

0.140

0.120

UNIT: MM

9.90

2.10

1.95

0.23

0.13

0.45

0.30

0.80 BSC

SEE DETAIL “A”

0.25

0.10

0-7

1.60 BSC

DETAIL “A”

1.03

0.73

6 JUNE. 2001 Ver 1.00

Page 13

40PDIP

GMS81C2112/GMS81C2120

UNIT: INCH

2.075

2.045

0.200 max. min. 0.015

0.022

0.015

0.065

0.045

0.100BSC

0.140

0.120

0-15

0.600 BSC

0.550

0.530

JUNE. 2001 Ver 1.00 7

Page 14

GMS81C2112/GMS81C2120

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent po wer source as wel l as poss ible, oth er than digital power source.

: ADC circuit ground.

RESET X

: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

RA(V

In addition, RA serves the functions of the V features. V

)

: RA is one-bit high-voltage input only port pin.

disp

is used as a high-voltage i nput power supply

disp

special

pin when selected by the mask option.

Port pin Alternate function

R00~R07

: R0 is an 8-bit hi gh-voltage CMOS bidir ectional

(High-voltage input power supply)

disp

I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features.

Port pin Alternate function

R00 R01 R02 R03

INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output)

R20~R27

: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 writt en to th e Port Direction R eg ister can be used as outputs or inputs.

R30~R34

: R3 is a 5-bit high-voltage CMOS bidirectional I/O port. R3 pins 1 or 0 writt en to th e Port Direction R eg ister can be used as outputs or inputs.

R53~R57

: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features.

Port pin Alternate function

R53 R54 R55 R56

R60~R67

SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output)

: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input.

Port pin Alternate function

R60 R61 R62 R63 R64 R66 R66 R67

AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7)

8 JUNE. 2001 Ver 1.00

Page 15

GMS81C2112/GMS81C2120

PIN NAME In/Out

Function

Basic Alternate

V RA (V

disp

)

- Supply voltage

- Circuit ground

I(I) 1-bit high-voltage Input only port High-voltage input power supply pin RESET I Reset signal input XIN I Oscillation input XOUT O Oscillation output R00 (INT0) I/O (I)

External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) Timer/Counter 0 external input

8-bit high-voltage I/O ports R03 (BUZO) I/O (O) Buzzer driving output R04~R07 I/O R20~R27 I/O 8-bit high-voltage I/O ports R30~R34 I/O 5-bit high-voltage I/O ports R53 (SCLK) I/O (I/O)

Serial clock source R54 (SIN) I/O (I) Serial data input R55 (SOUT) I/O (O) Serial data output

R56 (PWM1O/T1O) I/O (O)

5-bit high-voltage I/O ports

PWM 1 pulse output /Timer/Counter 1 out-

put R57 I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports Analog voltage input

AV AV V V

SS DD SS

- Supply voltage input pin for ADC

- Ground level input pin for ADC

- Supply voltage

- Circuit ground

Table 5-1 GMS81C2120 Port Function Description

JUNE. 2001 Ver 1.00 9

Page 16

GMS81C2112/GMS81C2120

Data Bus

Data Reg.

Direction

Reg.

MUX

Selection

SCLK Output

SCLK Input

Mask

N-MOS Open Drain Select

Option

Pull-up Tr.

Data Bus

Data Reg.

Direction

Reg.

Selection

SIN Input

Mask

N-MOS Open Drain Select

Option

Pull-up Tr.

6. PORT STRUCTURES

R57

Data Reg.

Dir.

Reg.

Data Bus

MUX

R00/INT0, R01/INT1, R02/EC0

Selection

Data Reg.

Dir.

Reg.

Data Bus

VSS

Mask Option

Pull-up Tr.

Mask Option

R53/SCLK

R54/SIN

EX) INT0 Alternate Function

Vdisp

10 JUNE. 2001 Ver 1.00

Page 17

GMS81C2112/GMS81C2120

RESET

OTP :disconnected Main :connected

XOUT

XIN

Stop Mainclk Off

Data Reg.

Dir.

Vdisp

Reg.

Data Bus

MUX

Selection

Data Reg.

Secondary Function

Mask Option

R55/SOUT

SOUT output

Data Reg.

Direction

Reg.

IOSWB

Data Bus

IOSWIN Input

RA/Vdisp

Selection

MUX

N-MOS Open Drain Select

RESET

Pull-up Tr.

Mask Option

XIN, XOUT

Data bus

Vdisp

Mask Option

R03/BUZO

R04~R07, R20~R27, R30~R34

Data Reg.

Mask

Dir.

Reg.

Data Bus

MUX

Option

Vdisp

JUNE. 2001 Ver 1.00 11

Page 18

GMS81C2112/GMS81C2120

R56/PWM1O/T1O

Selection

SOUT output

MUX

Data Reg.

Direction

Reg.

Data Bus

R60~R67/AN0~AN7

Data Reg.

N-MOS Open Drain Select

Pull-up Tr.

Mask Option

Pull-up Tr.

Mask

Option

Direction

Reg.

Data Bus

A/D Converter

Analog Input Mode

A/D Ch. Selection

12 JUNE. 2001 Ver 1.00

Page 19

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

GMS81C2112/GMS81C2120

Supply voltage.............................................-0.3 to +7.0 V

Storage Temperature ....................................-40 to +85 °C

Voltage on Normal voltage pin with respect to Ground (V

..............................................................-0.3 to V

)

+0.3 V

Voltage on High voltage pin with respect to Ground (V

............................................................-45V to V

Maximum current out of V Maximum current into V Maximum current sunk by (I

)

pin..........................150 mA

pin ..............................80 mA

per I/O Pin) ..........20 mA

+0.3 V

7.2 Recommended Operating Conditions

Parameter Symbol Condition

Supply Voltage

Operating Frequency

Operating Temperature

XIN OPR

fXI = 4.5 MHz

VDD = V

Maximum output current sourced by (I

per I/O Pin)

............................. ...... ................................................ 8 mA

Maximum current (ΣI Maximum current (ΣI

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause per manent damage to the d evice. This is a stress ra ting only and functional ope r ati on of the device at any oth er c ond iti ons ab ov e tho se ind ic ated in the oper ati o na l se c ti ons of this s pecificatio n i s no t i mp l ie d . Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Min. Max.

2.7 5.5 V

-40 85

)......................................100 mA

)........................................50 mA

Specifications

14.5MHz

Unit

7.3 A/D Converter Characteristics

(TA=25°C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @

Parameter Symbol Condition

Analog Power Supply Input Voltage Range Analog Input Voltage Range

Current Following Between AV

and

Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time

1. Data in “T yp” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

AVDD

CA N

DNLE

N N

CONV

NLE

ZOE FSE NLE

=4MHz)

XIN

=4MHz

Specifications

Min.

-0.3

Typ.

Max.

+0.3

--200uA

--±2LSB

--20us

Unit

V V

JUNE. 2001 Ver 1.00 13

Page 20

GMS81C2112/GMS81C2120

DC Electrical Characteristics for Standard Pins(5V)

7.4

(VDD = 5.0V ± 10%, V

= 0V, TA = -40 ~ 85°C, f

= 4 MHz, Vdisp = VDD-40V to VDD)

XIN

Specification

Parameter Pin Symbol Test Condition

Min

XIN

Input High Voltage

RESET,SIN,R55,SCLK,

1,EC0

INT0 R53~R57,R6 XIN

,SIN,,R55,SCLK,

Input Low Voltage

RESET

INT0

1,EC0

R53~R57,R6

Output High

Voltage

Output Low

Voltage

Input High

Leakage Current

Input Low

Leakage Current

Input Pull-up

Current(*Option)

Power Fa il

Detect Voltage

Current dissipation

in active mode

Current dissipation

in standby mode

Current dissipation

in stop mode

Hysteresis

Internal RC WDT

Frequency

RC Oscillation

Frequency

1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

R53~R57,R6,BUZO, PWM1O/T1O,SCLK,SOUT

R53~R57,R6

,SIN,R55,SCLK,

RESET

INT1,EC0

INT0 XOUT

XOUT

OL1

OL2

IH1

IL1

PFD

STBY

STOP

T+~VT-

RCWDT

RCOSC

IH1

IH2

IH3

IL1

IL2

IL3

External Clock

External Clock -0.3

= -0.5mA VDD-0.5

= 1.6mA

= 10mA

XIN

=4.5MHz 8 mA

XIN

=4.5MHz 3 mA

XIN

=Off

SXIN

=32.7KHz

R= 120K

0.9V

0.8V

0.7V

-0.3

-1 uA

50 100 180 uA

0.4 V

830KHz

Ω

1.522.5MHz

Typ.

Max

VDD+0.3

0.1V

0.2V

0.3V

0.4 2

1uA

2.7 V

10 uA

Unit

14 JUNE. 2001 Ver 1.00

Page 21

7.5 DC Electrical Characteristics for High-Voltage Pins

GMS81C2112/GMS81C2120

(VDD = 5.0V ± 10%, V

= 0V, TA = -40 ~ 85°C, f

= 4 MHz, Vdisp = VDD-40V to VDD)

XIN

Specification

Parameter Pin Symbol Test Condition

Input High Voltage R0,R2,R30~R34,RA

Input Low Voltage R0,R2,R30~R34,RA

Output High

Voltage

Output Low

Voltage

Input High

Leakage Current

Input Pull-down

Current(*Option)

R0,R2,R30~R34

R0,R2,R30~R34,RA

R0,R2,R30~R34

Input High Voltage R0,R2,R30~R34,RA

1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

= -15mA

= -10mA

= - 4mA

Vdisp = VDD-40

150KΩ atVDD-

VIN=VDD-40V

to V

Vdisp=VDD-35V

VIN=V

Min

0.7V

VDD-40 0.3V

-3.0

VDD-2.0 V

-1.0

200 600 1000 uA

0.7V

Typ.

Max

VDD+0.3

-37

VDD-37

20 uA

VDD+0.3

Unit

V V

JUNE. 2001 Ver 1.00 15

Page 22

GMS81C2112/GMS81C2120

7.6 AC Characteristics

(TA=-40~ 85°C, VDD=5V±10%, VSS=0V)

Parameter Symbol Pins

Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width External Input Pulse Transi-

tion Time RESET Input Width

CPW

RCP,tFCP

EPW

REP,tFEP

RST

Specifications

Min. Typ. Max.

XIN 1 - 8 MHz XIN 80 - - nS XIN - - 20 nS

XIN, XOUT - - 20 mS

INT0, INT1, EC0 2 - -

INT0, INT1, EC0 - - 20 nS

RESET 8--

1/f

CPW

0.5V

-0.5V

Unit

SYS

RESETB

INT0, INT1

EC0

REP

SYS

EPW

FEP

RCP

RST

EPW

FCP

Figure 7-1 Timing Chart

0.2V

0.8V

16 JUNE. 2001 Ver 1.00

Page 23

7.7 AC Characteristics

GMS81C2112/GMS81C2120

(TA=-40~+85°C, VDD=5V±10%, VSS=0V, f

Parameter Symbol Pins

Serial Input Clock Pulse Serial Input Clock Pulse Width Serial Input Clock Pulse Transition

Time

SIN Input Pulse Transition Time

SIN Input Setup Time (External SCLK) SIN Input Setup Time (Internal SCLK) SIN Input Hold Time Serial Output Clock Cycle Time Serial Output Clock Pulse Width Serial Output Clock Pulse Transition

Time Serial Output Delay Time

XIN

SCYC

SCKW

FSCK

RSCK

FSIN

RSIN

SUS

SCYC

SCKW

FSCK

RSCK

OUT

=4MHz)

Specifications

Unit

Min. Typ. Max.

SCLK SCLK

SYS

+70

SYS

-8ns

+200

SCLK - - 30 ns

SIN - - 30 ns

SIN 100 - - ns SIN 200 - ns

SIN SCLK SCLK

SYS

-30

-ns

16t

SYS

ns ns

+70

SCLK 30 ns

SOUT 100 ns

SCLK

SIN

SOUT

0.8V

0.2V

SCYC

FSCK

DD DD

SCKW

SUS

FSIN

0.8V

0.2V

Figure 7-2 Serial I/O Timing Chart

RSCK

SCKW

0.8V

0.2V

RSIN

JUNE. 2001 Ver 1.00 17

Page 24

GMS81C2112/GMS81C2120

7.8 Typical Characteristics

This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices

are guaranteed to operate properly only within the specified range.

R40~R43, R6, R53~R57 BUZO, PWM1O/T1O

SCLK, SOUT pins

4.8 4.9

R40~R43, R6, R53~R57

BUZO, PWM1O/T1O

SCLK, SOUT pins

5.0

V (V)

(mA)

-1.6

-1.2

-0.8

-0.4

(mA)

VDD=4.0V Ta=25°C

−

3.6 3.7

−

(mA)

-1.6

-1.2

-0.8

-0.4

(mA)

VDD=5.0V Ta=25°C

−

4.6 4.7

−

The data presented in this s ection is a statistical s ummary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation

−

VDD=3.0V Ta=25°C

2.6 2.7

−

VDD=3.0V Ta=25°C

2.8 2.9

3.0

3.8 3.9

4.0

V (V)

(mA)

-1.6

-1.2

-0.8

-0.4

(mA)

V (V)

(mA)

-16

-12

-8

-4

VDD=5.0V Ta=25°C

0.6 0.8

−

1.0 2.0

1.0 1.2

R0, R2,RA R30~R34 pins

3.0 4.0

1.4

5.0

(V)

V (V)

1.4

5.0

(V)

V (V)

(mA)

-16

-12

-8

-4

0.6 0.8

−

VDD=4.0V Ta=25°C

1.0 2.0

1.0 1.2

3.0 4.0

(mA)

-16

-12

-8

-4

0.6 0.8

−

VDD=3.0V Ta=25°C

1.0 2.0

1.0 1.2

3.0 4.0

1.4

5.0

(V)

V (V)

18 JUNE. 2001 Ver 1.00

Page 25

GMS81C2112/GMS81C2120

RESET, R55, SIN, SCLK

IH2

INT0, INT1, EC0 pinsXIN pins

RESET, R55, SIN, SCLK

IL2

INT0, INT1, EC0 pinsXIN pins

−

IH3

=4.5MHz

XIN

(V)

Ta=25°C

(V)

−

IL3

=4.5MHz

XIN

(V)

Ta=25°C

IH3

IL3

R53~R57, R6 pins

(V)

R53~R57, R6 pins

(V)

IL2

XIN

Ta=25°C

XIN

Ta=25°C

−

=4.5MHz

−

=4.5MHz

−

=4.5MHz

XIN

Ta=25°C

=4.5MHz

XIN

Ta=25°C

IH1

−

IL1

(V)

IH1

(V)

IL1

(V)

IH2

(V)

(mA)

4.0

3.0

2.0

1.0

Ta=25°C

−

= 4.5MHz

XIN

Normal Operation

2.5MHz

−

SBY

= 4.5MHz

XIN

Stand-by Mode

2.5MHz

(V)

Ta=25°C

(mA)

4.0

3.0

2.0

1.0

(V)

(µA)

2.0

1.5

1.0

0.5

STOP

−

Stop Mode

85°C 25°C

-20°C

(V)

JUNE. 2001 Ver 1.00 19

Page 26

GMS81C2112/GMS81C2120

Stack Address ( 100H ~ 1FEH )

Bit 15 Bit 087

Hardware fixed

00H~FF

8. MEMORY ORGANIZATION

The GMS81C2112 and GMS81C2120 have separate address spaces for Program memory and Data Memory. Pro gram memory can only be read, not written to. It can be up

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.

A X Y

PCH

Figure 8-1 Configuration of Registers

Accumulator:

PCL

PSW

The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y Register as shown below.

ACCUMULATOR X REGISTER Y REGISTER

STACK POINTER PROGRAM COUNTER

PROGRAM STATUS WORD

to 12K/20K bytes of Program memory. Data memory can be read and written to up to 448 by tes includ ing the s tack area.

Generally, SP is automatically updated when a subrout ine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost.

The stack can be located at any position within 100 1FF

of the internal data memory. The SP is not initialized

by hardware, requiring to write the initial v alue (the lo cation with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FF

” is

used.

Note:

The Stack Pointer must be initi alized by softwa re be-

cause its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH

Y A

Two 8-bit Registers can be used as a "YA" 16-bit Register

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers

: In the addressing mode which uses these index registers, the register conten ts a re added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables . The index regi sters also h ave increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.

Stack Pointer

: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore).

Program Counter

: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PC

Program Status Word

:0FFH, PCL:0FEH).

: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C] This flag stores any carry or borrow from the ALU of CPU

after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.

[Zero flag Z] This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

20 JUNE. 2001 Ver 1.00

Page 27

NEGATIVE FLAG

OVERFLOW FLAG

when G=1, page is selected to “page 1”

SELECT DIRECT PAGE

BRK FLAG

Figure 8-3 PSW (Program Status Word) Register

MSB LSB

PSW

V G B H I Z C

GMS81C2112/GMS81C2120

RESET VALUE : 00

CARRY FLAG RECEIVES CARRY OUT

ZERO FLAG INTERRUPT ENABLE FLAG

HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF

ADDITION OPERLANDS

[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction.

[Half carry flag H] After operation, this is set when there is a carry from bit 3

of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V).

[Break flag B] This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector address.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00 addressing area is assigned 100

to 0FFH when this flag is "0". If it is set to "1",

to 1FFH. It is set by

SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7F

) or -128(80H). The CLRV instruction

clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag.

[Negative flag N] This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.

JUNE. 2001 Ver 1.00 21

Page 28

GMS81C2112/GMS81C2120

At execution of a CALL/TCALL/PCALL

01FE 01FD 01FC

01FB

SP before execution

SP after execution

PCH PCL

01FE

01FC

Push down

01FE 01FD 01FC

01FB

SP before execution

SP after execution

At acceptance of interrupt

01FE 01FD 01FC

01FB

At execution of PUSH instruction PUSH A (X,Y,PSW)

01FE

01FD

PCH PCL PSW

01FE

01FB

Push down

01FE 01FD 01FC

01FB

At execution of RET instruction

01FE 01FD 01FC

01FB

At execution of POP instruction POP A (X,Y,PSW)

PCH PCL

01FC

01FE

01FD

01FE

Pop up

At execution of RET instruction

01FE 01FD 01FC

01FB

0100H

01FEH

PCH

PCL

PSW

01FB

01FE

Stack depth

Pop up

Figure 8-4 Stack Operation

22 JUNE. 2001 Ver 1.00

Page 29

8.2 Program Memory

0FFE0H

Address Vector Area Memory

E4 E6 E8 EA EC EE F0

F2 F4 F6 F8 FA FC FE

Serial Communication Interface

Basic Interval Timer

Timer/Counter 0 Interrupt

External Interrupt 0

RESET Vector Area

External Interrupt 1

Watchdog Timer Interrupt

"-" means reserved area.

NOTE:

Timer/Counter 1 Interrupt

A/D Converter

GMS81C2112/GMS81C2120

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 2 0K bytes program memory space only physically implemented. Accessing a location above FFFF

will cause a wrap-around to 0000H.

Figure 8-5, shows a map of Pr ogram Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFE

and FFFFH as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fix ed location in Program Memory. Program Memory area contains the user program.

B000

D000

FEFF

FF00

FFC0 FFDF

FFE0 FFFF

TCALL area

Vector Area

Interrupt

PCALL area

GMS81C2120, 20K ROM

GMS81C2112, 12K ROM

Example: Usage of TCALL

LDA #5

TCALL 0FH ; :;

:; ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0

RET ; FUNC_B: LDA LRG1

RET ; ;TABLE CALL ADD. AREA ;

ORG 0FFC0H ;

DW FUNC_A

DW FUNC_B

1BYTE INSTRUCTION IN STEAD OF 3 BYTES NORMAL CALL

TCALL ADDRESS AREA

The interrupt causes the CPU to jum p to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFA interval: 0FFF8 0FFFA

Any area from 0FF00

. The interrupt service locations spaces 2-byte

and 0FFF9H for External Interru pt 1,

and 0FFFBH for External Interrupt 0, etc.

to 0FFFFH, if it is not going to be

used, its service location is available as general purpose Program Memory.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length .

Table Call (TCALL) c auses the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0 TCALL14, etc., as shown in Figure 8-7.

JUNE. 2001 Ver 1.00 23

for TCALL15, 0FFC2H for

Figure 8-6 Interrupt Vector Area

Page 30

GMS81C2112/GMS81C2120

11111111 11010110

01001010

PC:

FH FH DH 6H

0FFD6

0FF00

0FFFF

0FFD7

➊

➋

➌

0D125

Reverse

Address

0FF00

0FFFF

PCALL Area Memory

PCALL Area

(256 Bytes)

Address P ro gra m Mem o r y

0FFC0

C1 C2

C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF

NOTE:

* means that the BRK software interrupt is using same address with TCALL0.

TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8

TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *

PCALL

→

→ →

rel

4F35 PCALL 35H

0FF00

0FF35

0FFFF

Figure 8-7 PCALL and TCALL Memory Area

TCALL

→

→ →

4A TCALL 4

24 JUNE. 2001 Ver 1.00

Page 31

Example: The usage software example of Vector address for GMS81C2120.

ORG 0FFE0H DW NOT_USED

DW NOT_USED DW SIO ; Serial Interface DW BIT_TIMER ; Basic Interval Timer DW WD_TIMER ; Watchdog Timer DW ADC ; ADC DW NOT_USED DW NOT_USED DW NOT_USED DW NOT_USED DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW INT1 ; Int.1 DW INT0 ; Int.0 DW NOT_USED ; DW RESET ; Reset

GMS81C2112/GMS81C2120

; ORG 0D000H ; GMS81C2112(12K)ROM Start address ;*******************************************

; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts

RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH)

;

ORG 0B000H ; GMS81C2120(20K)ROM Start address

CLRG LDX #0

STA {X}+ CMPX #0C0H BNE RAM_CLR

LDX #0FFH ;Stack Pointer Initialize TXSP

LDM R0, #0 ;Normal Port 0 LDM R0IO,#82H ;Normal Port Direction : : : LDM TDR0,#125 ;8us x 125 = 1mS LDM TM0,#0FH ;Start Timer0, 8us at 4MHz LDM IRQH,#0 LDM IRQL,#0 LDM IENH,#0E0H ;Enable Timer0, INT0, INT1 LDM IENL,#0 LDM IEDS,#05H ;Select falling edge detect on INT pin LDM R0FUNC,#03H ;Set external interrupt pin(INT0, INT1)

EI ;Enable master interrupt : : :

NOT_USED :NOP

: RETI

JUNE. 2001 Ver 1.00 25

Page 32

GMS81C2112/GMS81C2120

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data Memory is divi d ed i nto two groups, a user RAM (including Stack) and control registers.

0000

digital converters and I/O ports. The control registers are in address range of 0C0

to 0FFH.

Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User Memory

00BF 00C0

00FF

0100

01FF

H H

Control

Registers

User Memory or Stack Area

PAGE0

PAGE1

When “G-flag=0”,

this page is selected

When “G-flag=1”

Figure 8-8 Data Memory Map

User Memory

The GMS81C21xx have 448 × 8 bits for the user me mo ry (RAM).

Control Registers

The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to

More detailed informations of each register are explained in each peripheral section.

Note:

Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”.

Example; To write at CKCTLR

LDM CLCTLR,#09H

;Divide ratio(

÷16

)

Stack Area

The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt.

When returning from the processing routine, execu ting the subroutine return instruction [RET] restores the contents of the program counter from the stack; ex ecuting the interrupt return instruction [RETI] restores the contents of the program counter and flags.

The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 22.

26 JUNE. 2001 Ver 1.00

Page 33

GMS81C2112/GMS81C2120

Address

0C0H 0C1H 0C4H 0C5H 0C6H

0C7H 0CAH 0CBH 0CCH 0CDH

0D0H

0D1H

0D1H 0D1H

0D2H

0D3H

0D4H

0D4H 0D4H

0D5H 0DEH

0E0H

0E1H

0E2H

0E3H

0E4H

0E5H

0E6H

0EAH

0EBH 0ECH

0ECH

0EDH

0EFH

0F4H 0F6H 0F7H

0F9H 0FAH 0FBH

Symbol R/W

R0IO

R2IO

R3IO

R5IO

R6IO

TM0

T0 TDR0 CDR0

TM1

TDR1

T1PPR

T1 CDR1

T1PDR

PWM1HR

BUR

SIOM SIOR IENH

IENL

IRQH

IRQL IEDS

ADCM

ADCR

BITR

CKCTLR

WDTR WDTR

PFDR

R0FUNC R5FUNC R6FUNC R5NODR

SCMR

R/W

W W

R R

R/W

W W

R/W R/W R/W R/W R/W R/W R/W R/W

R R

R/W

W W W W

R/W

RESET

Value

Undefined 0000_0000 Undefined 0000_0000 Undefined

---0_0000 Undefined 0000_0--Undefined 0000_0000

--00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000

----_0000 1111_1111

0000_0001 Undefined 0000_---0000_---0000_---0000_----

----_0000

-000_0001 Undefined 0000_0000

-001_0111 0000_0000 0111_1111

----_-100

----_0000

-0--_---0000_0000 0000_0---

---0_0000 Undefined

Addressing

mode

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte byte byte

byte, bit

byte byte byte byte

byte, bit

byte byte

byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit

byte byte byte byte byte

byte, bit

byte byte byte byte byte

Note:

Several names are given at same address. Refer to

below table.

When read When write

Addr.

Timer Mode

Capture

Mode

PWM

Mode

Timer Mode

PWM Mode

D1H T0 CDR0 - TDR0 D3H - TDR1 T1PPR D4H T1 CDR1 T1PDR - T1PDR ECH BITR CKCTLR

Table 8-2 Various Register Name in Same Address

Table 8-1 Control Registers

1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.

3. RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.

JUNE. 2001 Ver 1.00 27

Page 34

GMS81C2112/GMS81C2120

Address Name

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register C7H R3IO R3 Port Direction Register

(Bit[4:0])

CAH R5 R5 Port Data Register (Bit[7:3]) CBH R5IO R5 Port Direction Register (Bit[7:3]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST

D1H

T0/TDR0/ CDR0

Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H

D4H D5H PWM1HR PWM1 Hig h Register

TDR1/ T1PPR

T1/CDR1/ T1PDR

Timer1 Data Register / PWM1 Period Register

Timer1 Register / Capture1 Data Register / PWM1 Duty Register

(Bit[3:0])

DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0

E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - -

E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH

ECH

BITR CKCTLR

Basic Interval Timer Data Register

- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH

PFDR

-----PFDISPFDMPFDS

F4H R0FUNC - - - - BUZO EC0 INT1 INT0

Table 8-3 Control Registers of GMS81C2120

These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ".

28 JUNE. 2001 Ver 1.00

Page 35

GMS81C2112/GMS81C2120

Address Name

F6H R5FUNC F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 - - FAH SCMR - - - CS1 CS0 - - MAINOFF FBHRA -------RA0

These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ".

1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.

2.The register PFDR only be implemented on devices, not on In-circuit Emulator.

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PWM1O/

T1O

Table 8-3 Control Registers of GMS81C2120

- - - - - -

JUNE. 2001 Ver 1.00 29

Page 36

GMS81C2112/GMS81C2120

8.4 Addressing Mode

The GMS800 series MCU uses six addressing modes;

• Register addressing

• Immediate addressing

• Direct page addressing

• Absolute addressing

• Indexed addressing

• Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

→

→ →

#imm

In this mode, second byte (operand) is accessed as a data immediate ly.

Example:

0435 ADC #35H

MEMORY

04 35

A+35H+C → A

(3) Direct Page Addressing

→

→ →

In this mode, a address is specified within direct page. Example; G=0

C535 LDA 35H ;A ←RAM[35H]

35H

data

➋

0E550H 0E551H

C5 35

(4) Absolute Addressing

→

→ →

➊

!abs

data → A

Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command bec omes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY

When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data.

Example: G=1

E45535 LDM 35H,#55H

0135H

➊

0F100H 0F101H 0F102H

data

data ¨ 55H

➋

E4 55 35

Example;

0735F0 ADC !0F035H ;A ←ROM[0F035H]

0F035H

0F100H 0F101H 0F102H

data

07 35 F0

➋

A+data+C → A

➊

address: 0F035

The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag.

30 JUNE. 2001 Ver 1.00

Page 37

983501 INC !0135H ;A ←ROM[135H]

GMS81C2112/GMS81C2120

135H

0F100H 0F101H 0F102H

data

98 35 01

➌

➋

data+1 → data

➊

address: 0135

(5) Indexed Addressing

X indexed direct page (no offset)

→

→ →

{X}

In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15

D4 LDA {X} ;ACC←RAM[X].

115H

data

, G=1

➋

data → A

➊

0E550H

35H

X indexed direct page (8 bit offset)

data

➊

➋

data Æ A

36H Æ X

→

→ →

dp+X

This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

C645 LDA 45H+X

3AH

data

➌

0E550H 0E551H

➋

➊

45H+0F5H=13AH

data → A

X indexed direct page, auto increment

In this mode, a address is specified within direct page by the X register and the content of X is increased by 1.

LDA, STA Example; G=0, X=35

DB LDA {X}+

→

→ →

{X}+

Y indexed direct page (8 bit offset)

→

→ →

dp+Y

This address value is the second byte (Operand) of command plus the data of Y-register, which assign s Memory in Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

→

→ →

!abs+Y

Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area.

Example; Y=55

JUNE. 2001 Ver 1.00 31

Page 38

GMS81C2112/GMS81C2120

D500FA LDA !0FA00H+Y

0F100H 0F101H

0F102H

0FA55H

data

➊

0FA00H+55H=0FA55H

➋

data → A

➌

(6) Indirect Addressing

Direct page indirect

→

→ →

[dp]

Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y.

JMP, CALL Example; G=0

3F35 JMP [35H]

1625 ADC [25H+X]

35H 36H

0E005H

0FA00H

Y indexed indirect

data

16 25

→

→ →

0E005H

➋

[dp]+Y

25 + X(10) = 35

➊

A + data + C → A

➌

Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operan d in Direct pageplus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10

1725 ADC [25H]+Y

35H 36H

0E30AH

0FA00H

X indexed indirect

0A E3

→

→ →

[dp+X]

➋

➊

jump to address 0E30AH

Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register dat a in Direct page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10

25H 26H

0E015H

0FA00H

Absolute indirect

05 E0

data

17 25

→

→ →

[!abs]

➋

➊

0E005H + Y(10) = 0E015H

➌

A + data + C

→

The program jumps to address specified by 16-bit absolute address.

JMP Example; G=0

32 JUNE. 2001 Ver 1.00

Page 39

1F25E0 JMP [!0C025H]

PROGRAM MEMORY

GMS81C2112/GMS81C2120

➊

0E025H 0E026H

0E725H

0FA00H

25 E7

1F 25

➋

jump to address 0E30AH

JUNE. 2001 Ver 1.00 33

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GMS81C2112/GMS81C2120

R0 Data Register R0

ADDRESS: 0C0

RESET VALUE: Undefined

R07 R06 R05 R04 R03

R02 R01

R00

Port Direction

R0 Direction Register R0IO

ADDRESS : 0C1

RESET VALUE : 00

0: Input 1: Output

Input / Output data

R0 Function Selection Register R0FUNC

ADDRESS : 0F4

RESET VALUE : ----0000

0: R00 1: INT0

0: R01 1: INT1

0: R02 1: BUZO

0: R03 1: EC0

123----

9. I/O PORTS

The GMS81C21xx has five ports (R0, R2, R3, R5, and R6).These ports pins may be multiplexed with an alternate function for the peripheral features on the device.

All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specif y it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbe red bits as input ports, write “55

” to address 0C1H (R0 port direction reg-

ister) during initial setting as shown in Figure 9-1. All the port direction registers in the GMS81C2120 have 0

written to them by reset function. On the other hand, its initial status is input.

0C0 0C1 0C2 0C3

WRITE "55

R0 direction

H H

R1 direction

R0 data

R1 data

" TO PORT R0 DIRECTION REGISTER

0 1 0 1 0 1 0 1 76543210

I O I O I O I O

76543210

I : INPUT PORT

O : OUTPUT PORT

BIT

PORT

R0 and R0IO register:

bidirectional I/O port (address 0C0

R0 is an 8-bit high-voltage CMOS

). Each port can be set

individually as input and output through the R0IO register (address 0C1

). Each port can directly drive a vacuum flu-

orescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt Input Port(INT1, INT0)

Port Pin

R00 R01 R02 R03

INT0 (External interrupt 0 Input Port) INT1 (External interrupt 1 Input Port) EC0 (Event Counter Input Port) BUZO (Buzzer Output Port)

.The control register R0FUNC (address F4

Alternate Function

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alter nate function such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the corresponding bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is sel ected to use as alterna te functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0)

Figure 9-1 Example of Port I/O Assignment

RA(Vdisp) register:

only port pin. In addition, RA se rves the funct ions of the

special features. V

disp

power supply pin when selected by the mask option.

RA Data Register RA

Port pin Alternate function

RA is one-bit high-voltage input

is used as a high-voltage input

disp

ADDRESS: 0FB RESET VALUE: Undefined

RA0

Input data

(High-voltage input power supply)

disp

34 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

R5 Data Register R5

ADDRESS: 0CA

RESET VALUE: Undefined

R57

R56 R55 R54 R53

- - -

R5 Direction Register R5IO

ADDRESS : 0CB

RESET VALUE : 00000---

Input / Output data

R5 Function Selection Register R5FUNC

ADDRESS : 0F6

RESET VALUE : -0------

0: R56 1:

- -----6-

R5 N-MOS Open Drain

R5NODR

ADDRESS: 0F9

RESET VALUE: 00000---

N-MOS Open Drain Selection

Selection Register

0: Disable 1: Enable

Port Direction 0: Input 1: Output

PWM1O/T1O

R2 and R2IO register:

bidirectional I/O port (address 0C4

R2 is an 8-bit high-volta ge CMOS

). Each port can be set

individually as input and output th rou gh t he R2IO regis t er (address 0C5

). Each port can directly drive a vacuum flu-

orescent display.

R2 Data Register R2

R27 R26 R25 R24 R23 R22 R21 R20

Input / Output data

R2 Direction Register R2IO

R3 and R3IO register:

R3 is a 5-bit high-voltage CMOS

bidirectional I/O port (address 0C6

ADDRESS: 0C4 RESET VALUE: Undefined

ADDRESS : 0C5 RESET VALUE : 00

Port Direction 0: Input 1: Output

). Each port can be set

individually as input and output th rou gh t he R3IO regis t er (address 0C7

R5FUNC. The control register R5NODR (address 0F9

) controls to

select N-MOS open drain port. To select N -MOS open drain port, write "1" to the corresponding bit of R5 FUNC.

R3 Data Register

- - R34 R33

R3 Direction Register R3IO

- -

R5 and R5IO register:

port (address 0CA input and output through the R5IO register (address 0CB

).In addition, Po rt R5 is multiplexed wi th Pulse

Width Modulator (PWM).

Port Pin

R56

The control register R5FUNC (address 0F6 select PWM function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To select

). Each pin can be set individually as

PWM1 Data Output Timer 1 Data Output

PWM function, write "1" to the corresponding bit of

ADDRESS: 0C6 RESET VALUE: Undefined

R32 R31 R30

ADDRESS : 0C7 RESET VALUE : ---00000

Input / Output data

Port Direction 0: Input 1: Output

R5 is an 5-bit bidirectional I/O

Alternate Function

) controls to

R6 and R6IO register:

port (address 0CC

R6 is an 8-bit bidirectional I/O

). Each port can be set individually as input and output through the R6IO register (address 0CD

). R67~R60 ports are multiplexed with Analog Inpu t

Port.

Port Pin

R60 R61 R62 R63 R64 R65 R66 R67

AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7)

The control register R6FUNC (address 0F7

Alternate Function

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alter nate func-

JUNE. 2001 Ver 1.00 35

Page 42

GMS81C2112/GMS81C2120

tion such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0)

R6 Data Register R6

R67 R66 R65 R64 R63

R6 Direction Register

ADDRESS: 0CC RESET VALUE: Undefined

R62 R61

Input / Output data

ADDRESS : 0CD RESET VALUE : 00

R6IO

Port Direction 0: Input 1: Output

R6 Function Selection Register R6FUNC

0: R67 1: AN7

0: R66 1: AN6

0: R65 1: AN5

0: R64 1: AN4

R60

ADDRESS : 0F7 RESET VALUE : 00

1234567

0: R61 1: AN1

0: R62

1: AN2 0: R63 1: AN3

0: R60 1: AN0

36 JUNE. 2001 Ver 1.00

Page 43

10. BASIC INTERVAL TIMER

GMS81C2112/GMS81C2120

The GMS81C21xx has one 8-bit Basic Interval Timer that is free-run, can not stop. Block di agram is shown in Figure 10-1. In addition, the Basic Interval Tim er generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF).

The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overfl ows fr om FF

to 00H, this overflow causes to

generate the Basic interval timer interrupt. The BITIF is interrupt request flag of Basic interval timer. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2.

When write "1 " to bi t BTCL of CKCTLR, BITR reg ister is cleared to "0" and restart to count-up. The bit BTCL be-

Internal RC OSC

WAKEUP

STOP

comes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit

WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the o scillator, prescaler (only fXIN÷2048) and Timer0.

If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer.

Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0EC

is read as a BITR, and written to CKCTLR.

MUX

128

256

Prescaler

512

1024

Select Input clock

]

[0EC

Basic Interval Timer clock control register

BTS[2:0]

CKCTLR

RCWDT

source clock

[0EC

Internal bus line

8-bit up-counter

BITR

]

clear

BTCL

Read

overflow

Basic Interval

BITIF

To Watchdog timer (WDTCK)

Timer Interrupt

Figure 10-1 Block Diagram of Basic Interval Timer

JUNE. 2001 Ver 1.00 37

Page 44

GMS81C2112/GMS81C2120

CKCTLR

[2:0]

000 001 010 011 100 101 110 111

76543210

CKCTLR

Caution:

Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.

Source clock

XIN

128

XIN

256

XIN

512

XIN

1024

XIN

Interrupt (overflow) Period (ms)

Table 10-1 Basic Interval Timer Interrupt Time

WAKEUP

RCWDT

WDTON

BTCL

BTS1

BTS0BTS2

Basic Interval Timer source clock select 000: f

001: f 010: f 011: f 100: f 101: f 110: f 111: f

Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically

0: Operate as a 7-bit general timer 1: Enable Watchdog Timer operation See the section “Watchdog Timer”.

0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer

ADDRESS: 0EC INITIAL VALUE: -001 0111

÷ 8

XIN

÷ 16

XIN

÷ 32

XIN

÷ 64

XIN

÷ 128

XIN

÷ 256

XIN

÷ 512

XIN

÷ 1024

XIN

after one machine cycle, and starts counting.

@ f

16.384

32.768

65.536

= 4MHz

XIN

0.512

1.024

2.048

4.096

8.192

0: Disable Wake-up Timer 1: Enable Wake-up Timer

BITR

76543210

BTCL

8-BIT FREE-RUN BINARY COUNTER

ADDRESS: 0EC INITIAL VALUE: Undefined

Figure 10-2 BITR: Basic Interval Timer Mode Register

Example 1: Basic Interval Timer Interrupt request flag is generated

every 4.096ms at 4MHz.

: LDM CKCTLR,#03H SET1 BITE EI :

Example 2: Basic Interval Timer Interrupt request flag is generated

every 1.024ms at 4MHz.

: LDM CKCTLR,#01H SET1 BITE EI :

38 JUNE. 2001 Ver 1.00

Page 45

11. WATCHDOG TIMER

GMS81C2112/GMS81C2120

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The purpo se of the watchdog timer is to detect the malfunction (runa way) of program due to external noise or other causes and return the operation to the normal condition.

The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not

require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for ex ample, by entering the STOP mode.

The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and

the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON.

Note:

Because the watchdog timer counter is enabled after clearing Basic Inte rval Timer, af ter the bit WDTO N set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle.

The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below.

LDM CKCTLR,#3FH; enable the RC-osc WDT LDM WDTR,#0FFH; set the WDT period STOP ; enter the STOP mode NOP NOP ; RC-osc WDT running :

The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS). The following equation shows the RCWDT oscillated watchdog timer time-out.

RCWD T

=CLK

×28×[

RCWD T

where, CLK

WD TR.6~0]+(CLK

= 40~ 120uS

RCWD T

×28)/2

In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below.

= [WDTR.6~0]

WDT

××××

Interval of BIT

clear

BASIC INTERVAL TIMER OVERFLOW

Count source

WDTCL

[0ED

Watchdog

Counter (7-bit)

7-bit compare data

WDTR

]

Internal bus line

clear

comparato r

Watchdog Timer Register

“0” “1”

enable

WDTON in CKCTLR [0EC

WDTIF

to reset CPU

Watchdog Timer interrupt

]

Figure 11-1 Block Diagram of Watchdog Timer

JUNE. 2001 Ver 1.00 39

Page 46

GMS81C2112/GMS81C2120

Watchdog Timer Control

Figure 11-2 shows the watchdog timer control register. The watchdog timer is automatically disab led aft e r reset.

The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time.

If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from

WDTR

WWWW

76543210

WDTCL

Clear count flag

0: Free-run count 1: When the WDTCL is set to "1", binary counter

is cleared to “0”. And the WDTCL becomes “0” automatically after one machine cycle. Counter count up again.

WWWW

the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET When WDTON=0, a watchdog timer interrupt (WDTIF) is generated.

The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).

7-bit compare data

Figure 11-2 WDTR: Watchdog Timer Data Register

Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz

pin to low to reset the internal hardware.

ADDRESS: 0ED INITIAL VALUE: 0111_1111

NOTE: The WDTON bit is in register CKCTLR.

Within WDT detection time

LDM CKCTLR,#3FH ; LDM WDTR,#04FH

LDM WDTR,#04FH ; : : : : LDM WDTR,#04FH ; : : : : LDM WDTR,#04FH ;

Select 1/2048 clock source, WDTON ← 1, Clear Counter

Clear counter

40 JUNE. 2001 Ver 1.00

Page 47

GMS81C2112/GMS81C2120

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to “1”. WDTON is initialized to “0” during reset and it should be set to “1” to operate after reset is released.

Example: Enables watchdog timer for Reset

: LDM CKCTLR,#xx1x_xxxxB; : :

WDTON

← 1

The watchdog timer is disabled by clearing bit 5 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released.

Source clock BIT overflow

Binary-counter

WDTR

WDTIF interrupt

WDT reset reset

Watchdog Timer Interrupt

The watchdog timer can be also used as a simple 7-bit timer by clearin g bit5 of CKCTLR to “0”. The in terval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.

The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source.

Example: 7-bit timer interrupt set up.

WDTR ← "0100_0011

T WDT R Interval of BIT

LDM CKCTLR,#xx0xxxxxB; LDM WDTR,#7FH ;

WDTCL

Counter Clear

Match Detect

WDTON

←1

←0

Figure 11-3 Watchdog timer Timing

If the watchdog timer output becomes active, a reset is generated, which drives the RESET

pin low to reset the inter-

nal hardware.

The main clock oscillator also turns on wh en a watchdog timer reset is generated in sub clock mode.

JUNE. 2001 Ver 1.00 41

Page 48

GMS81C2112/GMS81C2120

12. TIMER/EVENT COUNTER

The GMS81C21xx has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match).

Timer 0 and Timer 1 are can be used either two 8-bit Timer/Counter or one 16-bit Timer/Counter with combine them.

In the "timer" function, the register is increased every internal clock input. Thus , one can th ink of it as count ing in ternal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8).

In the “counter” function, the register is increase d in re-

16BIT CAP0 CAP1 PWM1E

0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event c ounter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output 0 X 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 X 0 XX X 11 0 16-bit Captu re (internal clock) 1 0 0 0 XXX 11 1 16-bit Compare Output

T0CK

[2:0]

T1CK

[1:0]

PWM1O TIMER 0 TIMER 1

sponse to a 1-to-0 (falling edge) or 0-to-1(ris ing edge) transition at its corresponding external input pin, EC0.

In addition the “capture” function, the register is increased in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into capture data register CDRx.

Timer1 is shared with "PWM" function and "Compare output" function

It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer m ode register TM0 and TM1 as shown in Figure 12-1 and Table 12-1.

Table 12-1 Operating Modes of Timer0 and Timer1

42 JUNE. 2001 Ver 1.00

Page 49

TM0

R/W R/W R/W R/W R/W R/W

543210

-- T0CN

BTCL

T0STT0Ck0T0CK1CAP0 T0Ck2

Bit Name Bit Position Description

CAP0 TM0.5 0: Timer/Counter mode

1: Capture mode selection flag

T0CK2 T0CK1 T0CK0

TM0.4 TM0.3 TM0.2

000: 8-bit Timer, Clock source is f 001: 8-bit Timer, Clock source is f 010: 8-bit Timer, Clock source is f 011: 8-bit Timer, Clock source is f 100: 8-bit Timer, Clock source is f 101: 8-bit Timer, Clock source is f 110: 8-bit Timer, Clock source is f

(External clock)

111: EC0

T0CN T M0 .1 0: Stop the time r

1: A logic 1 starts the timer.

T0ST TM0.0 0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

ADDRESS: 0D0 INITIAL VALUE: --000000

÷ 2

XIN

÷ 4

XIN

÷ 8

XIN

÷ 32

XIN

÷ 128

XIN

÷ 512

XIN

÷ 2048

XIN

GMS81C2112/GMS81C2120

TM1

R/W R/W R/W R/W R/W R/W R/W R/W

76543210

PWM1E

16BITPOL T1CN

CAP1

BTCL

T1STT1CK0T1CK1

Bit Name Bit Position Description

POL TM1.7 0: PWM Duty Active Low

1: PWM Duty Active High

16BIT TM1.6 0: 8-bit Mode

1: 16-bit Mode

PWMIE TM1.5 0: Disable PWM

1: Enable PWM

CAP1 TM1.4 0: Timer/Counter mode

1: Capture mode selection flag

T1CK1 T1CK0

TM1.3 TM1.2

00: 8-bit Timer, Clock source is f 01: 8-bit Timer, Clock source is f 10: 8-bit Timer, Clock source is f 11: 8-bit Timer, Clock source is Using the the Timer 0 Clock

T0CN TM1.1 0: Stop the timer

1: A logic 1 starts the timer.

T0ST TM1.0 0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

76543210

TDR0

R/W R/W R/W R/W R/W R/W R/W R/W

76543210

TDR1

ADDRESS: 0D2 INITIAL VALUE: 00

XIN

÷ 2

XIN

÷ 8

XIN

ADDRESS: 0D1 INITIAL VALUE: Undefined

ADDRESS: 0D3 INITIAL VALUE: Undefined

Read: Count value read Write: Compare data write

Figure 12-1 TM0, TM1 Registers

JUNE. 2001 Ver 1.00 43

Page 50

GMS81C2112/GMS81C2120

12.1 8-bit Timer / Counter Mode

The GMS81C21xx has two 8-bit Timer/Counte rs, Timer 0 , Timer 1 as shown in Figure 12-2.

The "timer" or "counter" function is selected by mode registers TMx as shown in Fi gure 12-1 and Table 12-1. To use

76543210

EC0 PIN

XIN PIN

TM0

TM1

EDGE DETECTOR

Prescaler

--T0CN

-- XXXX

76543210

16BITPOL T1CN T1STT1CK0T1CK1

X0 XXXX







512



2048



PWM1E

T0CK[2:0]

111

000 001

010 011 100

101 110

MUX

CAP1

BTCL

T0CN

TIMER 0

as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to “0”(Table 12-1).

T0STT0CK0T0CK1CAP0 T0CK2

X means don’t care

T0ST

0: Stop 1: Clear and start

T0 (8-bit)

TDR0 (8-bit)

ADDRESS: 0D0 INITIAL VALUE: --000000

ADDRESS: 0D2 INITIAL VALUE: 00

Comparator

clear

T0IF

F/F

TIMER 0 INTERRUPT

T0O PIN

T1CK[1:0]

T1ST



MUX

T1CN

TIMER 1

0: Stop 1: Clear and start

T1 (8-bit)

TDR1 (8-bit)

clear

Comparator

T1IF

F/F

TIMER 1 INTERRUPT

T1O PIN

Figure 12-2 8-bit Timer/Counter 0, 1

44 JUNE. 2001 Ver 1.00

Page 51

GMS81C2112/GMS81C2120

Example 1:

Timer0 = 2ms 8-bit timer mode at 4M Hz Timer1 = 0.5ms 8-bit timer mode at 4MHz

LDM TDR0,#250 LDM TDR1,#250 LDM TM0,#0000_1111B LDM TM1,#0000_1011B SET1 T0E SET1 T1E EI

Example 2:

Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz

LDM TDR0,#250 LDM TDR1,#250 LDM TM0,#0001_1111B LDM TM1,#0000_1011B SET1 T0E SET1 T1E EI

Note:

The contents of Timer data register TDRx should be initialized 1 set.

~FFH, not 0H, because it is undefined after re-

These timers have each 8-bit count register and data register. The count register is increased by every intern al or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 selected by control bits T0CK[2:0] of register (TM0) and 1, 2, 8 selected by control bits T1CK[1:0] of register (TM1). In the Timer 0, timer register T0 increases from 00 TDR0 and then reset to 00

. The match output of Timer 0

until it matches

generates Timer 0 interru pt (latched in T0IF bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx.

In counter function, the counter is increased every 0-to1(1-to-0) (rising & falling edge) transi tion of EC0 pin. In order to use counte r fun ctio n, th e bit EC0 o f t he R0

tion Selection

(R0FUNC.2) is set to "1". The Timer

Func-

0 can be used as a counter by pin EC0 input, but Timer 1 can not.

JUNE. 2001 Ver 1.00 45

Page 52

GMS81C2112/GMS81C2120

8-bit Timer Mode

In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer 1 interrupt (T1IF) is generated and the up-counter is cleared to 0.

Start count

Source clock

Up-counter

TDR1 T1IF interrupt

Example:

When

INTERRUPT PERIOD =

TDR1

Timer 1 (T1IF) Interrupt

Make 2msinterrupt using by Timer0 at 4MHz

LDM TM0,#0FH ; divide by 32 LDM TDR0,#125 ; 8us x 125= 1ms SET1 T0E ; Enable Timer 0 Interrupt EI ; Enable Master Interrupt

TM0 = 0000 1111 TDR0 = 125 f

= 4 MHz

XIN

(8-bit Timer mode, Prescaler divide ratio = 32)

= 7D

4 × 10

Occur interrupt Occur interrupt Occur interrupt

Figure 12-3 Timer Mode Timing Chart

(TDR0 = T0)

32 × 125 = 1 ms

MATCH

up-count

Interrupt period = 8 µs x 125

Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time in-

terval is set as you want

n-2

n-1

Match Detect

Count Pulse Period

8 µs

Counter Clear

1 4

TIME

Figure 12-4 Timer Count Example

46 JUNE. 2001 Ver 1.00

Page 53

8-bit Event Counter Mode

GMS81C2112/GMS81C2120

In this mode, counting up is started by an external trigger. This trigger means falling edge or rising edge of the EC0 pin input. Source clock is used as an internal clock selected with timer mode register TM0. The conten ts of ti mer data register TDR0 is compared with the contents of the upcounter T0. If a match is found, an timer interrupt request flag T0IF is generated, and the counter is cleared to “0”. The counter is restart and count up continuously by every falling edge or rising edge of the EC0 pin input.

The maximum frequency applied to the EC0 pin is f

XIN

[Hz].

Start count

ECn pin input

Up-counter

TDR1

T1IF interrupt

Figure 12-5 Event Counter Mode Timing Chart

In order to use event counter function, the bit 2 of the R5 function register (R5FUNC.2) is required to be set to “1”.

After reset, the value of timer data register TDR0 is undefined, it should b e initialized to between 1

~FFH not to

"0"The interval period of Timer is calculated as below equation.

Period (sec)

---------- -

2 Divide Ratio TDR0

XIN

×××=

n-1

TDR1

Timer 1 (T1IF) Interrupt

T1ST Start & St op

T1CN Control count

disable

clear & start

stop

Occur interrupt Occur interrupt

T1ST = 1

T1ST = 0

enable

up-count

T1CN = 1

T1CN = 0

Figure 12-6 Count Operation of Timer / Event counter

TIME

JUNE. 2001 Ver 1.00 47

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GMS81C2112/GMS81C2120

12.2 16-bit Timer / Counter Mode

The Timer register is bein g run with 16 bi ts. A 16-bit ti mer/ counter register T0, T1 are increased from 0000 matches TDR0, TDR1 and then resets to 0000

until it

. The

match output generates Timer 0 interrupt not Timer 1 interrupt.

The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0].

In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively.

EC0 PIN

XIN PIN

TM0

TM1

EDGE DETECTOR

76543210

CAP1

T0CN

BTCL

Higher byte

COMPARE DATA

X means don’t care

T0ST

0: Stop 1: Clear and start

T1 + T0 (16-bit)

TDR1 + TDR0

(16-bit)

Lower byte

T0STT0CK0T0CK1CAP0 T0CK2

Comparator

--T0CN

-- XXXX

76543210

16BITPOL T1CN T1STT1CK0T1CK1

X1 XX11

T0CK[2:0]

111



000



001



010



011



÷ ÷

512



2048



100 101 110

MUX

Prescaler

PWM1E

ADDRESS: 0D0 INITIAL VALUE: --000000

ADDRESS: 0D2 INITIAL VALUE: 00

clear

T0IF

(Not Timer 1 interrupt)

F/F

TIMER 0 INTERRUPT

T0O PIN

TIMER 0 + TIMER 1 → TIMER 0 (16-bit)

Figure 12-7 16-bit Timer/Counter

48 JUNE. 2001 Ver 1.00

Page 55

12.3 8-bit Compare Output (16-bit)

COMP

Oscillation F r equency

2 Prescaler Value T DR 1

)+(××

---------------------------------------------------------------------------------

The GMS81C21xx has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, T1O) as shown in Figure 12-2 and Figure 12-7. Thus, pulse out is generated by the timer match. These operation is implemented to pin, T0O, PWM1O/T1O.

In this mode, the bit PWM1O/T1O of R5 function register (R5FUNC.6) should be set to "1", and the bit PWM1E of timer1 mode register (TM1) should be set to "0". In addi-

12.4 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bi t CAP1 of tim er mode reg ister TM1 for Timer 1) as shown in Figure 12-8.

As mentioned above, not on ly Timer 0 but Timer 1 can also be used as a capture mode.

The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer in terrup t is gener ated wh en timer register T0 (T1) increases and matches TDR0 (TDR1).

This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer.

For example, in Figure 12-10, the pulse width of captured signal is wider than the timer data value (FF times. When external interrupt is occurred, the captured value (13

) is more little than wanted value. It can be ob-

) over 2

GMS81C2112/GMS81C2120

tion, 16-bit Compare output mode is available, also. This pin output the signal having a 50 : 50 duty square

wave, and output frequency is same as below equation.

tained correct value by counting the number o f timer overflow occurrence.

Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware.

Note:

The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation.

It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.

JUNE. 2001 Ver 1.00 49

Page 56

GMS81C2112/GMS81C2120

EC0 PIN

XIN PIN

TM0

TM1

Edge Detector

Prescaler

76543210

CAP1

IEDS[1:0]

BTCL

T0CN

T0STT0CK0T0CK1CAP0 T0CK2

X means don’t care

T0 (8-bit)

clear

Capture

CDR0 (8-bit)

--T0CN

-- XXXX

76543210

16BITPOL T1CN T1STT1CK0T1CK1

X0 XXXX

T0CK[2:0]







512



2048



PWM1E

111

000 001

010 011

100 101 110

MUX

ADDRESS: 0D0 INITIAL VALUE: --000000

ADDRESS: 0D2 INITIAL VALUE: 00

T0ST

0: Stop 1: Clear and start

INT0 PIN

INT1 PIN



“01”

T1CK[1:0]

11 00

01 10

MUX

IEDS[1:0]

“10”

“11”

T1CN

“01” “10”

“11”

Figure 12-8 8-bit Capture Mode

clear

Capture

T1ST

0: Stop 1: Clear and start

T1 (8-bit)

CDR1 (8-bit)

INT0IF

INT1IF

INT0 INTERRUPT

INT1 INTERRUPT

50 JUNE. 2001 Ver 1.00

Page 57

Ext. INT0 Pin

Interrupt Request

( INT0F )

GMS81C2112/GMS81C2120

This value is loaded to CDR0

n-1

coun

Interrupt Interval Period

TIME

Ext. INT0 Pin

Interrupt Request

( INT0F )

Ext. INT0 Pin

Interrupt Request

( INT0F )

Interrupt Request

( T0F )

Delay

Capture

Clear & Start

( Timer Stop )

Figure 12-9 Input Capture Operation

Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H

Figure 12-10 Excess Timer Overflow in Capture Mode

JUNE. 2001 Ver 1.00 51

Page 58

GMS81C2112/GMS81C2120

12.5 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits.

The clock source of the Timer 0 is selected either internal

or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 an d 16BIT of TM1

should be set to "1" respectively.

EC0 PIN

XIN PIN

INT0 PIN

TM0

TM1

Edge Detector

Prescaler

76543210

CAP1

IEDS[1:0]

BTCL

T0CN

“01” “10”

“11”

T0STT0CK0T0CK1CAP0 T0CK2

X means don’t care

TDR1 + TDR0

(16-bit)

clear

Capture

CDR1 + CDR0

(16-bit)

Higher byte

CAPTURE DATA

--T0CN

-- XXXX

76543210

16BITPOL T1CN T1STT1CK0T1CK1

X1 XX11

T0CK[2:0]







512



2048



PWM1E

111

000 001

010 011 100

101 110

MUX

ADDRESS: 0 D0 INITIAL VALUE: --000000

ADDRESS: 0D2 INITIAL VALUE: 00

T0ST

0: Stop 1: Clear and start

Lower byte

INT0IF

INT0 INTERRUPT

Figure 12-11 16-bit Capture Mode

52 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

Example 1:

Timer0 = 16-bit timer mode, 0.5s at 4MHz

LDM TM0,#0000_1111B;8uS LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<62500 ;8uS X 62500 LDM TDR1,#>62500 ;=0.5s SET1 T0E EI : :

Example 2:

Timer0 = 16-bit event counter mode

LDM R0FUNC,#0000_0100B;EC0 Set LDM TM0,#0001_1111B;Counter Mode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; SET1 T0E EI : :

12.6 PWM Mode

The GMS81C2120 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1.

In PWM mode, pin R5 6/P WM1O/ T1O out p uts up t o a 10bit resolution PWM output . This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register.

The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the dut y of the PWM output is determined by the T1PDR (PWM1 Duty Register) and PWM1HR[1:0] (bit1,0 of PWM1 High Register).

The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2].

Example 3:

Timer0 = 16-bit capture mode

LDM R0FUNC,#0000_0001B;INT0 set LDM TM0,#0010_1111B;Capture Mode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; LDM IEDS,#01H;Falling Edge SET1 T0E EI : :

And writes duty value to the T1PDR and the PWM1HR[1:0] same way.

The T1PDR is configured as a double buffering for glitchless PWM output. In Figure 12-12, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i .e. at t he beg inning of next duty cycle)

PWM Period = [PWM1HR[3:2]T1PPR] X Source Clock PWM Duty = [PWM1HR[1:0]T1PDR] X Source Clock

The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency vs. resolution.

JUNE. 2001 Ver 1.00 53

Page 60

GMS81C2112/GMS81C2120

If it needed more higher frequency of PWM, it should be reduced resolution.

Frequency

Resolution

10-bit 3.9KHz 0.98KHZ 0.49KHZ

9-bit 7.8KHz 1.95KHz 0.97KHz 8-bit 15.6KHz 3.90KHz 1.95KHz 7-bit 31.2KHz 7.81KHz 3.90KHz

Table 12-2 PWM Frequency vs. Resolution at 4MHz

TM1

PWM1HR

T1CK[1:0]

= 00(250nS)

POL 16BIT PWM1E CAP1

X010

- - -

----

T1CK[1:0]

= 01(500nS)

T1CK[1:0]

= 10(2uS)

T1CK1 T1CK0 T1CN T1ST

XXXX

- PWM1HR3PWM1HR2PWM1HR1PWM1HR0

XXXX

Period High

PWM1HR[3:2]

The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM

output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00

", the PWM output is deter-

mined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM ou tput. How-

ever the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 12-14. As it were, the ab solute duty time is not changed in varying frequency. But the changed peri od value must greater than the duty value.

ADDRESS : D2H RESET VALUE : 00000000

ADDRESS : D5H RESET VALUE : ----0000

Bit Manipulation Not Available

Duty High

X : The value "0" or "1" corresponding your operation.

T0 clock source

[T0CK]

T1CK[1:0]

MUX

T1ST

0 : Stop 1 : Clear and Start

T1CN

Slave

Master

T1PPR(8-bit)

COMPARATOR

(2-bit)

T1 ( 8-bit )

COMPARATOR

T1PDR(8-bit)

PWM1HR[1:0]

T1PDR(8-bit)

Figure 12-12 PWM Mode

CLEAR

POL

PWM1O

[R5FUNC.6]

R56/

PWM1O/T1O

54 JUNE. 2001 Ver 1.00

Page 61

Source clock

PWM1E

T1ST

T1CN

PWM1O [POL=1]

PWM1O [POL=0]

02 03 04 05 7F

0100

Duty Cycle [ 80H x 250nS = 32uS ]

Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ]

GMS81C2112/GMS81C2120

81 02 03

3FF

0100

T1CK[1:0] = 00 ( f PWM1HR = 0CH

T1PPR = FFH T1PDR = 80H

T1CK[1:0] = 10 ( 1uS )

PWM 1HR = 00H T1PPR = 0EH T1PDR = 05H

Source clock

PWM1O POL=1

02 03 04

Duty Cycle

[ 05H x 2uS = 10uS ]

)

PWM1HR3 PWM1HR2

Period

PWM1HR1 PWM1HR0

Duty

Figure 12-13 Example of PWM at 4MHz

Write T1PPR to 0AH

06 08 09 0B 0C 0D

T1PPR (8-bit)

11 FFH

T1PDR (8-bit)

00 80H

Period changed

02 03 04

Duty Cycle

[ 05H x 2uS = 10uS ]

06 07 08 09

02 03 0407 0A

Duty Cycle

[ 05H x 2uS = 10uS ]

Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ]

Period Cycle [ 0AH x 2uS = 20uS, 50KHz ]

Figure 12-14 Example of Changing the Period in Absolute Duty Cycle (@4MHz)

JUNE. 2001 Ver 1.00 55

Page 62

GMS81C2112/GMS81C2120

13. ANALOG DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AV

of ladder resistance

of A/D module. The A/D module has two registers which are the control

register ADCM and A/D result register ADR. The register ADCM, shown in Figure 13-1, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O.

To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register.

R/W R/W R/W R/W R/W R

BTCL

ADEN

ADS1 ADS0 - ADS2

ADCM

76543210

ADST

And selected the corresponding channel to b e converted by setting ADS[3:0].

How to Use A/D Converter

The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block di agram of the A /D mo dule is shown in Figu re 13-2. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20

uS (at f

ADSF

=4 MHz)

ADDRESS: 0EA INITIAL VALUE: -0-0 0001

A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed

ADCR

RRRR RR

76543210

A/D Conversion Data

BTCL

Figure 13-1 A/D Converter Control Register

A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware.

Analog input channel select 000: Channel 0 (AN0) 001: Channel 1 (AN1) 010: Channel 2 (AN2) 011: Channel 3 (AN3) 100: Channel 4 (AN4) 101: Channel 5 (AN5) 110: Channel 6 (AN6) 111: Channel 7 (AN7)

A/D converter Enable bit 0: A/D converter module turn off and

current is not flow.

1: Enable A/D converter

ADDRESS: 0EB INITIAL VALUE: Undefined

56 JUNE. 2001 Ver 1.00

Page 63

GMS81C2112/GMS81C2120

R60/AN0

R61/AN1

R62/AN2

R63/AN3

R64/AN4

R65/AN5

R66/AN6

R67/AN7

R6FUNC[7:0]

ANSEL0

ANSEL1

ANSEL2

ANSEL3

ANSEL4

ANSEL5

ANSEL6

ADS[2:0]

000

001

010

011

100

101

110

111

S/H

Sample & Hold

“0”

“1”

ADEN

LADDER R E SISTOR

8-bit DAC

SUCCESSIVE

APPROXIMATION

CIRCUIT

ADR (8-bit)

A/D result register

A/D INTERRUPT

ADIF

ADDRESS: E9 RESET VALUE: Undefined

ANSEL7

Figure 13-2 A/D Block Diagram

JUNE. 2001 Ver 1.00 57

Page 64

GMS81C2112/GMS81C2120

AN11~AN0

100~1000pF

Analog Input

(2) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid to

ENABLE A/D CONVERTER

A/D INPUT CHANNEL SELECT

ANALOG REFERENCE SELECT

A/D START ( ADST = 1 )

noise on pins AVDD and AN7 to AN0. Since

es in proportion to the output impedance of the analog input source, it is recommended that

externally as shown in Figure 13-4 in order to reduce noise.

Figure 13-4 Analog Input Pin Connecting Capacitor

the effect increas-

a capacitor be connected

NOP

ADSF = 1

YES

READ ADCR

Figure 13-3 A/D Converter Operation Flow

A/D Converter Cautions

(1) Input range of AN7 to AN0 The input voltage of AN7 to AN0 should be within the

specification range. In particular, if a vo ltage above A

or below AVSS rating range), the con version value for t hat ch annel can n ot be in determinate. The conversion values of the ot her channels may also be affected.

is input (even if within the absolute maximum

VDD

(3) Pins AN7/R67 to AN0/R60 The analog input pins AN7 to AN0 also function as input/

output port (PORT R6) pi ns. When A/D convers ion i s performed with any of pins AN7 to AN0 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/ D conversion, the expe cted A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.

(4) AVDD pin input impeda n ce A series resistor string of approximately 10KΩ is connected be-

tween the AVDD

pin and the AVS S pin.

Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connectio n

series resistor string between the AVDD and there will be a large reference voltage error.

pin and the AVSS pin,

to the

58 JUNE. 2001 Ver 1.00

Page 65

14. SERIAL PERIPHERAL INTERFACE

GMS81C2112/GMS81C2120

The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The Se rial Peripheral Interf ace(SPI) is 8-bit

SCK[1:0]

POL

“0”

“1”

IOSW

XIN PIN

Timer0 Overflow

SCLK PIN

SOUT

IOSWIN

Prescaler

SCK[1:0]

“11”

not “11”

SOUT

00 01 10

MUX

clock synchronous type and consists of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. The SOUT pin is designed to input and output. So Serial Peripheral Interface(SPI) can be operated with minimum two pin

SPI

SIOSF

Complete

Clock

overflow

Octal

Counter

SIOIF

Serial communication Interrupt

SIOST

Start

Clock

CONTROL

CIRCUIT

SIN PIN

IOSWIN

Input shift register

SIOR

Internal Bus

Figure 14-1 SPI Block Diagram

Shift

JUNE. 2001 Ver 1.00 59

Page 66

GMS81C2112/GMS81C2120

Serial I/O Mode Register(SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected. The serial transmission operation mode is decided by setting the SM1 and SM0, and the polarity of transfer clock is selected by setting the POL.

Serial I/O Data Register(S IOR) is a 8-bit shift regi ster. First LSB is send or is received. When receiving mode, serial input pin is selected by IOSW. The SPI allows 8-bits of data to be synchronously transmitted and received.

R/W

R/W R/W R/W R/W R/W R

BTCL

SCK1 SCK0SM1

SM0

SIOM

76543210

IOSWPOL SIOST

To accomplish communication, typically three pins are used:

- Serial Data In R54/SIN

- Serial Data Out R55/SOUT

- Serial Clock R53/SCLK

SIOSF

ADDRESS: 0E0 INITIAL VALUE: 0000 0001

Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed

Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware.

Serial transmission Clock selection 00: f

XIN

01: f

XIN

10: TMR0OV(Timer0 Overflow) 11: External Clock

SIOR

R/W R/W R/W R/W R/W R/W

R/W

76543210

Sending Data at Sending Mode Receiving Data at Receiving Mode

R/W

BTCL

Figure 14-2 SPI Control Register

Serial transmission Operation Mode 00: Normal Port(R55,R54,R53) 01: Sending Mode(SOUT,R54,SCLK) 10: Receiving Mode(R55,SIN,SCLK) 11: Sending & Receiving Mode(SOUT,SIN,SCLK)

Serial In put Pin Selection bit 0: SIN Pin Selection

1: IOSWIN Pin Selection

Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge

Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge

Received Data Latch at Falling Edge

ADDRESS: 0E1 INITIAL VALUE: Undefined

60 JUNE. 2001 Ver 1.00

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14.1 Transmission/Receiving Timing

GMS81C2112/GMS81C2120

The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycle of SCK, SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at falling edge of SCLK. And input data

SIOST

SCLK [R53]

(POL=0)

SOUT [R55]

SIN [R54]

(IOSW=0)

IOSWIN [R 5 5 ]

(IOSW=1)

SIOSF

(SPI Status)

SPIIF

(SPI Int. Req)

D1 D2 D3 D4 D6 D7D0 D5

is latched at rising edge of SCLK pin. When transmis sion clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and serial I/ O interrupt(IFSIO) occurred.

SIOST

SCLK [R53]

(POL=1)

SOUT [R55]

SIN [R54]

(IOSW=0)

IOSWIN [R 5 5 ]

(IOSW=1)

SIOSF

(SPI Status)

SPIIF

(SPI Int. Req)

Figure 14-3 SPI Timing Diagram at POL=0

D1 D2 D3 D4 D6 D7D0 D5

Figure 14-4 SPI Timing Diagram at POL=1

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GMS81C2112/GMS81C2120

14.2 The method of Serial I/O

 Select transmission/receiving mode

Note:

When external clock is used, the frequency should

be less than 1MHz and recommended duty is 50%.

 In case of sending mode, write data t o be s end to SIOR.  Set SIOST to “1” to start serial transmission.

Note:

If both transmission mode is selected and transmis-

sion is performed simultaneously it would be made error.

14.3 The Method to Test Correct Transmission

Serial I/O Interrupt Service Routine

SIOSF

SE = 0

 The SIO interrupt is generated at the completion of SIO and SIOSF is set to “1”. In SIO interrupt service routine, correct transmission should be tested.

 In case of receiving mode, the received data is acquired by reading the SIOR.

Abnormal

Write SIOM

Normal Operation

- SE : Interrupt Enable Register Low IENL(Bit3)

- SR : Interrupt Request Flag Register Low IRQL(Bit3)

Overrun Error

Figure 14-5 Serial Method to Test Transmission

62 JUNE. 2001 Ver 1.00

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15. BUZZER FUNCTION

GMS81C2112/GMS81C2120

The buzzer driver block consists of 6-bit binary counter, buzzer register BUR, and clock source selector. It generates square-wave which has very wide range frequency (480Hz ~ 250kHz at f

= 4MHz) by user software.

XIN

A 50% duty pulse can be output to R03/BUZO pin to use for piezo-electric buzzer drive

port of Buzzer driver by setting the bit 3 of R0FUNC(address 0F4

) to “1”.

At this time, the pin R03 must be defined as

. Pin R03 is assigned for output

output mode (the bit 3 of R0IO=1). Example: 5kHz output at 4MHz.

LDM R0IO,#XXXX_1XXXB LDM BUR,#0011_0010B

LDM R0FUNC,#XXXX_1XXXB

X means don’t care

6-BIT COUNTER

Compare data

BUR

]

6-bit binary

XIN PIN

Prescaler

MUX

[0DE

The bit 0 to 5 of BUR determines output frequency for buzzer driving.

Equation of frequency calcu lation is shown below .

--------------------------------------------------------------------------- -

BUZ

2 DivideRatio BUR 1+()××

: Buzzer frequency

BUZ

: Oscillator frequency

XIN

Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUR. Buzzer period value.

XIN

The frequency of output signal is controlled by the buzzer control register BUR.The bit 0 to bit 5 of BUR determine output frequency for buzzer driving.

R03 port data

[0F4

0 1

R0FUNC

]

R03/BUZO PIN

Port selection

Comparator

F/F

Internal bus line

Figure 15-1 Block Diagram of Buzzer Driver

ADDRESS: 0DE RESET VALUE: Undefined

BUR[5:0] Buzzer Period Data

Source clock select 00:

01: ÷ 16 10: ÷ 32 11: ÷ 64

R0FUNC

ADDRESS : 0F4 RESET VALUE : ---- 0000

BUZO EC0 INT1 INT0

R03/BUZO Selection 0: R03 port (Turn off buzzer) 1: BUZO port (Turn on buzzer)

BUR

BUCK1

BUCK0

WWWWWW

Figure 15-2 R0FUNC and Buzzer Register

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GMS81C2112/GMS81C2120

Note:

BUR is undefined after rese t, so it m ust be in itialize d

to between 1

and 3FH by software.

Note that BUR is a write-only register.

BUR [5:0]

00 01 02 03 04 05 06 07

08 09 0A

0B 0C 0D

1B 1C 1D

00 01 10 11 00 01 10 11

250.000

125.000

83.333

62.500

50.000

41.667

35.714

31.250

27.778

25.000

22.727

20.833

19.231

17.857

16.667

15.625

14.706

13.889

13.158

12.500

11.905

11.364

10.870

10.417

10.000

9.615

9.259

8.929

8.621

8.333

8.065

7.813

BUR[7:6]

125.000

62.500

41.667

31.250

25.000

20.833

17.857

15.625

13.889

12.500

11.364

10.417

9.615

8.929

8.333

7.813

7.353

6.944

6.579

6.250

5.952

5.682

5.435

5.208

5.000

4.808

4.630

4.464

4.310

4.167

4.032

3.906

62.500

31.250

20.833

15.625

12.500

10.417

8.929

7.813

6.944

6.250

5.682

5.208

4.808

4.464

4.167

3.906

3.676

3.472

3.289

3.125

2.976

2.841

2.717

2.604

2.500

2.404

2.315

2.232

2.155

2.083

2.016

1.953

31.250

15.625

10.417

7.813

6.250

5.208

4.464

3.906

3.472

3.125

2.841

2.604

2.404

2.232

2.083

1.953

1.838

1.736

1.645

1.563

1.488

1.420

1.359

1.302

1.250

1.202

1.157

1.116

1.078

1.042

1.008

0.977

The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00

until

it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is

shown as below table.

BUR [5:0]

20 21 22 23 24 25 26 27

28 29 2A 2B 2C 2D 2E 2F

30 31 32 33 34 35 36 37

38 39 3A 3B 3C 3D 3E 3F

7.576

7.353

7.143

6.944

6.757

6.579

6.410

6.250

6.098

5.952

5.814

5.682

5.556

5.435

5.319

5.208

5.102

5.000

4.902

4.808

4.717

4.630

4.545

4.464

4.386

4.310

4.237

4.167

4.098

4.032

3.968

3.907

BUR[7:6]

3.788

3.676

3.571

3.472

3.378

3.289

3.205

3.125

3.049

2.976

2.907

2.841

2.778

2.717

2.660

2.604

2.551

2.500

2.451

2.404

2.358

2.315

2.273

2.232

2.193

2.155

2.119

2.083

2.049

2.016

1.984

1.953

1.894

1.838

1.786

1.736

1.689

1.645

1.603

1.563

1.524

1.488

1.453

1.420

1.389

1.359

1.330

1.302

1.276

1.250

1.225

1.202

1.179

1.157

1.136

1.116

1.096

1.078

1.059

1.042

1.025

1.008

0.992

0.977

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

0.548

0.539

0.530

0.521

0.512

0.504

0.496

0.488

64 JUNE. 2001 Ver 1.00

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16. INTERRUPTS

GMS81C2112/GMS81C2120

The GMS81C21xx interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). Nine interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 16-2.

The External Interrupts INT0 and INT1 each can be transition-activated (1-to-0 or 0-to -1 transition) by selection IEDS. The flags that actu ally generate these in terrupts are bit INT0F and INT1F in register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated.

The Timer 0 ~ Timer 1 Interrupts are generated by TxIF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register.

The AD converter Interrupt is generated by ADIF whi ch is set by finishing the analog to digital conversion. The Watchdog timer Interrupt is generated by WDTIF which set by a match in Watchdog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer counter register.

The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 21), the interrupt enable

register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. Below table shows the Interrupt priority.

Reset/Interrupt Symbol Priority

Hardware Reset External Interrupt 0 External Interrupt 1

Timer/Counter 0

Timer/Counter 1

ADC Interrupt

Watchdog Timer

Basic Interval Timer

Serial Communication

RESET

INT0

INT1 TIMER0 TIMER1

ADC

WDT

BIT

SCI

1 2 3 4

5 6 7 8

Vector addresses are shown in Figure 8-6 on page 23. Interrupt enable registers are shown in Figure 16-3. These registers are composed of interrupt enab le flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.

R/W

SPIF

INT1IF

WDTIF

R/W T0IF T1IF

R/W

BITIF

R/W R/W

IRQH

IRQL

INT0IF

MSB

R/W R/W

ADIF

MSB LSB

Figure 16-1 Interrupt Request Flag

ADDRESS: 0E4 INITIAL VALUE: 0000 ----

LSB

Timer/Counter 1 interrupt request flag Timer/Counter 0 interrupt request flag

External interrupt 1 request flag External interrupt 0 request flag

ADDRESS: 0E5 INITIAL VALUE: 0000 ----

Serial Communication interrupt request flag Basic Interval imer interrupt request flag Watchdog timer interrupt request flag A/D Conver interrupt request flag

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GMS81C2112/GMS81C2120

Internal bus line

INT0

INT1 Timer 0 Timer 1

A/D Converter

Watchdog Timer

BIT

Communication

Serial

IRQH [0E4

IRQL [0E5

]

INT0IF INT1IF

T0IF T1IF

ADIF

WDTIF

BITIF

SIOIF

[0E2H]

[0E3

IENH

]

Interrupt Enable Register (Higher byte)

Interrupt Enable

IENL

Internal bus line

I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.

Release STOP

To CPU

I-flag

Priority Control

Interrupt Master Enable Flag

Interrupt

Vector

Address

Generator

Figure 16-2 Block Diagram of Interrupt

R/W

T1E

R/W

SPIE

IENH

R/W R/W

INT0E

INT1E

R/W

T0E

MSB

IENL

R/W R/W

ADE

WDTE

R/W

BITE

MSB LSB

Figure 16-3 Interrupt Enable Flag

ADDRESS: 0E2 INITIAL VALUE: 0000 ----

LSB

Timer/Counter 1 interrupt enable flag Timer/Counter 0 interrupt enable flag External interrupt 1 enable flag External interrupt 0 enable flag

ADDRESS: 0E3 INITIAL VALUE: 0000 ----

VALUE

0: Disable 1: Enable

Serial Communication interrupt enable flag Basic Interval imer interrupt enable flag Watchdog timer interrupt enable flag A/D Convert interrupt enable flag

66 JUNE. 2001 Ver 1.00

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16.1 Interrupt Sequence

GMS81C2112/GMS81C2120

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 µs at f

=4.19MHz) after the completion of the current

MAIN

XIN

instruction execution. The interrupt service task is term inated upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.

System clock

Instruction Fetch

Address Bus

SP SP-1

2. Interrupt request flag for the interr upt source accepted is cleared to “0”.

3. The contents of the program counter (return address) and the program status word are saved (pushed) ont o the stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter.

5. The instruction stored at the entry address of the interrupt service program is executed.

SP-2 V.H. New PC

V.L.

Data Bus

Internal Read

Internal Write

V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.

Not used

PCH PCL

Interrupt Processing Step Interrupt Service Task

Figure 16-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

Basic Interval Timer Vector Table Address

0FFE6 0FFE7

Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.

012 0E3

H H

0E312 0E313

Entry Address

0E 2E

H H

A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced.

PSW ADL OP codeADH

V.L.

When nested interrupt service is required, the I -flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers ar e not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory

JUNE. 2001 Ver 1.00 67

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GMS81C2112/GMS81C2120

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

area for saving registers. The following method is used to save/restore the general-

purpose registers. Example: Register save using push and pop instructions

INTxx: PUSH A

PUSH X PUSH Y

interrupt processing

POP Y POP X POP A RETI

;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.

;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN

General-purpose register save/restore using push and pop instructions;

main task

acceptance of interrupt

interrupt service task

saving registers

16.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in Figure 16-5.

interrupt return

restoring registers

Figure 16-5 Execution of BRK/TCALL0

68 JUNE. 2001 Ver 1.00

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16.3 Multi Interrupt

GMS81C2112/GMS81C2120

If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced.

Main Program service

Occur TIMER1 interrupt

Occur INT0

TIMER 1 service

enable INT0 disable other

enable INT0 enable other

INT0 service

However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interru pt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.

Example:

During Timer1 interrupt is in progress, INT0 in-

terrupt serviced without any suspen d.

TIMER1: PUSH A

PUSH X PUSH Y

LDM IENH,#80H ; LDM IENL,#0 ; EI ;

: : :

LDM IENH,#0F0H ; LDM IENL,#0F0H

POP Y POP X POP A RETI

Enable INT0 only Disable other Enable Interrupt

Enable all interrupts

In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.

Figure 16-6 Execution of Multi Interrupt

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GMS81C2112/GMS81C2120

16.4 External Interrupt

The external interrupt on INT0 and INT1 pins are edge triggered depending o n the edge select ion register IEDS (address 0F8

) as shown in Figure 16-7.

The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.

INT1 pin

INT0 pin

2 2

IEDS

[0E6H]

Figure 16-7 External Interrupt Block Diagram

INT1IF

INT1 INTERRUPT

INT0IF

INT0 INTERRUPT

Edge selection Register

INT0 and INT1 are mu ltiplexed with general I/O ports (R00 and R01). To use as an external interrupt pin, the bit of R4 port mode regis ter R0FUNC should be set to “1” correspondingly.

Example:

To use as an INT0 and INT1

: :

;

**** Set port as an input port R00,R01

LDM R0IO,#1111_1100B ;

;

**** Set port as an inter rupt port

LDM R0FUNC,#0000_0011B ;

;

**** Set Falling-edge Detection

LDM IEDS,#0000_0101B : : :

Response Time

The INT0 and INT1 edge are latched into INT0IF and INT1IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the reques ted service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.

Figure 16-8shows interrupt response timings.

8 f

XIN

Interrupt processing

Interrupt routine

Interrupt goes active

max. 12 f

Interrupt latched

XIN

Figure 16-8 Interrupt Response Timing Diagram

70 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

R0FUNC

IEDS

WWWWWWWW

INT1

---

---IED0H

Edge selection register

00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)

BTCL

-IED0LIED1LIED1H

EC0BUZO

R/W R/W R/W R/W

BTCL

INT1

INT0

LSBMSB

INT0

Figure 16-9 R0FUNC and IEDS Registers

ADDRESS: 0F4 INITIAL VALUE: ---- 0000

0: R00 1: INT0

0: R01 1: INT1

0: R02 1: EC0

0: R03 1: BUZO

ADDRESS: 0E6 INITIAL VALUE: ---- 0000

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GMS81C2112/GMS81C2120

17. Power Saving Mode

For applications where power consumption is a critical factor, device provides four kinds of power saving functions, STOP mode, Sub-active mode and Wake-up Timer mode (Stand-by mode, Watc h mode). Table 17-1 shows the status of each Power Saving Mode.

Wake-up Timer

Peripheral STOP Mode

RAM Retain Retain

Control Registers Retain Retain

I/O Ports Retain Retain

CPU Stop Stop

Timer0 Stop Operation

Oscillation Stop Oscillation

Prescaler Stop

Entering Condition

[WAKEUP]

Table 17-1 Power Saving Mode

Mode

Stand-by Mode

2048 only

The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR. We shows the release sources from each Power Saving Mode

Wake-up Timer

Release Source STOP Mode

RESET O O

RCWDT O O

EXT.INT0

EXT.INT1

Timer0 X O

Table 17-2 Release Sources from Power Saving Mode

Mode

Stand-by Mode

72 JUNE. 2001 Ver 1.00

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17.1 Operating Mode

fXI : Main clock frequency

GMS81C2112/GMS81C2120

SYS

: fXI,f

÷4

8,f

cpu : system clock tmr : timer0 clock peri : peripheral clock

CKCTLR = CKCTLR[6:5]

STANDBY Mode

: oscillation

f cpu : stop

tmr : ps11(f peri : stop

CKCTLR[10]

STOP

)

TIMER0 EXT_INT RESET RC_WDT

ACTIVE Mode

: oscillation

f cpu : f

tmr : f peri : f

CKCTLR[00]

STOP

STOP Mode

SYS

EXT_INT RESET RC_WDT

: stop

f cpu : stop

tmr : stop peri : stop

System Clock Mode Register

SCMR

CS[1:0] Clock selection enable bits

- - - CS1 CS0 - - -

00 : fXI 10 : fXI ÷ 8

01 : f

÷ 4 11 : fXI ÷ 32

ADDRESS : FAH RESET VALUE : ---00---

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GMS81C2112/GMS81C2120

IEXX

STOP

INSTRUCTION

STOP Mode

Interrupt Request

STOP Mode Release

I-FLAG

Interrupt Service Routine

INSTRUCTION

Master Interrupt

Enable Bit PSW[2]

Corresponding Inte rr upt

Enable Bit (IENH, IENL)

17.2 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.

• The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode.

The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to “0”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)

In the Stop mode of operation, V imize power consumption. Care must be taken, however, to ensure that V invoked, and that V

is not reduced before the Stop mode is

is restored to its normal op erating

level, before the Stop mode is terminated.

can be reduced to min-

Release the STOP mode

The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Contro l registers but do es not change the on-chip RAM. External interrupts allow both on-chip RAM and Co ntrol regi sters to reta in their v alues.

If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 17-1)

When exit from Stop mode by external interrupt, enough oscillation stabilization t ime is required to normal o peration. Figure 17-2 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00

until FFH. The count

overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.

By reset, exit from Stop mode is shown in Figure .

The reset should not be activated before V

its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize.

Note:

After STOP instruction, at least two or more NOP in-

struction should be writ ten

Ex) LDM CKCTLR ,#0 00 0_1 110 B

STOP NOP NOP

In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determ ined by the hard ware operatio n of the STOP feature. This point should be little current flows when the input level is s table at the power voltage level (V er than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the

DD/VSS

output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means.

); however, when the input lev el get s high -

is restored to

Figure 17-1 STOP Releasing Flow by Interrupts

74 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

Oscillator

pin)

Internal Clock

External Interrupt

BIT Counter

STOP Instruction Executed

n+1 n+2 n+3

Normal Operation Stop Operation Normal Operation

Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms.

Clear

Figure 17-2 STOP Mode Release Timing by External Interrupt

tST > 20ms by software

STOP Mode

Oscillator

(XI pin)

Internal

Clock

RESETB

Internal

RESETB

STOP Instruction Execution

Time can not be control by software

Figure 17-3 Timing of STOP Mode Release by RESET

17.3 Wake-up Timer Mode

In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler(onl y 2048 divi ded ratio) and Timer0, all functions are stopped, but the on-c hip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers.

The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to “1”. (This register should be written by byte operation. If this register is set by bit ma nipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)

Note:

After STOP instruction, at least two or more NOP in-

Stabilization Time

= 64mS @4MHz

struction should be written

Ex) LDM TDR0,#0FFH

LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP

In addition, the clock source of timer0 should be selected to 2048 divided ratio. Otherwise, the wake-u p function can not work. And the timer0 can be operated as 16-bit timer with timer1. (refer to timer function)The period of wakeup function is varied by setting the timer data register 0, TDR0.

JUNE. 2001 Ver 1.00 75

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GMS81C2112/GMS81C2120

Release the Wake-up Timer mode

The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values.

If I-flag = 1, the normal in terrupt response takes place. I f I-

Oscillator

(XI pin)

CPU

Clock

Interrupt Request

STOP Instruction Execution

Normal Operation

Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt

Wake-up Timer Mode ( stop the CPU clock )

17.4 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Wat chdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers.

The Internal RC-Oscillated Watchdog Timer mode i s activated by execution of STOP instruction afte r setting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be u ndesired operation)

Note:

Caution: After STOP instruction, at le ast two or more

NOP instruction should be written

Ex)

The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM

LDM WDTR LDM CKCTLR STOP

NOP NOP

,#1111_1111B

,#0010_1110B

flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 17-1)

When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 17-4.

Normal Operation Do not need Stabilization Time

and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In

this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 17-5) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 17-6)

If I-flag = 0, the chip will resume execution starting wi th the instruction following the STOP instruction. It wil l not vector to interrupt service routine.(refer to Figure 17-1)

When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to norma l operation. Figure 17-5 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00

until FFH. The

count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.

By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 17-6.

76 JUNE. 2001 Ver 1.00

Page 83

Oscillator

(XI pin)

Internal

RC Clock

Internal

Clock

External Interrupt

( or WDT Interrupt )

BIT

Counter

N-2

N-1

STOP Instruction Execution

N+1N N+2

GMS81C2112/GMS81C2120

Clear Basic Interval Timer

00 01 FE FF 00 00

Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt

Oscillator

(XI pin)

Internal

RC Clock

Internal

Clock

RESET

RESET by WDT

Internal

RESET

Normal Operation

RCWDT Mode Normal Operation

RCWDT Mode

STOP Instruction Execution

Time can not be control by software

Stabilization Time

> 20mS

Stabilization Time

= 64mS @4MHz

Figure 17-6 Internal RCWDT Mode Releasing by RESET

17.5 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.

Note:

In the STOP operation, the power dissipation asso-

ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. Th is point sh ould be little c urrent flows when the input level is stable at the power voltage level (V

); however, when the input level becomes higher

DD/VSS

JUNE. 2001 Ver 1.00 77

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GMS81C2112/GMS81C2120

than the power voltage level (by approximately 0.3V), a cu rrent begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a curr ent flow across th e ports input transistor, requiring it to fix the level by pull-up or other means.

It should be set properly in order that current flow through port doesn't exist.

First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship wi th external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current does n’t flow.

INPUT PIN

internal pull-up

GND

Weak pull-up current flows

OPEN

But input voltage lev el shou ld be V

or VDD. Be careful

that if unspecified voltage, i.e. if unfirmed voltage level (not V

or VDD) is applied to input pin, there can be little

current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input m ode, then set to

output mode considering th ere is no current flow. Settin g to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-u p resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.

INPUT PIN

OPEN

Very weak current flows

i=0

GND

When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.

Figure 17-7 Application Example of Unused Input Port

OUTPUT PIN

OFF

GND

In the left case, much current flows from port to GND.

OFF

Figure 17-8 Application Example of Unused Output Port

OPEN

OUTPUT PIN

OFF

In the left case, Tr. base current flows from port to GND. To avoid power consumpt ion, there should be low output to the port .

OFF

GND

i=0

GND

78 JUNE. 2001 Ver 1.00

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18. OSCILLATOR CIRCUIT

OUT

GMS81C2112/GMS81C2120

The GMS81C21xx has an oscillation circuits internally. X

and X

are input and output for main frequency re-

OUT

spectively, inverting ampl ifier which can be configured for

Recommend

Crystal Oscillator Ceramic Resonator

Crystal or Ceramic Oscillator

Open

External Clock

External Oscillator RC Oscillator

OUT

4.19MHz

C1,C2 = 20pF C1,C2 = 30pF

being used as an on-chip oscillator , as shown in Figure 18-

OUT

EXT

For selection R value, Refer to AC Characteristics

(mask option)

Figure 18-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

In addition, see Figure 18-2 for the layout of the crystal.

Note:

Minimize the wiring leng th. Do not allow the wiring to intersect with other signa l cond uctors . Do not all ow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of

. Do not ground it to any g round pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 18-2 Layout of Oscillator PCB circuit

JUNE. 2001 Ver 1.00 79

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GMS81C2112/GMS81C2120

7036P

10uF

10k

Ω

to the RESET pin

19. RESET

The GMS81C21xx have two types of reset generatio n procedures; one is an external reset input, the other is a watch-

dog timer reset. Table 19-1 shows on-chip hardwar e initialization by reset action.

On-chip Hardware Initial Value On-chip Hardware Initial Value

Program counter (PC)

(FFFF

Peripheral clock Off

) - (FFFEH)

RAM page register (RPR) 0 Watchdog timer Disable G-flag (G) 0 Control registers Refer to Table 8-1 on page 27 Operation mode Main-frequency clock Power fail detector Disable

Table 19-1 Initializing Internal Status by Reset Action

19.1 External Reset Input

The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. A fter reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 19-2.

Internal RAM is not affected by reset. When V

is turned

on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it.

A connection for simple p ower-on-reset is shown in Figure 19-1.

When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFE

- FFFFH.

Oscillator

pin)

RESET

ADDRESS

BUS

DATA

BUS

Stabilization Time

= 62.5mS at 4.19MHz

Figure 19-2 Timing Diagram after RESET

19.2 Watchdog Timer Reset

Refer to “11. WATCHDOG TIMER” on page 39.

Figure 19-1 Simple Power-on-Reset Circuit

1 2 3 4 5 6 7

~ ~

RESET Process Step

= x 256

÷1024

MAIN

FFFE FFFF

FE?ADL

ADH

Start

MAIN PROGRAM

80 JUNE. 2001 Ver 1.00

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20. POWER FAIL PROCESSOR

GMS81C2112/GMS81C2120

The GMS81C21xx has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the po wer fail detect circuitry. Whenever V

falls close to or below power fail

voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to “7.4 DC Electrical Characteristics for Standard Pins(5V)” on page 14.

In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Theref ore, af ter final development of user program, this function may be experimented or evaluated.

Note:

User can select po wer fail v olt age le vel ac cordi ng to PFD0, PFD1 bit of CONFIG register(703F (GMS87C21xx) but

must select

the power fail v oltage leve l to define PFD option of “Mask Order & Verification Sheet” at the mask chip(GMS81C21xx). Because the power fail voltage level of mask chip (GMS81C21xx) is determined according to mask option.

) at the OTP

Note:

If power fail voltage is selected to 3.0V on 3V oper-

ation, MCU is freezed at all the times.

Power FailFunction OTP MASK

Enable/Disable PFDIS flag PFDIS flag Level Selection

PFS0 bit PFS1 bit

Mask option

Table 20-1 Power fail processor

PFDR

76543210

R/W R/W R/W

PFDM

PFDIS

PFS

Figure 20-1 Power Fail Voltage Detector Register

ADDRESS: 0EF INITIAL VALUE: ---- -100

Power Fail Status

0: Normal operate 1: Set to “1” if power fail is detected

Operation Mode

0 : Normal operation regardless of powe r fail 1 : MCU will be reset by power fail detection

Disable Flag

0: Power fail detection enable 1: Power fail detection disable

JUNE. 2001 Ver 1.00 81

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GMS81C2112/GMS81C2120

RESET VECTOR

Internal RESET

PFS =1

RAM CLEAR

INITIALIZE RAM DATA

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

FUNTION

EXECUTION

YES

PFS = 0

Skip the

initial routine

Figure 20-2 Example S/W of RESET flow by Power fail

64mS

MAX

PFD

MIN

PFD

When PFR = 1

Internal RESET

t <64mS

64mS

Figure 20-3 Power Fail Processor Situations

MAX

PFD

MIN

PFD

MAX

PFD

MIN

PFD

82 JUNE. 2001 Ver 1.00

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21. OTP PROGRAMMING

21.1 DEVICE CONFIGURATION AREA

The Device Configuration Area can be programm ed or left unprogrammed to select device configuration such as security bit. Sixteen memory locatio ns (7030

~ 703FH) are designated

7030

DEVICE

CONFIGURATION

AREA

703F

GMS81C2112/GMS81C2120

as Customer ID recording locat ions where the user can store check-sum or other customer iden tification n umbers. This area is not accessible during normal execution but is readable and writable during program / verify.

ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID

CONFIG

7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 703A 703B 703C 703D 703E

703F

CONFIG

76543210

PFS0PFS1

LOCK

RCO

ADDRESS: 703F INITIAL VALUE: --00 -0-0

External RC OSC Selection

0: Crystal or Resonator Oscillator 1: External RC Oscillator

Code Protect

0 : Allow Code Read Out 1 : Lock Code Read Out

PFD Level Selection

00: PFD = 2.7V 01: PFD = 2.7V 10: PFD = 3.0V 11: PFD = 2.4V

Figure 21-1 Device Configuration Area

JUNE. 2001 Ver 1.00 83

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GMS81C2112/GMS81C2120

42PDIP

CTL3

CTL2

CTL1

CTL0

VPP

EPROM Enable

A_D0

A_D1

A_D2

A_D3

A_D4

A_D5

A_D6

A_D7

RA R53 R54 R55 R56 R57

RESET

V R60

R61 R62 R63 R64 R65 R66 R67

DD DD

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00

Figure 21-2 Pin Assignment t

User Mode EPROM MODE

Pin No.

Pin Name Pin Name Description

2 R53 CTL3 Read/Write Control 3 R54 CTL2 A ddress /Data Control 4 R55 CTL1 Write Control 1 5 R56 CTL0 Write Control 0 7 RESETB VPP Programming Power (0V, 12.75V) 8 XI EPROM Enable High Active, Latch Address in falling edge 9 XO NC No connection

10 VSS VSS

Connect to VSS

12 R60 A_D0 13 R61 A_D1 A9 A1 D1 14 R62 A_D2 A10 A2 D2

Data Input/Output

15 R63 A_D3 A11 A3 D3 16 R64 A_D4 17 R65 A_D5 A13 A5 D5 18 R66 A_D6 A14 A6 D6

Data Input/Output

19 R67 A_D7 A15 A7 D7 21 VDD VDD

Connect to VDD

(0V)

Address Input

(6.0V)

A8 A0 D0

A12 A4 D4

Table 21-1 Pin Description in EPROM Mode (GMS81C2120)

84 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

 

EPROM Enable

VPP

CTL0/1

CTL2

CTL3

A_D7~ A_D0

VDD

VDDS

DD1H

VPPS

SET1

HLD1

IHP

VPPR

CD1

High 8bit Address Input

DLY1

CD1

DD1H

Low 8bit Address Input

HLD2

DATA IN

Write Mode

DD1H

DLY2

DATA

Verify

CD1

OUT

CD1

Low 8bit Address Input

Figure 21-3 Timing Diagram in Program (Write & Verify) Mode

LA DATA IN

Write Mode

DATA

OUT

Verify

JUNE. 2001 Ver 1.00 85

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GMS81C2112/GMS81C2120

EPROM Enable

VPP

CTL0/1

CTL2

CTL3

A_D7~ A_D0

VDD

VDDS

DD2H

VPPS

SET1

VPPR

After input a high address,

output data following low address input

HLD1

CD1

High 8bit Address Input

DLY1

IHP

CD2

DD2H

Low 8bit Address Input

DD2H

CD1

DATA

DATA Output

HLD2

Low 8bit Address Input

DLY2

CD2

LA DATA

DATA Output

Anothe high address step

High 8bit Address Input

Low 8bit Address Input

DATA

DATA Output

Figure 21-4 Timing Diagram in READ Mode

Parameter Symbol MIN TYP MAX Unit

Programming Supply Current Supply Current in EPROM Mode VPP Level during Programming VDD Level in Program Mode VDD Level in Read Mode CTL3~0 High Level in EPROM Mode CTL3~0 Low Level in EPROM Mode A_D7~A_D0 High Level in EPROM Mode A_D7~A_D0 Low Level in EPROM Mode VDD Saturation Time VPP Setup Time VPP Saturation Time EPROM Enable Setup Time after Data Input EPROM Enable Hold Time after T

SET1

Table 21-2 AC/DC Requirements for Program/Read Mode

VPP

VDDP

DD1H

DD2H

V V V

VDDS

VPPR

VPPS

SET1

HLD1

IHP

IHC

ILC

IHAD

ILAD

--50mA

--20mA

11.5 12.0 12.5 V

566.5V

-2.7-V

0.8V

0.9V

--V

0.2V

--V

0.1V

1--mS

--1mS 1--mS

200 nS 500 nS

86 JUNE. 2001 Ver 1.00

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GMS81C2112/GMS81C2120

EPROM Enable Delay Time after T

HLD1

EPROM Enable Hold Time in Write Mode EPROM Enable Delay Time after T

HLD2

CTL2,1 Setup Time after Low Address input and Data input CTL1 Setup Time before Data output in Read and Verify Mode

Table 21-2 AC/DC Requirements for Program/Read Mode

START

Set VDD=V

Set VPP=V

Verify blank

First Address Location

DD1H

IHP

PASS

Report

Programming failure

FAIL

DLY1

HLD2

DLY2

CD1

CD2

Verify of all address

VDD=6V & 2.7V

Programming OK

200 nS 100 nS 200 nS 100 nS 100 nS

Report

Verify failure

FAIL

Verify

PASS

Report

Next address location

Apply 3x program cycle

N=1

EPROM Write

100uS program time

Verify

PASS

Last address

YES

N=N+1

YES

FAIL



Figure 21-5 Programming Flow Chart

VPP=0V

VDD=0V

END

JUNE. 2001 Ver 1.00 87

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GMS81C2112/GMS81C2120

88 JUNE. 2001 Ver 1.00

Page 95

APPENDIX

Page 96

A. CONTROL REGISTER LIST

GMS800 Series

Address Register Name Symbol R/W

00C0 R0 port data register R0 R/W Undefined 34 00C1 R0 port I/O direction register R0IO W 0 0 0 0 0 0 0 0 34 00C4 R2 port data register R2 R/W Undefined 35 00C5 R2 port I/O direction register R2IO W 0 0 0 0 0 0 0 0 35 00C6 R3 port data register R3 R/W Undefined 35

00C7 R3 port I/O direction register R3IO W - - - 0 0 0 0 0 35 00CA R5 port data register R5 R/W Undefined 35 00CB R5 port I/O direction register R5IO W 0 0 0 0 0 - - - 35 00CC R6 port data register R6 R/W Undefined 35 00CD R6 port I/O direction register R6IO W 0 0 0 0 0 0 0 0 35

00D0 Timer mode register 0 TM0 R/W - -000000 44

Timer 0 register T0 R 00000000 48

00D1

00D2 Timer mode register 1 TM1 R/W 00000000 44

00D3

00D4

00D5 PWM 1 High register PWM1HR W - - - - 0 0 0 0 54 00DE Buzzer driver register BUR W 1 1 1 1 1 1 1 1 63

00E0 Serial I/O mode register SIOM R/W 0 0 0 0 0 0 0 1 60

00E1 Serial I/O data register SIOR R/W Undefined 60

00E2 Interrupt enable register high IENH R/W 0 0 0 0 - - - - 66

00E3 Interrupt enable register low IENL R/W 0 0 0 0 - - - - 66

00E4 Interrupt request flag register high IRQH R/W 0 0 0 0 - - - - 65

00E5 Interrupt request flag register low IRQL R/W 0 0 0 0 - - - - 65

00E6 External interrupt edge selection register IEDS R/W - - - - 0 0 0 0 71 00EA A/D converter mode register ADCM R/W - 0 0 0 0 0 0 1 56 00EB A/D converter data register ADCR R Undefined 56

00EC

00ED

00EF Power fail detection register PFDR R/W - - - - - 1 0 0 81

Timer 0 data register TDR0 W 1 1 1 1 1 1 1 1 44 Capture 0 data register CDR0 R 0 0 0 0 0 0 0 0 50

Timer 1 data register TDR1 W 1 1 1 1 1 1 1 1 44 PWM 1 period register T1PPR W 1 1 1 1 1 1 1 1 54 Timer 1 register T1 R 00000000 48 PWM 1 duty register T1PDR R/W 0 0 0 0 0 0 0 0 54 Capture 1 data register CDR1 R 0 0 0 0 0 0 0 0 50

Basic interval timer mode register BITR R 0 0 0 0 0 0 0 0 38 Clock contr ol register CKCTLR W - 0 0 1 0 1 1 1 38 Watchdog Timer Register WDTR R 0 0 0 0 0 0 0 0 40 Watchdog Timer Register WDTR W 0 1 1 1 1 1 1 1 40

Initial Value

76543210

Page

JUNE. 2001 i

Page 97

GMS800 Series

Address Register Name Symbol R/W

00F4 R0 Function selection register R0FUNC W - - - - 0 0 0 0 34

00F6 R5 Function selection register R5FUNC W - 0 - - - - - - 35

00F7 R6 Function selection register R6FUNC W 0 0 0 0 0 0 0 0 35

00F9 R5 N-MOS open drain selection register R5MPDR W 0 0 0 0 0 - - - 35

00FA System clock mode register SCMR R/W - - - 0 0 - - - 73

00FB RA port data register RA R Undefined 34

Initial Value

76543210

Page

ii JUNE. 2001

Page 98

B. INSTRUCTION

B.1 Terminology List

Terminology Description

A Accumulator X X - register

Y Y - register PSW Program Status Word #imm 8-bit Immediate data

dp Direct Page Offset Address

!abs Absolute Address

[ ] Indirect expression { } Register Indirect expression

{ }+ Register Indirect expression, after that, Register auto-increment

.bit Bit Position

A.bit Bit Position of Accumulator

dp.bit Bit Position of Direct Page Memory

M.bit

rel Relative Addressing Data

upage

n Table CALL Number (0~15) + Addition

− ×

/ Division

( ) Contents Expression

∧

∨

⊕

~NOT

← →

↔

= Equal

≠

Bit Position of Memory Data (000

~0FFFH)

U-page (0FF00H~0FFFFH) Offset Address

Bit Position

Subtraction Multiplication

AND OR Exclusive OR

Assignment / Transfer / Shift Left Shift Right Exchange

Not Equal

GMS800 Series

Upper Nibble Expression in Opcode

JUNE. 2001 iii

Page 99

GMS800 Series

B.2 Instruction Map

0000000000010100010020001103001000400101050011006001110701000080100109010100A010110B011000C011010D011100E01111

LOW

HIGH

000 -

001 CLRC

010 CLRG

011 DI

100 CLRV

101 SETC

110 SETG

111 EI

LOW

HIGH

000

SET1

dp.bit

1000010100011110010121001113101001410101151011016101111711000181100119110101A110111B111001C111011D111101E11111

BPL

CLR1

rel

dp.bit

BBS

A.bit,rel

BBC

A.bit,rel

BBS

dp.bit,rel

BBC

dp.bit,rel

ADC

SBC

AND

EOR

LDA

LDM

ADC

{X}

ADCdpADC

dp+X

SBCdpSBC

dp+X

CMPdpCMP

dp+X

ANDdpAND

dp+X

EORdpEOR

dp+X

LDAdpLDA

dp+X

STAdpSTA

dp+X

ADC

!abs+Y

ADC

[dp+X]

#imm

CMP #imm

#immORdpORdp+XOR!abs

#imm

dp,#imm

ADC !abs

SBC !abs

CMP

!abs

AND !abs

EOR

!abs

LDA !abs

STA !abs

ADC

[dp]+Y

ASLAASLdpTCALL0SETA1

ROLAROLdpTCALL2CLRA1

LSRALSRdpTCALL4NOT1

RORARORdpTCALL6OR1

INCAINCdpTCALL8AND1

DECADECdpTCALL10EOR1

LDYdpTCALL12LDC

TXA

STYdpTCALL14STC

TAX

ASL

dp+X

TCALL1JMP

!abs

.bit

M.bit

OR1B

AND1B

EOR1B

LDCB

M.bit

!abs

BITdpPOPAPUSH

COMdpPOPXPUSHXBRA

TSTdpPOPYPUSHYPCALL

CMPXdpPOP

CMPYdpCBNE

DBNEdpXMA

LDXdpLDX

STXdpSTX

BIT

ADDWdpLDX

!abs

PSW

dp+X

dp+Y

PUSH

TXSP

TSPX

#imm

BRK

Upage

PSW

RET

INC

DEC

XCN DAS

XAX STOP

JMP

[!abs]

rel

001

010

011

100

101

110

111

BVC

rel

BCC

rel

BNE

rel

BMI

rel

BVS

rel

BCS

rel

BEQ

rel

SBC

AND

EOR

LDA

STA

SBC

[dp]+Y

CMP

[dp]+Y

AND

[dp]+Y

EOR

[dp]+Y

LDA

[dp]+Y

STA

[dp]+Y

{X}

!abs+Y

[dp+X]

CMP

AND

EOR

LDA

STA

CMP

[dp+X]

{X}

!abs+Y

{X}OR!abs+YOR[dp+X]OR[dp]+Y

AND

{X}

!abs+Y

EOR

{X}

!abs+Y

LDA

{X}

!abs+Y

STA

{X}

!abs+Y

ROL

!abs

LSR !abs

ROR

!abs

INC !abs

DEC

!abs

LDY !abs

STY !abs

ROL

TCALL3CALL

dp+X

LSR

TCALL

dp+X

ROR dp+X

INC

dp+X

DEC

dp+X

LDY

dp+X

STY

dp+X

TCALL7DBNEYCMPX

TCALL

TCALL11XMA

TCALL13LDA

TCALL15STA

TEST

!abs

TCLR1

MUL

!abs

CMPY

DIV

!abs

XMAdpDECWdpDEC

{X}

LDX

{X}+

!abs

STX

{X}+

!abs

SUBWdpLDY

CMPWdpCMPX

#imm

LDYAdpCMPY

#imm

INCWdpINC

STYA

CBNE

XAY DAA

XYX NOP

JMP

[dp]

CALL

[dp]

RETI

TAY

TYA

iv JUNE. 2001

Page 100

B.3 Instruction Set

Arithmetic / Logic Operation

GMS800 Series

No. Mnemonic

1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A ← ( A ) + ( M ) + C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC { X } 14 1 3

9 AND #imm 84 2 2 Logical AND 10 AND dp 85 2 3 A ← ( A ) ∧ ( M ) 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND { X } 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP { X } 54 1 3 29 CMPX #imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 ( X ) - ( M ) 31 CMPX !abs 7C 3 4 32 CMPY #imm 7E 2 2 Compare Y contents with memory contents 33 CMPY dp 8C 2 3 ( Y ) - ( M ) 34 CMPY !abs 9C 3 4 35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) 36 DAA DF 1 3 Decimal adjust for addition 37 DAS CF 1 3 Decimal adjust for subtraction 38 DEC A A8 1 2 Decrement 39 DEC dp A9 2 4 M ← ( M ) - 1 40 DEC dp + X B9 2 5 41 DEC !abs B8 3 5 42 DEC X AF 1 2 43 DEC Y BE 1 2

Code

ByteNoCycle

Operation

Arithmetic shift left

76543210

←

Compare accumulator contents with memory contents ( A ) - ( M )

“0”

←

←←←←←←←←

Flag

NVGBHIZC

NV--H-ZC

N-----Z-

N-----ZC

N-----ZN-----ZC N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z-

JUNE. 2001 v

Datasheet GMS87C2120Q, GMS87C2120K, GMS87C2120, GMS81C2112Q, GMS81C2112K Datasheet (HYNIX)

Specifications and Main Features

Frequently Asked Questions

User Manual

1. OVERVIEW

1.1 Description

1.2 Features

1.3 Development Tools

1.4 Ordering Information

2. BLOCK DIAGRAM

3. PIN ASSIGNMENT

4. PACKAGE DIAGRAM

5. PIN FUNCTION

6. PORT STRUCTURES

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

DC Electrical Characteristics for Standard Pins(5V)

7.5 DC Electrical Characteristics for High-Voltage Pins

7.6 AC Characteristics

7.7 AC Characteristics

7.8 Typical Characteristics

8. MEMORY ORGANIZATION

8.1 Registers

8.2 Program Memory

8.3 Data Memory

8.4 Addressing Mode

9. I/O PORTS

10. BASIC INTERVAL TIMER

11. WATCHDOG TIMER

12. TIMER/EVENT COUNTER

12.1 8-bit Timer / Counter Mode

12.2 16-bit Timer / Counter Mode

12.3 8-bit Compare Output (16-bit)

12.4 8-bit Capture Mode

12.5 16-bit Capture Mode

12.6 PWM Mode

13. ANALOG DIGITAL CONVERTER

14. SERIAL PERIPHERAL INTERFACE

14.1 Transmission/Receiving Timing

14.2 The method of Serial I/O

14.3 The Method to Test Correct Transmission

15. BUZZER FUNCTION

16. INTERRUPTS

16.1 Interrupt Sequence

16.3 Multi Interrupt

16.4 External Interrupt

17. Power Saving Mode

17.1 Operating Mode

17.2 Stop Mode

17.3 Wake-up Timer Mode

17.4 Internal RC-Oscillated Watchdog Timer Mode

17.5 Minimizing Current Consumption

18. OSCILLATOR CIRCUIT

19. RESET

19.1 External Reset Input

19.2 Watchdog Timer Reset

20. POWER FAIL PROCESSOR

21. OTP PROGRAMMING

21.1 DEVICE CONFIGURATION AREA

A. CONTROL REGISTER LIST

B. INSTRUCTION

B.1 Terminology List

B.2 Instruction Map

B.3 Instruction Set