Datasheet GMS87C2020Q, GMS87C2020LQ, GMS87C2020K, GMS81C2020K, GMS81C2012Q Datasheet (HYNIX)

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Page 1

HYNIX SEMICONDUCTOR

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2012 GMS81C2020

User’s Manual

JUNE. 2001 Ver 1.00

Page 2

HYNIX SEMICONDUCTOR

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2012 GMS81C2020

User’s Manual (Ver. 1.00)

Page 3

Version 1.00 Published by

MCU Application Team



Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory.

HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, HYNIX Semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

Page 4

Page 5

Table of Contents

1. OVERVIEW............................................1

Description .........................................................1

Features ............................... ..............................1

Development Tools ............................................2

Ordering Information



2. BLOCK DIAGRAM.................................3

3. PIN ASSIGNMENT ................................4

4. PACKAGE DIAGRAM............................6

5. PIN FUNCTION......................................8

6. PORT STRUCTURES..........................11

7. ELECTRICAL CHARACTERISTICS....14

Absolute Maximum Ratings .............................14

Recommended Operating Conditions ..............14

A/D Converter Characteristics .........................14

DC Electrical Characteristics for Standard Pins(5V) 15

DC Electrical Characteristics for High-Voltage Pins 16

AC Characteristics ...........................................17

AC Characteristics ...........................................18

Typical Characteristics .....................................19

8. MEMORY ORGANIZATION.................21

Registers ....................... ...................................21

Program Memory ....................... ....... ...............24

Data Memory ...................................................27

Addressing Mode .............................................31

9. I/O PORTS...........................................35

10. BASIC INTERVAL TIMER..................39

11. WATCHDOG TIMER..........................41

12. TIMER/EVENT COUNTER................44

8-bit Timer / Counter Mode ..............................46

16-bit Timer / Counter Mode ............................50

8-bit Compare Output (16-bit) ..........................51

8-bit Capture Mode ......................................... 51

16-bit Capture Mode ....................................... 54

PWM Mode ..................................................... 55

13. ANALOG DIGITAL CONVERTER.....58

14. SERIAL PERIPHERAL INTERFACE.61

Transmission/Recei vi ng Timi ng ........... ........... 63

The method of Serial I/O ................................. 64

The Method to Test Correct Transmission ...... 64

15. BUZZER FUNCTION.........................65

16. INTERRUPTS....................................67

Interrupt Sequence .......................................... 69

Multi Interrupt .................................................. 71

External Interrupt ............................................. 72

17. Power Saving Mode...........................74

Operating Mode .............................................. 75

Stop Mode ....................................................... 76

Wake-up Timer Mode ...................................... 77

Internal RC-Oscillated Watchdog Timer Mode 78

Minimizing Current Consumption .................... 79

18. OSCILLATOR CIRCUIT.....................81

19. RESET...............................................82

External Reset Input ........................................ 82

Watchdog Timer Reset ................................... 82

20. POWER FAIL PROCESSOR.............83

21. OTP PROGRAMMING.......................85

DEVICE CONFIGURATION AREA ...... ...... ..... 85

A. CONTROL REGISTER LIST..................i

B. INSTRUCTION.............. ..... .... ..... ......... iii

Terminology List ................................................iii

Instruction Map ..................................................iv

Instruction Set ....................................................v

C. MASK ORDER SHEET........................xi

Page 6

Page 7

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 1

GMS81C2012/GMS81C2020

CMOS Single-Chip 8-Bit Microcontroller

with A/D Converter & VFD Driver

1. OVERVIEW

1.1 Description

The GMS81C2012 and GMS81C2020 are advanced CMOS 8-b it micro contr oller with 12 K/20K bytes of ROM. Thes e are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 12K/20K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, Serial Peripheral Interface, on-chip oscillator and clo ck circuitry. They also come with h igh voltage I/O p ins that can dir ectl y drive a VFD (Vacuum Fluores cent Displ ay). I n addit ion, t he GMS81C20 12 and GMS 81C202 0 suppor t po wer saving modes to reduce power consumption.

1.2 Features

• 20K/12K bytes ROM(EPROM)

• 448 Bytes of On-Chip Data RAM (Including STACK Area)

• Minimum Instruction Execution time:

- 1uS at 4MHz (2cycle NOP Instruction)

• One 8-bit Basic Interval Timer

• One 7-bit Watch Dog Timer

• Two 8-bit Timer/Counters

• 10-bit High Speed PWM Output

• One 8-bit Serial Peripheral Interface

• Two External Interrupt Ports

• One Programmable 6-bit Buzzer Driving Port

• 60 I/O Lines

- 56 Programmable I/O pins (Included 30 high-voltage pins Max. 40V)

- Three Input Only pins: 1 high-voltage pin

- One Output Only pin

• Eight Interrupt Sources

- Two External Sources (INT0, INT1)

- Two Timer/Counter Sources (Timer0, Timer1)

- Four Functional Sources (SPI,ADC,WDT,BIT)

• 12-Channel 8-bit On-Chip Analog to Digital Converter

• Oscillator:

- Crystal

- Ceramic Resonator

- External R Oscillator

• Low Power Dissipation Modes

- STOP mode

- Wake-up Timer Mode

- Standby Mode

- Watch Mode

- Sub-active Mode

• Operating Voltage: 2.7V ~ 5.5V (at 4.5MHz)

• Operating Frequency: 1MHz ~ 4.5MHz

• Sub-clock: 32.768KHz Crystal Oscillator

• Enhanced EMS Improvement Power Fail Processor (Noise Immunity Circuit)

Device name ROM Size RAM Size OTP Package

GMS81C2012 12K bytes

448 bytes

64SDIP, 64MQFP, 64LQFP

GMS81C2020 20K bytes GMS87C2020

Page 8

GMS81C2012/GMS81C2020

2 JUNE. 2001 Ver 1.00

1.3 Development Tools

The GMS81C20xx are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.

and OTP programmers. There are third diffe rent type program mers such as emulator add-on board type, single type, gang type. For mode detail, Refer to “21. OTP PROGRAMMING” on page 85. Macro assembler operates under the MS-Windows 95/98

Please contact sales part of Hynix Semiconductor.

1.4 Ordering Information

In Circuit

Emulators

CHOICE-Dr.

Socket Adapter

for OTP

OA87C20XX-64SD (64SDIP)

OA87C20XX-64QF (64MQFP)

OA87C20XX-64QT (64LQFP)

POD

CHPOD81C20D-64SD (64SDIP)

Assembler

HYNIX Macro Assembler

Device name ROM Size RAM size Package

Mask version

GMS81C2012 K GMS81C2012 Q GMS81C2012 LQ GMS81C2020 K GMS81C2020 Q GMS81C2020 LQ

12K bytes 12K bytes 12K bytes 20K bytes 20K bytes 20K bytes

448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes

64SDIP 64MQFP 64LQFP 64SDIP 64MQFP 64LQFP

OTP version

GMS87C2020 K GMS87C2020 Q GMS87C2020 LQ

20K bytes OTP 20K bytes OTP 20K bytes OTP

448 bytes 448 bytes 448 bytes

64SDIP 64MQFP 64LQFP

Page 9

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 3

2. BLOCK DIAGRAM

ALU

Interrupt Controller

Data Memor y

8-bit ADC

8-bit

Counter

Timer/

Program

Memory

Data Table

8-bit Basic

Timer

Interval

Watchdog

Timer

R4 R5

PSW

Syst

em controller

Timing generator

System

Clock Controller

Cloc k Generator

RESET

OUT

R40 / T0O R41

R50

R20~R27

Power

Supply

8-bit serial

R51 R52 R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57

R10~R17

R30~R35

Interface

Buzzer

Driver

R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7

(448 bytes)

10-bit

AVDDAV

ADC Power

Supply

Stack Pointer

R04 R03/BUZO R02/EC0

R00/INT0

Vdisp/RA

R70 / AN8 R71 / AN9 R72 / AN10

R42 R43 R73 / AN11

Sub System

Clock Controller

OUT

R05

R06

R07

R01/INT1

PWM

X Y

High Voltage Port

Page 10

GMS81C2012/GMS81C2020

4 JUNE. 2001 Ver 1.00

3. PIN ASSIGNMENT

R40 R42

R43 R50 R51 R52 R53 R54 R55 R56 R57

RESET

SCLK

SIN

SOUT

PWM1O/T1O

SXIN

SXOUT

AN0

R74 R75

R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73

AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8

AN9 AN10 AN11

RA R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 V

R51

R30 R31 R32 R33 R34 R35

RA R40 R41 R42 R43 R50

T0O

disp

R66

R04 R03 R02 R01 R00 V

R73 R72 R71 R70 R67

AN6

AN8 AN7

R27

R25

R24

R23

R22

R21

R20

R17

R16

R15

R14

R13

R12

R11

R10

R07

R26

R06

R05

R52

R54

R55

R56

R57

RESET

R74

R75

R60

R61

R62

R63

R53

R64

R65

SIN

SOUT

PWM1O/T1O

SXI

SXO

AN0

AN1

AN2

AN3

SCLK

AN4

AN5

123456789

101112131415161718

484746

4443424140

3837363534

515049

32 31 30 29 28 27 26 25 24 23 22 21 20

52 53 54 55 56 57 58 59 60 61 62 63 64

64MQFP

64SDIP

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

BUZO EC0 INT1 INT0

disp

R41

T0O

AN9

AN11 AN10

INT0

EC0 INT1

BUZO

High Voltage Port

GMS81C2012/20

Page 11

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 5

R06 R05 R04 R03 R02 R01 R00 V

R73 R72 R71 R70 R67 R66 R65

R26

R25

R24

R23

R22

R21

R20

R17

R16

R15

R14

R13

R12

R11

R10

R07

R54

R55

R56

R57

RESET

XIN

XOUT

R74

R75

R60

R61

R62

R63

R64

123456789

10111213141516

R27 R30 R31 R32 R33 R34 R35

R40 R41 R42 R43 R50 R51 R52 R53

484746454443424140393837363534

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

64LQFP

SIN

SOUT

PWM1O/T1O

SXIN

SXOUT

AN0

AN1

AN2

AN3

AN4

AN6

AN8 AN7

AN5

disp

T0O

SCLK

AN10

AN11 AN9

INT1

BUZO EC0

INT0

High Voltage Port

GMS81C2012/20

Page 12

GMS81C2012/GMS81C2020

6 JUNE. 2001 Ver 1.00

4. PACKAGE DIAGRAM

UNIT: INCH

2.280

2.260

0.022

0.016

0.050

0.030

0.070 BSC

0.140

0.120

min. 0.015

0.680

0.660

0.750 BSC

0-15

64SDIP

0.205 max.

20.10

19.90

24.15

23.65

18.15

17.65

14.10

13.90

3.18 max.

0.50

0.35

1.00 BSC

SEE DETAIL "A"

1.03

0.73

0-7

0.36

0.10

0.23

0.13

1.95 REF

DETAIL "A"

UNIT: MM

64MQFP

Page 13

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 7

1.60 max.

SEE DETAIL "A"

0.75

0.45

0-7

0.15

0.05

1.00 REF

DETAIL "A"

UNIT: MM

10.00 BSC

12.00 BSC

10.00 BSC

0.38

0.22

0.50 BSC

1.45

1.35

64LQFP

Page 14

GMS81C2012/GMS81C2020

8 JUNE. 2001 Ver 1.00

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent po wer source as wel l as poss ible, oth er than digital power source.

: ADC circuit ground.

RESET

: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

RA(V

disp

)

: RA is one-bit high-voltage input only port pin.

In addition, RA serves the functions of the V

disp

special

features. V

disp

is used as a high-voltage i nput power supply

pin when selected by the mask option.

R00~R07

: R0 is an 8-bit hi gh-voltage CMOS bidir ectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features.

R10~R17

: R1 is an 8-bit high-volta ge CMOS bidirect ional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R20~R27

: R2 is an 8-bit high-volta ge CMOS bidirect ional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R30~R35

: R3 is a 6-bit high-voltage CMOS bidirectional I/O port. R3 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs.

R40~R43

: R4 is a 4-bit CMOS bidirection al I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R 4 serves the func-

tions of the following special features.

R50~R57

: R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features.

R60~R67

: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input.

R70~R73

: R7 is a 4-bit CMOS bidirectiona l I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R7 is shared with the ADC input.

: Input to the internal subsystem clock operating circuit. In addition, SXIN serves the R74 pin when selected by the code option. *R74 has a Pull-up circuit.

OUT

: Output from the inverting subsystem oscillator

amplifier. In addition, SXOUT serves the R75 pin when

Port pin Alternate function

disp

(High-voltage input power supply)

Port pin Alternate function

R00 R01 R02 R03

INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output)

Port pin Alternate function

R40 T0O (Timer/Counter 0 output)

Port pin Alternate function

R53 R54 R55 R56

SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output)

Port pin Alternate function

R60 R61 R62 R63 R64 R66 R66 R67

AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7)

Port pin Alternate function

R70 R71 R72 R73

AN8 (Analog Input 8) AN9 (Analog Input 9) AN10 (Analog Input 10) AN11 (Analog Input 11)

Page 15

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 9

selected by the code option. *R75 has a Pull-up circuit.

Port pin Alternate function

SXI

SXO

R74(Included Internal Pull-up Resister) R75(Included Internal Pull-up Resister)

Page 16

GMS81C2012/GMS81C2020

10 JUNE. 2001 Ver 1.00

PIN NAME In/Out

Function

Basic Alternate

- Supply voltage

- Circuit ground

RA (V

disp

)

I(I) 1-bit high-voltage Input only port High-voltage input power supply pin RESET I Reset signal input XIN I Oscillation input XOUT O Oscillation output SXIN(R74) I Sub Os cillation input

General I/O ports

SXOUT(R75) O Sub Oscillation output R00 (INT0) I/O (I)

8-bit high-voltage I/O ports

External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) Timer/Counter 0 external input R03 (BUZO) I/O (O) Buzzer driving output R04~R07 I/O R10~R17 I/O 8-bit high-voltage I/O ports R20~R27 I/O 8-bit high-voltage I/O ports R30~R35 I/O 6-bit high-voltage I/O ports R40 (T0O) I/O (O)

4-bit general I/O ports

Timer/Counter 0 output R41~R43 I/O R50~R52 I/O

8-bit general I/O ports

R53 (SCLK) I/O (I/O) Serial clock source R54 (SIN) I/O (I) Serial data input R55 (SOUT) I/O (O) Serial data output

R56 (PWM1O/T1O) I/O (O)

PWM 1 pulse output /Timer/Counter 1 out-

put R57 I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports

Analog voltage input

R70~R73 (AN8~AN11)

I/O (I) 4-bit general I/O ports

- Supply voltage input pin for ADC

- Ground level input pin for ADC

- Supply voltage

- Circuit ground

Table 5-1 GMS81C2020 Port Function Description

Page 17

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 11

6. PORT STRUCTURES

R41~R43, R50~R52, R57

R00/INT0, R01/INT1, R02/EC0

R40/T0O

R53/SCLK

R54/SIN

Data Reg.

Dir.

VSS

Reg.

Data Bus

MUX

Mask Option

Pull-up Tr.

Data Reg.

Dir.

Vdisp

Reg.

Data Bus

Selection

Data Reg.

EX) INT0 Alternate Function

Mask Option

MUX

Data Bus

Data Reg.

Direction

Reg.

MUX

Selection

Secondary Function

Mask Option

Pull-up Tr .

Data Bus

Data Reg.

Direction

Reg.

MUX

Selection

SCLK Output

SCLK Input

Mask

N-MOS Open Drain Select

Option

Pull-up Tr.

Data Bus

Data Reg.

Direction

Reg.

Selection

SIN Input

Mask

N-MOS Open Drain Select

Option

Pull-up Tr.

Page 18

GMS81C2012/GMS81C2020

12 JUNE. 2001 Ver 1.00

R55/SOUT

RA/Vdisp

R04~R07, R10~R17, R20~R27, R30~R35

RESET

SXIN, SXOUT

XIN, XOUT

Data Bus

Data Reg.

Direction

Reg.

MUX

Selection

SOUT output

IOSWIN Input

Mask

N-MOS Open Drain Select

IOSWB

Option

Pull-up Tr.

Vdisp

Data bus

Mask Option

Data Reg.

Dir.

Vdisp

Reg.

Data Bus

MUX

Mask Option

RESET

OTP :disconnected Main :connected

SXOUT

SXIN

Stop Subclk Off

XOUT

XIN

Stop Mainclk Off

Page 19

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 13

R74, R75

R03/BUZO

R56/PWM1O/T1O

R60~R67/AN0~AN7, R70~R73/AN8~AN11

Data Reg.

Dir.

VSS

Reg.

Data Bus

MUX

Data Reg.

Dir.

Vdisp

Reg.

Data Bus

MUX

Selection

Data Reg.

Secondary Function

Mask Option

Data Bus

Data Reg.

Direction

Reg.

MUX

Selection

SOUT output

Mask

N-MOS Open Drain Select

Option

Pull-up Tr.

Data Bus

Data Reg.

Direction

Reg.

Mask

A/D

Analog

Converter

Input Mode A/D Ch.

Selection

Option

Pull-up Tr.

Page 20

GMS81C2012/GMS81C2020

14 JUNE. 2001 Ver 1.00

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage.............................................-0.3 to +7.0 V

Storage Temperature ....................................-40 to +85 °C

Voltage on Normal voltage pin with respect to Ground (V

)

..............................................................-0.3 to V

+0.3 V

Voltage on High voltage pin with respect to Ground (V

)

............................................................-45V to V

+0.3 V

Maximum current out of V

pin..........................150 mA

Maximum current into V

pin ..............................80 mA

Maximum current sunk by (I

per I/O Pin) ..........20 mA

Maximum output current sourced by (I

per I/O Pin)

............................. ...... ................................................ 8 mA

Maximum current (ΣI

)......................................100 mA

Maximum current (ΣI

)........................................50 mA

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause per manent damage to the d evice. This is a stress ra ting only and functional ope r ati on of the device at any oth er c ond iti ons ab ov e tho se ind ic ated in the oper ati o na l se c ti ons of this s pecificatio n i s no t i mp l ie d . Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

(TA=25°C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @

XIN

=4MHz)

Parameter Symbol Condition

Specifications

Unit

Min. Max.

Supply Voltage

fXI = 4.5 MHz

2.7 5.5 V

Operating Frequency

XIN

VDD = V

14.5MHz

Operating Temperature

OPR

-40 85

Parameter Symbol Condition

Specifications

Unit

Min.

Typ.

1. Data in “T yp” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Max.

Analog Power Supply Input Voltage Range

Analog Input Voltage Range

-0.3

+0.3

Current Following Between AV

and

AVDD

--200uA

Overall Accuracy

--±2LSB

Non-Linearity Error

NLE

--±2LSB

Differential Non-Linearity Error

DNLE

--±2LSB

Zero Offset Error

ZOE

--±2LSB

Full Scale Error

FSE

--±2LSB

Gain Error

NLE

--±2LSB

Conversion Time

CONV

XIN

=4MHz

--20us

Page 21

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 15

7.4

DC Electrical Characteristics for Standard Pins(5V)

(VDD = 5.0V ± 10%, V

= 0V, TA = -40 ~ 85°C, f

XIN

= 4 MHz, Vdisp = VDD-40V to VDD)

Parameter Pin Symbol Test Condition

Specification

Unit

Min

Typ.

1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Max

Input High Voltage

XIN

SXIN V

IH1

External Clock

0.9V

VDD+0.3

RESET,SIN,R55,SCLK, INT0

1,EC0

IH2

0.8V

VDD+0.3

R40~R43,R5,R6,R70~R73

IH3

0.7V

VDD+0.3

Input Low Voltage

XIN, SXIN V

IL1

External Clock -0.3

0.1V

RESET

,SIN,R55,SCLK,

INT0

1,EC0

IL2

-0.3

0.2V

R40~R43,R5,R6,R70~R73

IL3

-0.3

0.3V

Output High

Voltage

R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT

= -0.5mA VDD-0.5

Output Low

Voltage

R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT

OL1

OL2

= 1.6mA

= 10mA

0.4 2

Input High

Leakage Current

R40~R43,R5,R6,R70~R73

IH1

1uA

Input Low

Leakage Current

R40~R43,R5,R6,R70~R73

IL1

-1 uA

Input Pull-up

Current(*Option)

R40~R43,R5,R6,R70~R73

50 100 180 uA

Power Fa il

Detect Voltage

PFD

2.7 V

Current dissipation

in active mode

XIN

=4.5MHz 8 mA

Current dissipation

in standby mode

STBY

XIN

=4.5MHz 3 mA

Current dissipation in sub-active mode

SUB

XIN

= Off

SXIN

=32.7KHz

100 uA

Current dissipation

in watch mode

WTC

XIN

=Off

SXNI

=32.7KHz

20 uA

Current dissipation

in stop mode

STOP

XIN

=Off

SXIN

=32.7KHz

10 uA

Hysteresis

RESET

,SIN,R55,SCLK,

INT0

INT1,EC0

T+~VT-

0.4 V

Internal RC WDT

Frequency

XOUT

RCWDT

830KHz

RC Oscillation

Frequency

XOUT

RCOSC

R= 120K

Ω

1.522.5MHz

Page 22

GMS81C2012/GMS81C2020

16 JUNE. 2001 Ver 1.00

7.5 DC Electrical Characteristics for High-Voltage Pins

(VDD = 5.0V ± 10%, V

= 0V, TA = -40 ~ 85°C, f

XIN

= 4 MHz, Vdisp = VDD-40V to VDD)

Parameter Pin Symbol Test Condition

Specification

Unit

Min

Typ.

1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Max

Input High Voltage R0,R1,R2,R30~R35,RA

0.7V

VDD+0.3

Input Low Voltage R0,R1,R2,R30~R35,RA

VDD-40 0.3V

Output High

Voltage

R0,R1,R2,R30~R35

= -15mA

= -10mA

= - 4mA

-3.0 VDD-2.0 V

-1.0

Output Low

Voltage

R0,R1,R2,R30~R35

Vdisp = VDD-40

150KΩ atVDD-

-37

VDD-37

Input High

Leakage Current

R0,R1,R2,R30~R35,RA

VIN=VDD-40V

to V

20 uA

Input Pull-down

Current(*Option)

R0,R1,R2,R30~R35

Vdisp=VDD-35V

VIN=V

200 600 1000 uA

Input High Voltage R0,R1,R2,R30~R35,RA

0.7V

VDD+0.3

Page 23

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 17

7.6 AC Characteristics

(TA=-40~ 85°C, VDD=5V±10%, VSS=0V)

Figure 7-1 Timing Chart

Parameter Symbol Pins

Specifications

Unit

Min. Typ. Max.

Operating Frequency

XIN 1 - 8 MHz

External Clock Pulse Width

CPW

XIN 80 - - nS

External Clock Transition Time

RCP,tFCP

XIN - - 20 nS

Oscillation Stabilizing Time

XIN, XOUT - - 20 mS

External Input Pulse Width

EPW

INT0, INT1, EC0 2 - -

SYS

External Input Pulse Transition Time

REP,tFEP

INT0, INT1, EC0 - - 20 nS

RESET Input Width

RST

RESET 8--

SYS

RCP

FCP

INT0, INT1

0.5V

-0.5V

0.2V

RESETB

REP

FEP

0.2V

0.8V

EC0

RST

EPW

1/f

CPW

SYS

Page 24

GMS81C2012/GMS81C2020

18 JUNE. 2001 Ver 1.00

7.7 AC Characteristics

(TA=-40~+85°C, VDD=5V±10%, VSS=0V, f

XIN

=4MHz)

Figure 7-2 Serial I/O Timing Chart

Parameter Symbol Pins

Specifications

Unit

Min. Typ. Max.

Serial Input Clock Pulse

SCYC

SCLK

SYS

+200

-8ns

Serial Input Clock Pulse Width

SCKW

SCLK

SYS

+70

-8ns

Serial Input Clock Pulse Transition Time

FSCK

RSCK

SCLK - - 30 ns

SIN Input Pulse Transition Time

FSIN

RSIN

SIN - - 30 ns

SIN Input Setup Time (External SCLK)

SUS

SIN 100 - - ns

SIN Input Setup Time (Internal SCLK)

SUS

SIN 200 - ns

SIN Input Hold Time

SIN

SYS

+70

-ns

Serial Output Clock Cycle Time

SCYC

SCLK

SYS

16t

SYS

Serial Output Clock Pulse Width

SCKW

SCLK

SYS

-30

Serial Output Clock Pulse Transition Time

FSCK

RSCK

SCLK 30 ns

Serial Output Delay Time

OUT

SOUT 100 ns

SCLK

SIN

0.2V

SOUT

0.2V

0.8V

SCYC

SCKW

RSCK

FSCK

0.8V

SUS

0.2V

0.8V

RSIN

FSIN

Page 25

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 19

7.8 Typical Characteristics

This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices

are guaranteed to operate properly only within the specified range.

The data presented in this s ection is a statistical s ummary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation

−

-1.6

-1.2

-0.8

-0.4

4.6 4.7

4.8 4.9

5.0

(V)

Ta=25°C

VDD=5.0V

(mA)

−

-1.6

-1.2

-0.8

-0.4

3.6 3.7

3.8 3.9

4.0

(V)

Ta=25°C

VDD=4.0V

(mA)

−

-1.6

-1.2

-0.8

-0.4

2.6 2.7

2.8 2.9

3.0

(V)

Ta=25°C

VDD=3.0V

(mA)

−

0.6 0.8

1.0 1.2

1.4

(V)

Ta=25°C

VDD=5.0V

(mA)

−

0.6 0.8

1.0 1.2

1.4

(V)

Ta=25°C

VDD=4.0V

(mA)

−

0.6 0.8

1.0 1.2

1.4

(V)

Ta=25°C

VDD=3.0V

(mA)

−

-16

-12

-8

-4

1.0 2.0

3.0 4.0

5.0

(V)

Ta=25°C

VDD=5.0V

(mA)

−

-16

-12

-8

-4

1.0 2.0

3.0 4.0

5.0

(V)

Ta=25°C

VDD=4.0V

(mA)

−

-16

-12

-8

-4

1.0 2.0

3.0 4.0

5.0

(V)

Ta=25°C

VDD=3.0V

(mA)

R40~R43, R5, R6, R70~R73 BUZO, T0O, PWM1O/T1O SCLK, SOUT pins

R0, R1, R2,RA R30~R35 pins

Page 26

GMS81C2012/GMS81C2020

20 JUNE. 2001 Ver 1.00

Ta=25°C

−

4.0

3.0

2.0

1.0

(mA)

(V)

Normal Operation

STOP

−

2.0

1.5

1.0

0.5

(µA)

(V)

Stop Mode

85°C 25°C

-20°C

XIN

= 4.5MHz

2.5MHz

Ta=25°C

SBY

−

4.0

3.0

2.0

1.0

(mA)

(V)

Stand-by Mode

XIN

= 4.5MHz

2.5MHz

−

IL2

(V)

IL2

(V)

−

IL1

(V)

IL1

(V)

Ta=25°C

XIN

=4.5MHz

Ta=25°C

XIN

=4.5MHz

−

IL3

(V)

IL3

(V)

Ta=25°C

XIN

=4.5MHz

RESET, R55, SIN, SCLK INT0, INT1, EC0 pinsXIN, SXIN pins

R40~R43, R5

R6, R70~R73 pins

−

IH2

(V)

IH2

(V)

−

IH1

(V)

IH1

(V)

Ta=25°C

XIN

=4.5MHz

Ta=25°C

XIN

=4.5MHz

−

IH3

(V)

IH3

(V)

Ta=25°C

XIN

=4.5MHz

RESET, R55, SIN, SCLK INT0, INT1, EC0 pinsXIN, SXIN pins

R40~R43, R5 R6, R70~R73 pins

Page 27

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 21

8. MEMORY ORGANIZATION

The GMS81C2012 and GMS81C2020 have separate address spaces for Program memory and Data Memory. Pro gram memory can only be read, not written to. It can be up

to 12K/20K bytes of Program memory. Data memory can be read and written to up to 448 by tes includ ing the s tack area.

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator:

The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y Register as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers

: In the addressing mode which uses these index registers, the register conten ts a re added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables . The index regi sters also h ave increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.

Stack Pointer

: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore).

Generally, SP is automatically updated when a subrout ine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost.

The stack can be located at any position within 100

1FF

of the internal data memory. The SP is not initialized by hardware, requiring to write the initial v alue (the lo cation with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FF

” is

used.

Note:

The Stack Pointer must be initi alized by softwa re be-

cause its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH

Program Counter

: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PC

:0FFH, PCL:0FEH).

Program Status Word

: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C] This flag stores any carry or borrow from the ALU of CPU

after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.

[Zero flag Z] This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

ACCUMULATOR X REGISTER Y REGISTER

STACK POINTER PROGRAM COUNTER

PROGRAM STATUS WORD

PCL

PSW

PCH

Two 8-bit Registers can be used as a "YA" 16-bit Register

Y A

Stack Address ( 100H ~ 1FEH )

Bit 15 Bit 087

Hardware fixed

00H~FF

Page 28

GMS81C2012/GMS81C2020

22 JUNE. 2001 Ver 1.00

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction.

[Half carry flag H] After operation, this is set when there is a carry from bit 3

of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V).

[Break flag B] This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector address.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00

to 0FFH when this flag is "0". If it is set to "1",

addressing area is assigned 100

to 1FFH. It is set by

SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7F

) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag.

[Negative flag N] This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

V G B H I Z C

MSB LSB

RESET VALUE : 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF

ADDITION OPERLANDS

SELECT DIRECT PAGE

when G=1, page is selected to “page 1”

Page 29

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 23

Figure 8-4 Stack Operation

At execution of a CALL/TCALL/PCALL

PCL

PCH

01FB

SP after execution

SP before execution

01FC

01FD

01FE

Push down

At acceptance of interrupt

PCL

PCH

01FB

01FC

01FD

01FE

Push down

PSW

At execution of RET instruction

PCL

PCH

01FB

01FE

01FC

01FD

01FE

01FC

Pop up

At execution of RET instruction

PCL

PCH

01FB

01FE

01FC

01FD

01FE

01FB

Pop up

PSW

0100H

01FEH

Stack depth

At execution of PUSH instruction

01FB

01FD

01FC

01FD

01FE

Push down

SP after execution

SP before execution

PUSH A (X,Y,PSW)

At execution of POP instruction

01FB

01FE

01FC

01FD

01FE

01FD

Pop up

POP A (X,Y,PSW)

Page 30

GMS81C2012/GMS81C2020

24 JUNE. 2001 Ver 1.00

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 2 0K bytes program memory space only physically implemented. Accessing a location above FFFF

will cause a wrap-around to 0000H.

Figure 8-5, shows a map of Pr ogram Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFE

and FFFFH as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fix ed location in Program Memory. Program Memory area contains the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length .

Table Call (TCALL) c auses the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0

for TCALL15, 0FFC2H for

TCALL14, etc., as shown in Figure 8-7.

Example: Usage of TCALL

The interrupt causes the CPU to jum p to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9H for External Interru pt 1,

0FFFA

and 0FFFBH for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.

Figure 8-6 Interrupt Vector Area

Interrupt

Vector Area

D000

FEFF

FF00

FFC0

FFDF

FFE0

FFFF

PCALL area

B000

TCALL area

GMS81C2012, 12K ROM

GMS81C2020, 20K ROM

LDA #5

TCALL 0FH ;

1BYTE INSTRUCTION

IN STEAD OF 3 BYTES

NORMAL CALL

; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0

RET ; FUNC_B: LDA LRG1

RET ; ;TABLE CALL ADD. AREA ;

ORG 0FFC0H ;

TCALL ADDRESS AREA

DW FUNC_A

DW FUNC_B

0FFE0H

Address Vector Area Memory

E4 E6 E8 EA EC EE F0

F2 F4 F6 F8 FA FC FE

Serial Communication Interface

Basic Interval Timer

Timer/Counter 0 Interrupt

External Interrupt 0

RESET Vector Area

External Interrupt 1

Watchdog Timer Interrupt

"-" means reserved area.

NOTE:

Timer/Counter 1 Interrupt

A/D Converter

Page 31

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 25

Figure 8-7 PCALL and TCALL Memory Area

PCALL

→

→ →

→

rel

4F35 PCALL 35H

TCALL

→

→ →

→

4A TCALL 4

0FFC0

Address P ro gra m Mem o r y

C2 C3 C4 C5 C6 C7 C8

0FF00

Address

PCALL Area Memory

0FFFF

PCALL Area

(256 Bytes)

* means that the BRK software interrupt is using same address with TCALL0.

NOTE:

TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8

TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *

C9 CA CB CC CD CE CF

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF

0FF35

0FF00

0FFFF

11111111 11010110

01001010

PC:

FH FH DH 6H

0FFD6

0FF00

0FFFF

0FFD7

➊

➋

➌

0D125

Reverse

Page 32

GMS81C2012/GMS81C2020

26 JUNE. 2001 Ver 1.00

Example: The usage software example of Vector address for GMS81C2020.

ORG 0FFE0H DW NOT_USED

DW NOT_USED DW SIO ; Serial Interface DW BIT_TIMER ; Basic Interval Timer DW WD_TIMER ; Watchdog Timer DW ADC ; ADC DW NOT_USED DW NOT_USED DW NOT_USED DW NOT_USED DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW INT1 ; Int.1 DW INT0 ; Int.0 DW NOT_USED ; DW RESET ; Reset

ORG 0B000H ; GMS81C2020(20K)ROM Start address

; ORG 0D000H ; GMS81C2012(12K)ROM Start address ;*******************************************

; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts

CLRG LDX #0

RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH)

STA {X}+ CMPX #0C0H BNE RAM_CLR

;

LDX #0FFH ;Stack Pointer Initialize TXSP

;

LDM R0, #0 ;Normal Port 0 LDM R0IO,#82H ;Normal Port Direction : : : LDM TDR0,#125 ;8us x 125 = 1mS LDM TM0,#0FH ;Start Timer0, 8us at 4MHz LDM IRQH,#0 LDM IRQL,#0 LDM IENH,#0E0H ;Enable Timer0, INT0, INT1 LDM IENL,#0 LDM IEDS,#05H ;Select falling edge detect on INT pin LDM R0FUNC,#03H ;Set external interrupt pin(INT0, INT1)

EI ;Enable master interrupt : : :

: :

NOT_USED:NOP

RETI

Page 33

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 27

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data Memory is divi d ed i nto two groups, a user RAM (including Stack) and control registers.

Figure 8-8 Data Memory Map

User Memory

The GMS81C20xx have 448 × 8 bits for the user me mo ry (RAM).

Control Registers

The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to

digital converters and I/O ports. The control registers are in address range of 0C0

to 0FFH.

Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

More detailed informations of each register are explained in each peripheral section.

Note:

Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”.

Example; To write at CKCTLR

LDM CLCTLR,#09H

;Divide ratio(

÷16

)

Stack Area

The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt.

When returning from the processing routine, execu ting the subroutine return instruction [RET] restores the contents of the program counter from the stack; ex ecuting the interrupt return instruction [RETI] restores the contents of the program counter and flags.

The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 23.

User Memory

Control

Registers

or Stack Area

0000

00BF

00C0

00FF

0100

01FF

PAGE0

User Memory

PAGE1

When “G-flag=0”,

When “G-flag=1”

this page is selected

Page 34

GMS81C2012/GMS81C2020

28 JUNE. 2001 Ver 1.00

Note:

Several names are given at same address. Refer to below table.

Address

Symbol R/W

RESET

Value

Addressing

mode

0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H

0C9H 0CAH 0CBH 0CCH 0CDH 0CEH

0CFH

R0IO

R1IO

R2IO

R3IO

R4IO

R5IO

R6IO

R7IO

R/W

Undefined 0000_0000 Undefined

00000000 Undefined 0000_0000 Undefined

--00_0000 Undefined

----_0000 Undefined 0000_0000 Undefined 0000_0000 Undefined

--00_0000

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

0D0H 0D1H

0D1H 0D1H

0D2H 0D3H

0D3H

0D4H

0D4H 0D4H

0D5H

0DEH

TM0

T0 TDR0 CDR0

TM1

TDR1

T1PPR

T1 CDR1

T1PDR

PWM1HR

BUR

R/W

W W

R R

R/W

W W

--00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000

----_0000 1111_1111

byte, bit

byte byte byte

byte, bit

byte byte byte byte

byte, bit

byte byte

0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH

0ECH

0EDH

0EFH

SIOM SIOR IENH

IENL

IRQH

IRQL

IEDS ADCM ADCR

BITR

CKCTLR

WDTR WDTR

PFDR

R/W R/W R/W R/W R/W R/W R/W R/W

R R

R/W

0000_0001 Undefined 0000_---0000_---0000_---0000_----

----_0000

-000_0001 Undefined 0000_0000

-001_0111 0000_0000 0111_1111

----_-100

byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit

byte byte byte byte byte

byte, bit

0F4H 0F5H 0F6H 0F7H 0F8H

0F9H 0FAH 0FBH

R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR

SCMR

W W W W W W

R/W

----_0000

----_---0

-0--_---0000_0000

----_0000 0000_0000

---0_0000 Undefined

byte byte byte byte byte byte byte

Table 8-1 Control Registers

1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.

3. RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.

Addr.

When read When write

Timer Mode

Capture

Mode

PWM

Mode

Timer Mode

PWM Mode

D1H T0 CDR0 - TDR0 D3H - TDR1 T1PPR D4H T1 CDR1 T1PDR - T1PDR ECH BITR CKCTLR

Table 8-2 Various Register Name in Same Address

Page 35

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 29

Address Name

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C2H R1 R1 Port Data Register (Bit[7:0]) C3H R1IO R1 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register

(Bit[5:0])

C7H R3IO R3 Port Direction Register

(Bit[5:0])

C8H R4 R4 Port Data Register

(Bit[3:0])

C9H R4IO R4 Port Direction Register

(Bit[3:0])

CAH R5 R5 Port Data Register (Bit[7:0])

CBH R5IO R5 Port Direction Register (Bit[7:0]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0])

CEH R7 R7 Port Data Register

(Bit[5:0])

CFH R7IO R7 Port Direction Register

(Bit[5:0])

D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST

D1H

T0/TDR0/ CDR0

Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H

TDR1/ T1PPR

Timer1 Data Register / PWM1 Period Register

D4H

T1/CDR1/ T1PDR

Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register

(Bit[3:0])

DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0

E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - -

E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register

Table 8-3 Control Registers of GMS81C2020

These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ".

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ECH

BITR

Basic Interval Timer Data Register

ECH

CKCTLR

- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH

PFDR

-----PFDISPFDMPFDS

F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O

F6H R5FUNC -

PWM1O/

T1O

- - - - - -

F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8

F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBON CLKSEL MAINOFF FBHRA -------RA0

1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.

2.The register PFDR only be implemented on devices, not on In-circuit Emulator.

Address Name

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Table 8-3 Control Registers of GMS81C2020

These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by register operation instruction as " LDM dp,#imm ".

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8.4 Addressing Mode

The GMS800 series MCU uses six addressing modes;

• Register addressing

• Immediate addressing

• Direct page addressing

• Absolute addressing

• Indexed addressing

• Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

→

→ →

→

#imm

In this mode, second byte (operand) is accessed as a data immediate ly.

Example:

0435 ADC #35H

When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data.

Example: G=1

E45535 LDM 35H,#55H

(3) Direct Page Addressing

→

→ →

→

In this mode, a address is specified within direct page. Example; G=0

C535 LDA 35H ;A ←RAM[35H]

(4) Absolute Addressing

→

→ →

→

!abs

Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command bec omes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY

Example;

0735F0 ADC !0F035H ;A ←ROM[0F035H]

The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag.

A+35H+C → A

MEMORY

0F100H

data ¨ 55H

data

0135H

➊

0F102H

0F101H

➋

data

35H

0E551H

data → A

➋

➊

0E550H

0F100H

data

0F035H

➊

0F102H

0F101H

➋

A+data+C → A

address: 0F035

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983501 INC !0135H ;A ←ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

→

→ →

→

{X}

In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15

, G=1

D4 LDA {X} ;ACC←RAM[X].

X indexed direct page, auto increment

→

→ →

→

{X}+

In this mode, a address is specified within direct page by the X register and the content of X is increased by 1.

LDA, STA Example; G=0, X=35

DB LDA {X}+

X indexed direct page (8 bit offset)

→

→ →

→

dp+X

This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

C645 LDA 45H+X

Y indexed direct page (8 bit offset)

→

→ →

→

dp+Y

This address value is the second byte (Operand) of command plus the data of Y-register, which assign s Memory in Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

→

→ →

→

!abs+Y

Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area.

Example; Y=55

0F100H

data

135H

➊

0F102H

0F101H

➋

data+1 → data

➌

address: 0135

data

115H

0E550H

data → A

➋

➊

data

35H

data Æ A

➋

➊

36H Æ X

data

3AH

0E551H

data → A

➋

➊

0E550H

45H+0F5H=13AH

➌

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GMS81C2012/GMS81C2020

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D500FA LDA !0FA00H+Y

(6) Indirect Addressing

Direct page indirect

→

→ →

→

[dp]

Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y.

JMP, CALL Example; G=0

3F35 JMP [35H]

X indexed indirect

→

→ →

→

[dp+X]

Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register dat a in Direct page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10

1625 ADC [25H+X]

Y indexed indirect

→

→ →

→

[dp]+Y

Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operan d in Direct pageplus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10

1725 ADC [25H]+Y

Absolute indirect

→

→ →

→

[!abs]

The program jumps to address specified by 16-bit absolute address.

JMP Example; G=0

0F100H

data → A

➊

data

0FA55H

0FA00H+55H=0FA55H

➌

0F102H

0F101H

➋

35H

jump to

➊

0FA00H

36H

➋

0E30AH

address 0E30AH

35H

0E005H

0FA00H

36H

0E005H

data

➌

A + data + C → A

25 + X(10) = 35

➊

➋

25H

0E005H + Y(10)

➊

0FA00H

26H

➋

0E015H

data

➌

= 0E015H

A + data + C

→

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1F25E0 JMP [!0C025H]

0E025H

jump to

0FA00H

0E026H

➋

0E725H

PROGRAM MEMORY

➊

address 0E30AH

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9. I/O PORTS

The GMS81C20xx has eight ports (R0, R1, R2, R3, R4, R5, R6 and R7).The se ports pins may be multiplexed with an alternate function for the peripheral features on the device.

All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specif y it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbe red bits as input ports, write “55

” to address 0C1H (R0 port direction reg-

ister) during initial setting as shown in Figure 9-1. All the port direction registers in the GMS81C2020 have 0

written to them by reset function. On the other hand, its initial status is input.

Figure 9-1 Example of Port I/O Assignment

RA(Vdisp) register:

RA is one-bit high-voltage input only port pin. In addition, RA se rves the funct ions of the V

disp

special features. V

disp

is used as a high-voltage input

power supply pin when selected by the mask option.

R0 and R0IO register:

R0 is an 8-bit high-voltage CMOS

bidirectional I/O port (address 0C0

). Each port can be set individually as input and output through the R0IO register (address 0C1

). Each port can directly drive a vacuum fluorescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt Input Port(INT1, INT0)

.The control register R0FUNC (address F4

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alter nate function such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the corresponding bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is sel ected to use as alterna te functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0)

Port pin Alternate function

disp

(High-voltage input power supply)

I : INPUT PORT

WRITE "55

" TO PORT R0 DIRECTION REGISTER

0 1 0 1 0 1 0 1

I O I O I O I O

R0 data

R1 data

R0 direction

R1 direction

0C0

0C1

0C2

0C3

76543210

BIT

76543210

PORT

O : OUTPUT PORT

RA Data Register RA

ADDRESS: 0FB

RESET VALUE: Undefined

RA0

Input data

Port Pin

Alternate Function

R00 R01 R02 R03

INT0 (External interrupt 0 Input Port) INT1 (External interrupt 1 Input Port) EC0 (Event Counter Input Port) BUZO (Buzzer Output Port)

R0 Data Register R0

ADDRESS: 0C0

RESET VALUE: Undefined

R07 R06 R05 R04 R03

R02 R01

R00

Port Direction

R0 Direction Register R0IO

ADDRESS : 0C1

RESET VALUE : 00

0: Input 1: Output

Input / Output data

R0 Function Selection Register R0FUNC

ADDRESS : 0F4

RESET VALUE : ----0000

0: R00 1: INT0

0: R01 1: INT1

0: R02 1: BUZO

0: R03 1: EC0

123----

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R1 and R0IO register:

R1 is an 8-bit high-volta ge CMOS

bidirectional I/O port (address 0C2

). Each port can be set individually as input and output th rou gh t he R1IO regis t er (address 0C3

). Each port can directly drive a vacuum flu-

orescent display.

R2 and R2IO register:

R2 is an 8-bit high-volta ge CMOS

bidirectional I/O port (address 0C4

). Each port can be set individually as input and output th rou gh t he R2IO regis t er (address 0C5

). Each port can directly drive a vacuum flu-

orescent display.

R3 and R3IO register:

R3 is a 6-bit high-voltage CMOS

bidirectional I/O port (address 0C6

). Each port can be set individually as input and output th rou gh t he R3IO regis t er

(address 0C7

R4 and R4IO register:

R4 is a 4-bit bidirectional I/O port

(address 0C8

). Each port can be set individually as input

and output through the R4IO regis ter (address 0C9

). R40

port is multiplexed with Timer 0 Output Port (T0O).

The control register R4FUNC (address 0F5

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alter nate function such as Timer 0 Output, write "1" to the corresponding bit of R4FUNC. Regardless of the direction register R4IO, R4FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (T0O)

R1 Data Register R1

ADDRESS: 0C2

RESET VALUE: Undefined

R17 R16 R15 R14 R13 R12 R11 R10

Port Direction

R1 Direction Register R1IO

ADDRESS : 0C3

RESET VALUE : 00

0: Input 1: Output

Input / Output data

R2 Data Register R2

ADDRESS: 0C4

RESET VALUE: Undefined

R27 R26 R25 R24 R23 R22 R21 R20

Port Direction

R2 Direction Register R2IO

ADDRESS : 0C5

RESET VALUE : 00

0: Input 1: Output

Input / Output data

Port Pin

Alternate Function

R40 T0O (Timer 0 Compare Output Port)

R3 Data Register R3

ADDRESS: 0C6

RESET VALUE: Undefined

- - R35 R34 R33 R32 R31 R30

Port Direction

R3 Direction Register R3IO

ADDRESS : 0C7

RESET VALUE : --000000

0: Input 1: Output

Input / Output data

- -

R4 Data Register R4

ADDRESS: 0C8

RESET VALUE: Undefined

- - - - R43 R42 R41 R40

Port Direction

R4 Direction Register R4IO

ADDRESS : 0C9

RESET VALUE : ----0000

0: Input 1: Output

Input / Output data

R4 Function Selection Register R4FUNC

ADDRESS : 0F5

RESET VALUE : -------0

0: R40 1: T0O

T0O-------

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R5 and R5IO register:

R5 is an 8-bit bidirectional I/O

port (address 0CA

). Each pin can be set individually as input and output through the R5IO register (address 0CB

).In addition, Po rt R5 is multiplexed wi th Pulse

Width Modulator (PWM).

The control register R5FUNC (address 0F6

) controls to select PWM function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To select PWM function, write "1" to the corresponding bit of R5FUNC. The control register R5NODR (address 0F9

) controls to select N-MOS open drain port. To select N-MOS open drain port, write "1" to the corresponding bi t of R5FUNC.

R6 and R6IO register:

R6 is an 8-bit bidirectional I/O

port (address 0CC

). Each port can be set individually as input and output through the R6IO register (address 0CD

). R67~R60 ports are multiplexed with Analog Inpu t

Port.

The control register R6FUNC (address 0F7

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alter nate function such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0)

Port Pin

Alternate Function

R56

PWM1 Data Output Timer 1 Data Output

R5 Data Register R5

ADDRESS: 0CA

RESET VALUE: Undefined

R57 R56 R55 R54 R53 R52 R51 R50

R5 Direction Register R5IO

ADDRESS : 0CB

RESET VALUE : 00

Input / Output data

R5 Function Selection Register R5FUNC

ADDRESS : 0F6

RESET VALUE : -0------

0: R56 1:

- -----6-

R5 N-MOS Open Drain

R5NODR

ADDRESS: 0F9

RESET VALUE: 00

N-MOS Open Drain Selection

Selection Register

0: Disable 1: Enable

Port Direction 0: Input 1: Output

PWM1O/T1O

Port Pin

Alternate Function

R60 R61 R62 R63 R64 R65 R66 R67

AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7)

R6 Function Selection Register R6FUNC

ADDRESS : 0F7

RESET VALUE : 00

0: R60 1: AN0

0: R61 1: AN1

0: R63 1: AN3

0: R62 1: AN2

1234567

0: R65 1: AN5

0: R64 1: AN4

0: R66 1: AN6

0: R67 1: AN7

R6 Data Register R6

ADDRESS: 0CC

RESET VALUE: Undefined

R67

R66 R65 R64 R63

R62 R61 R60

Input / Output data

R6 Direction Register R6IO

ADDRESS : 0CD

RESET VALUE : 00

Port Direction 0: Input 1: Output

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R7 and R7IO register:

R7 is a 4-bit bidire ctio nal I/O po rt

(address 0CE

). Each port can be set individually as input

and output through the R7IO register (address 0CF

). R73~R70 ports are multiplexed with Analog Input Port AN8~AN11). R74, R75 ports are alternate function of SXI, SXO ports

R74, R75 ports can be set in di vidually as

input and output through the R7IO register.

The control register R7FUNC (address 0F8

) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R7FUNC. Regardless of the direction register R7IO, R7FUNC is selected to use as alternate functions, port pin

can be used as a corresponding alternate features.

Port Pin

Alternate Function

R70 R71 R72 R73

SXI

SXO

AN8 (ADC input 8) AN9 (ADC input 9) AN10 (ADC input 10) AN11 (ADC input 11) R74(included Internal Pull-up Resister) R75(included Internal Pull-up Resister)

R7 Function Selection Register R7FUNC

ADDRESS : 0F8

RESET VALUE : ----0000

0: R70 1: AN8

0: R71 1: AN9

0: R73 1: AN11

0: R72 1: AN10

123

R7 Direction Register R7IO

ADDRESS : 0CF

RESET VALUE : --000000

Port Direction 0: Input 1: Output

R7 Data Register R7

ADDRESS: 0CE

RESET VALUE: Undefined

R73 R72 R71 R70

Input / Output data

----

R74R75

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10. BASIC INTERVAL TIMER

The GMS81C20xx has one 8-bit Basic Interval Timer that is free-run, can not stop. Block di agram is shown in Figure 10-1. In addition, the Basic Interval Tim er generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF).

The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overfl ows fr om FF

to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITIF is interrupt request flag of Basic interval timer. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2.

When write "1 " to bi t BTCL of CKCTLR, BITR reg ister is cleared to "0" and restart to count-up. The bit BTCL be-

comes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit

WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the o scillator, prescaler (only fXIN÷2048) and Timer0.

If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer.

Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0EC

is read as a BITR, and written to CKCTLR.

Figure 10-1 Block Diagram of Basic Interval Timer

MUX

Basic Interval

BITR

Select Input clock

Basic Interval Timer

source clock

8-bit up-counter

BTS[2:0]

BTCL

1024

512

256

128

To Watchdog timer (WDTCK)

CKCTLR

clear

overflow

Internal bus line

clock control register

[0EC

]

[0EC

]

BITIF

Read

Prescaler

Timer Interrupt

Internal RC OSC

RCWDT

WAKEUP

STOP

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Table 10-1 Basic Interval Timer Interrupt Time

Figure 10-2 BITR: Basic Interval Timer Mode Register

Example 1: Basic Interval Timer Interrupt request flag is generated

every 4.096ms at 4MHz.

: LDM CKCTLR,#03H SET1 BITE EI :

Example 2: Basic Interval Timer Interrupt request flag is generated

every 1.024ms at 4MHz.

: LDM CKCTLR,#01H SET1 BITE EI :

CKCTLR

[2:0]

Source clock

Interrupt (overflow) Period (ms)

@ f

XIN

= 4MHz

000 001 010 011 100 101 110 111

XIN

128

XIN

256

XIN

512

XIN

1024

0.512

1.024

2.048

4.096

8.192

16.384

32.768

65.536

BTCL

76543210

RCWDT

BTS1

Basic Interval Timer source clock select 000: f

XIN

÷ 8

001: f

XIN

÷ 16

010: f

XIN

÷ 32

011: f

XIN

÷ 64

100: f

XIN

÷ 128

101: f

XIN

÷ 256

110: f

XIN

÷ 512

111: f

XIN

÷ 1024

Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically

INITIAL VALUE: -001 0111

ADDRESS: 0EC

after one machine cycle, and starts counting.

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 0EC

BITR

Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.

Caution:

8-BIT FREE-RUN BINARY COUNTER

WDTON

BTS0BTS2

BTCL

76543210

0: Operate as a 7-bit general timer 1: Enable Watchdog Timer operation See the section “Watchdog Timer”.

WAKEUP

0: Disable Wake-up Timer 1: Enable Wake-up Timer

0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer

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11. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The purpo se of the watchdog timer is to detect the malfunction (runa way) of program due to external noise or other causes and return the operation to the normal condition.

The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not

require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for ex ample, by entering the STOP mode.

The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and

the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON.

Note:

Because the watchdog timer counter is enabled after clearing Basic Inte rval Timer, af ter the bit WDTO N set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle.

The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below.

LDM CKCTLR,#3FH; enable the RC-osc WDT LDM WDTR,#0FFH; set the WDT period STOP ; enter the STOP mode NOP NOP ; RC-osc WDT running :

The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS). The following equation shows the RCWDT oscillated watchdog timer time-out.

RCWD T

=CLK

RCWD T

×28×[

WD TR.6~0]+(CLK

RCWD T

×28)/2

where, CLK

RCWD T

= 40~ 120uS

In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below.

WDT

= [WDTR.6~0]

××××

Interval of BIT

Figure 11-1 Block Diagram of Watchdog Timer

to reset CPU

BASIC INTERVAL TIMER

Count

enable

Watchdog

7-bit compare data

comparato r

Watchdog Timer interrupt

clear

WDTIF

Counter (7-bit)

WDTCL

“0”

“1”

WDTON in CKCTLR [0EC

]

OVERFLOW

Watchdog Timer Register

WDTR

Internal bus line

[0ED

]

source

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Watchdog Timer Control

Figure 11-2 shows the watchdog timer control register. The watchdog timer is automatically disab led aft e r reset.

The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time.

If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from

the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET

pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated.

The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).

Figure 11-2 WDTR: Watchdog Timer Data Register

Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz

76543210

Clear count flag

0: Free-run count

INITIAL VALUE: 0111_1111

ADDRESS: 0ED

WDTR

WWWW

1: When the WDTCL is set to "1", binary counter

is cleared to “0”. And the WDTCL becomes “0” automatically after one machine cycle. Counter count up again.

7-bit compare data

WWWW

NOTE: The WDTON bit is in register CKCTLR.

WDTCL

LDM CKCTLR,#3FH ;

Select 1/2048 clock source, WDTON ← 1, Clear Counter

LDM WDTR,#04FH LDM WDTR,#04FH ;

Clear counter

: : : : LDM WDTR,#04FH ;

Clear counter

: : : : LDM WDTR,#04FH ;

Clear counter

Within WDT detection time

Page 49

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 43

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to “1”. WDTON is initialized to “0” during reset and it should be set to “1” to operate after reset is released.

Example: Enables watchdog timer for Reset

: LDM CKCTLR,#xx1x_xxxxB;

WDTON

← 1 : :

The watchdog timer is disabled by clearing bit 5 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released.

Watchdog Timer Interrupt

The watchdog timer can be also used as a simple 7-bit timer by clearin g bit5 of CKCTLR to “0”. The in terval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.

The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source.

Example: 7-bit timer interrupt set up.

LDM CKCTLR,#xx0xxxxxB;

WDTON

←0

LDM WDTR,#7FH ;

WDTCL

←1

Figure 11-3 Watchdog timer Timing

If the watchdog timer output becomes active, a reset is generated, which drives the RESET

pin low to reset the inter-

nal hardware.

The main clock oscillator also turns on wh en a watchdog timer reset is generated in sub clock mode.

T WDT R Interval of BIT

Source clock

Binary-counter

WDTR

WDTIF interrupt

WDTR ← "0100_0011

Match Detect

Counter Clear

BIT overflow

WDT reset reset

Page 50

GMS81C2012/GMS81C2020

44 JUNE. 2001 Ver 1.00

12. TIMER/EVENT COUNTER

The GMS81C20xx has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match).

Timer 0 and Timer 1 are can be used either two 8-bit Timer/Counter or one 16-bit Timer/Counter with combine them.

In the "timer" function, the register is increased every internal clock input. Thus , one can th ink of it as count ing in ternal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8).

In the “counter” function, the register is increase d in re-

sponse to a 1-to-0 (falling edge) or 0-to-1(ris ing edge) transition at its corresponding external input pin, EC0.

In addition the “capture” function, the register is increased in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into capture data register CDRx.

Timer1 is shared with "PWM" function and "Compare output" function

It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer m ode register TM0 and TM1 as shown in Figure 12-1 and Table 12-1.

16BIT CAP0 CAP1 PWM1E

T0CK

[2:0]

T1CK

[1:0]

PWM1O TIMER 0 TIMER 1

0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event c ounter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output 0 X 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 X 0 XXX 11 0 16-bit Capture (internal clock) 1 0 0 0 XXX 11 1 16-bit Compare Output

Table 12-1 Operating Modes of Timer0 and Timer1

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GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 45

Figure 12-1 TM0, TM1 Registers

BTCL

76543210

16BITPOL T1CN

INITIAL VALUE: 00

ADDRESS: 0D2

TM1

T1STT1CK0T1CK1

PWM1E

CAP1

Bit Name Bit Position Description

POL TM1.7 0: PWM Duty Active Low

1: PWM Duty Active High

16BIT TM1.6 0: 8-bit Mode

1: 16-bit Mode

PWMIE TM1.5 0: Disable PWM

1: Enable PWM

CAP1 TM1.4 0: Timer/Counter mode

1: Capture mode selection flag

T1CK1 T1CK0

TM1.3 TM1.2

00: 8-bit Timer, Clock source is f

XIN

01: 8-bit Timer, Clock source is f

XIN

÷ 2

10: 8-bit Timer, Clock source is f

XIN

÷ 8

11: 8-bit Timer, Clock source is Using the the Timer 0 Clock

T0CN TM1.1 0: Stop the timer

1: A logic 1 starts the timer.

T0ST TM1.0 0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

BTCL

543210

-- T0CN

INITIAL VALUE: --000000

ADDRESS: 0D0

TM0

T0STT0Ck0T0CK1CAP0 T0Ck2

Bit Name Bit Position Description

CAP0 TM0.5 0: Timer/Counter mode

1: Capture mode selection flag

T0CK2 T0CK1 T0CK0

TM0.4 TM0.3 TM0.2

000: 8-bit Timer, Clock source is f

XIN

÷ 2

001: 8-bit Timer, Clock source is f

XIN

÷ 4

010: 8-bit Timer, Clock source is f

XIN

÷ 8

011: 8-bit Timer, Clock source is f

XIN

÷ 32

100: 8-bit Timer, Clock source is f

XIN

÷ 128

101: 8-bit Timer, Clock source is f

XIN

÷ 512

110: 8-bit Timer, Clock source is f

XIN

÷ 2048

111: EC0

(External clock)

T0CN T M0 .1 0: Stop the time r

1: A logic 1 starts the timer.

T0ST TM0.0 0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

76543210

INITIAL VALUE: Undefined

ADDRESS: 0D1

TDR0

Read: Count value read Write: Compare data write

R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W

76543210

INITIAL VALUE: Undefined

ADDRESS: 0D3

TDR1

R/W R/W R/W R/W R/W R/W R/W R/W

Page 52

GMS81C2012/GMS81C2020

46 JUNE. 2001 Ver 1.00

12.1 8-bit Timer / Counter Mode

The GMS81C20xx has two 8-bit Timer/Counte rs, Timer 0 , Timer 1 as shown in Figure 12-2.

The "timer" or "counter" function is selected by mode registers TMx as shown in Fi gure 12-1 and Table 12-1. To use

as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to “0”(Table 12-1).

Figure 12-2 8-bit Timer/Counter 0, 1

EC0 PIN



XIN PIN

MUX

Prescaler

clear

0: Stop 1: Clear and start

T0ST

T0CK[2:0]

111

000 001

010

T0CN

MUX

T1IF

clear

0: Stop 1: Clear and start

T1ST

T1CK[1:0]

11 00

TIMER 1 INTERRUPT



TDR0 (8-bit)

TDR1 (8-bit)

T1 (8-bit)

T0 (8-bit)

Comparator

TIMER 0

TIMER 1

T1O PIN

F/F

BTCL

76543210

--T0CN

INITIAL VALUE: --000000

ADDRESS: 0D0

TM0

T0STT0CK0T0CK1CAP0 T0CK2

-- XXXX

X means don’t care







512



2048

011 100 101 110

T0IF

TIMER 0 INTERRUPT

T0O PIN

F/F

T1CN

INITIAL VALUE: 00

ADDRESS: 0D2

TM1

X means don’t care

BTCL

76543210

16BITPOL T1CN T1STT1CK0T1CK1

PWM1E

CAP1

X0 XXXX

EDGE DETECTOR

Page 53

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 47

Example 1:

Timer0 = 2ms 8-bit timer mode at 4M Hz Timer1 = 0.5ms 8-bit timer mode at 4MHz

LDM TDR0,#250 LDM TDR1,#250 LDM TM0,#0000_1111B LDM TM1,#0000_1011B SET1 T0E SET1 T1E EI

Example 2:

Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz

LDM TDR0,#250 LDM TDR1,#250 LDM TM0,#0001_1111B LDM TM1,#0000_1011B SET1 T0E SET1 T1E EI

Note:

The contents of Timer data register TDRx should be

initialized 1

~FFH, not 0H, because it is undefined after re-

set.

These timers have each 8-bit count register and data register. The count register is increased by every intern al or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 selected by control bits T0CK[2:0] of register (TM0) and 1, 2, 8 selected by control bits T1CK[1:0] of register (TM1). In the Timer 0, timer register T0 increases from 00

until it matches

TDR0 and then reset to 00

. The match output of Timer 0 generates Timer 0 interru pt (latched in T0IF bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx.

In counter function, the counter is increased every 0-to1(1-to-0) (rising & falling edge) transi tion of EC0 pin. In order to use counte r fun ctio n, th e bit EC0 o f t he R0

Func-

tion Selection

(R0FUNC.2) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not.

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GMS81C2012/GMS81C2020

48 JUNE. 2001 Ver 1.00

8-bit Timer Mode

In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer 1 interrupt (T1IF) is generated and the up-counter is cleared to 0.

Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time in-

terval is set as you want

Figure 12-3 Timer Mode Timing Chart

Figure 12-4 Timer Count Example

n-2

n-1

Source clock

Up-counter

TDR1 T1IF interrupt

Start count

1 4

Match Detect

Counter Clear

Timer 1 (T1IF) Interrupt

TDR1

TIME

Occur interrupt Occur interrupt Occur interrupt

Interrupt period

up-count

Count Pulse

= 8 µs x 125

MATCH

Example:

Make 2msinterrupt using by Timer0 at 4MHz

LDM TM0,#0FH ; divide by 32 LDM TDR0,#125 ; 8us x 125= 1ms SET1 T0E ; Enable Timer 0 Interrupt EI ; Enable Master Interrupt

Period

When

TDR0 = 125

= 7D

XIN

= 4 MHz

INTERRUPT PERIOD =

4 × 10

32 × 125 = 1 ms

TM0 = 0000 1111

(8-bit Timer mode, Prescaler divide ratio = 32)

8 µs

(TDR0 = T0)

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GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 49

8-bit Event Counter Mode

In this mode, counting up is started by an external trigger. This trigger means falling edge or rising edge of the EC0 pin input. Source clock is used as an internal clock selected with timer mode register TM0. The conten ts of ti mer data register TDR0 is compared with the contents of the upcounter T0. If a match is found, an timer interrupt request flag T0IF is generated, and the counter is cleared to “0”. The counter is restart and count up continuously by every falling edge or rising edge of the EC0 pin input.

The maximum frequency applied to the EC0 pin is f

XIN

[Hz].

In order to use event counter function, the bit 2 of the R5 function register (R5FUNC.2) is required to be set to “1”.

After reset, the value of timer data register TDR0 is undefined, it should b e initialized to between 1

~FFH not to "0"The interval period of Timer is calculated as below equation.

Figure 12-5 Event Counter Mode Timing Chart

Figure 12-6 Count Operation of Timer / Event counter

Period (sec)

XIN

---------- -

2 Divide Ratio TDR0

×××=

n-1

ECn pin input

Up-counter

TDR1

T1IF interrupt

Start count

Timer 1 (T1IF) Interrupt

TDR1

TIME

Occur interrupt Occur interrupt

stop

clear & start

disable

enable

Start & St op

T1ST

T1CN Control count

up-count

T1ST = 0

T1ST = 1

T1CN = 0

T1CN = 1

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GMS81C2012/GMS81C2020

50 JUNE. 2001 Ver 1.00

12.2 16-bit Timer / Counter Mode

The Timer register is bein g run with 16 bi ts. A 16-bit ti mer/ counter register T0, T1 are increased from 0000

until it

matches TDR0, TDR1 and then resets to 0000

. The match output generates Timer 0 interrupt not Timer 1 interrupt.

The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0].

In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively.

Figure 12-7 16-bit Timer/Counter

clear

0: Stop 1: Clear and start

T0ST

T0CN

TDR1 + TDR0

Comparator

TIMER 0 + TIMER 1 → TIMER 0 (16-bit)

Higher byte

Lower byte

(16-bit)

COMPARE DATA

T1 + T0 (16-bit)

(Not Timer 1 interrupt)

EDGE

BTCL

76543210

--T0CN

INITIAL VALUE: --000000

ADDRESS: 0D0

TM0

T0STT0CK0T0CK1CAP0 T0CK2

-- XXXX

X means don’t care

INITIAL VALUE: 00

ADDRESS: 0D2

TM1

X means don’t care

BTCL

76543210

16BITPOL T1CN T1STT1CK0T1CK1

PWM1E

CAP1

X1 XX11

EC0 PIN



XIN PIN

MUX

Prescaler

T0CK[2:0]

111

000 001

010







512



2048

011 100 101 110

DETECTOR

T0IF

TIMER 0 INTERRUPT

T0O PIN

F/F

Page 57

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 51

12.3 8-bit Compare Output (16-bit)

The GMS81C20xx has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, T1O) as shown in Figure 12-2 and Figure 12-7. Thus, pulse out is generated by the timer match. These operation is implemented to pin, T0O, PWM1O/T1O.

In this mode, the bit PWM1O/T1O of R5 function register (R5FUNC.6) should be set to "1", and the bit PWM1E of timer1 mode register (TM1) should be set to "0". In addi-

tion, 16-bit Compare output mode is available, also. This pin output the signal having a 50 : 50 duty square

wave, and output frequency is same as below equation.

12.4 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bi t CAP1 of tim er mode reg ister TM1 for Timer 1) as shown in Figure 12-8.

As mentioned above, not on ly Timer 0 but Timer 1 can also be used as a capture mode.

The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer in terrup t is gener ated wh en timer register T0 (T1) increases and matches TDR0 (TDR1).

This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer.

For example, in Figure 12-10, the pulse width of captured signal is wider than the timer data value (FF

) over 2 times. When external interrupt is occurred, the captured value (13

) is more little than wanted value. It can be ob-

tained correct value by counting the number o f timer overflow occurrence.

Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware.

Note:

The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation.

It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.

COMP

Oscillation F r equency

2 Prescaler Value T DR 1

)+(××

---------------------------------------------------------------------------------

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GMS81C2012/GMS81C2020

52 JUNE. 2001 Ver 1.00

Figure 12-8 8-bit Capture Mode

INT0IF

0: Stop 1: Clear and start

T0ST

INT0 INTERRUPT

T0CN

CDR0 (8-bit)

T0 (8-bit)

“01” “10”

“11”

Capture

IEDS[1:0]

EC0 PIN



XIN PIN

MUX

Prescaler

T0CK[2:0]

111

000 001

010

MUX

T1CK[1:0]

11 00









512



2048

011 100 101 110

INT0 PIN

INT1IF

0: Stop 1: Clear and start

T1ST

INT1 INTERRUPT

T1CN

CDR1 (8-bit)

T1 (8-bit)

“01” “10”

“11”

Capture

IEDS[1:0]

INT1 PIN

BTCL

76543210

--T0CN

INITIAL VALUE: --000000

ADDRESS: 0D0

TM0

T0STT0CK0T0CK1CAP0 T0CK2

-- XXXX

X means don’t care

INITIAL VALUE: 00

ADDRESS: 0D2

TM1

X means don’t care

BTCL

76543210

16BITPOL T1CN T1STT1CK0T1CK1

PWM1E

CAP1

X0 XXXX

Edge Detector

clear

Page 59

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 53

Figure 12-9 Input Capture Operation

Figure 12-10 Excess Timer Overflow in Capture Mode

Ext. INT0 Pin

Interrupt Request

TIME

coun

n-1

Capture

( Timer Stop )

Clear & Start

Interrupt Interval Period

Delay

( INT0F )

Ext. INT0 Pin

Interrupt Request

( INT0F )

This value is loaded to CDR0

Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H

Ext. INT0 Pin

Interrupt Request

( INT0F )

Interrupt Request

( T0F )

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GMS81C2012/GMS81C2020

54 JUNE. 2001 Ver 1.00

12.5 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits.

The clock source of the Timer 0 is selected either internal

or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 an d 16BIT of TM1

should be set to "1" respectively.

Figure 12-11 16-bit Capture Mode

0: Stop 1: Clear and start

T0ST

T0CN

Capture

CDR1 + CDR0

Higher byte

Lower byte

(16-bit)

CAPTURE DATA

TDR1 + TDR0

(16-bit)

INT0IF

INT0 INTERRUPT

“01” “10”

“11”

IEDS[1:0]

EC0 PIN



XIN PIN

MUX

Prescaler

T0CK[2:0]

111

000 001

010







512



2048

011 100 101 110

INT0 PIN

BTCL

76543210

--T0CN

INITIAL VALUE: --000000

ADDRESS: 0 D0

TM0

T0STT0CK0T0CK1CAP0 T0CK2

-- XXXX

X means don’t care

INITIAL VALUE: 00

ADDRESS: 0D2

TM1

X means don’t care

BTCL

76543210

16BITPOL T1CN T1STT1CK0T1CK1

PWM1E

CAP1

X1 XX11

Edge Detector

clear

Page 61

GMS81C2012/GMS81C2020

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Example 1:

Timer0 = 16-bit timer mode, 0.5s at 4MHz

LDM TM0,#0000_1111B;8uS LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<62500 ;8uS X 62500 LDM TDR1,#>62500 ;=0.5s SET1 T0E EI : :

Example 2:

Timer0 = 16-bit event counter mode

LDM R0FUNC,#0000_0100B;EC0 Set LDM TM0,#0001_1111B;Counter Mode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; SET1 T0E EI : :

Example 3:

Timer0 = 16-bit capture mode

LDM R0FUNC,#0000_0001B;INT0 set LDM TM0,#0010_1111B;Capture Mode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; LDM IEDS,#01H;Falling Edge SET1 T0E EI : :

12.6 PWM Mode

The GMS81C2020 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1.

In PWM mode, pin R5 6/P WM1O/ T1O out p uts up t o a 10bit resolution PWM output . This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register.

The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the dut y of the PWM output is determined by the T1PDR (PWM1 Duty Register) and PWM1HR[1:0] (bit1,0 of PWM1 High Register).

The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2].

And writes duty value to the T1PDR and the PWM1HR[1:0] same way.

The T1PDR is configured as a double buffering for glitchless PWM output. In Figure 12-12, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i .e. at t he beg inning of next duty cycle)

PWM Period = [PWM1HR[3:2]T1PPR] X Source Clock PWM Duty = [PWM1HR[1:0]T1PDR] X Source Clock

The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency vs. resolution.

Page 62

GMS81C2012/GMS81C2020

56 JUNE. 2001 Ver 1.00

If it needed more higher frequency of PWM, it should be reduced resolution.

The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM

output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00

", the PWM output is deter-

mined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM ou tput. How-

ever the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 12-14. As it were, the ab solute duty time is not changed in varying frequency. But the changed peri od value must greater than the duty value.

Figure 12-12 PWM Mode

Resolution

Frequency

T1CK[1:0]

= 00(250nS)

T1CK[1:0]

= 01(500nS)

T1CK[1:0]

= 10(2uS)

10-bit 3.9KHz 0.98KHZ 0.49KHZ

9-bit 7.8KHz 1.95KHz 0.97KHz 8-bit 15.6KHz 3.90KHz 1.95KHz 7-bit 31.2KHz 7.81KHz 3.90KHz

Table 12-2 PWM Frequency vs. Resolution at 4MHz

PWM1HR

ADDRESS : D5H RESET VALUE : ----0000

- - -

- PWM1HR3PWM1HR2PWM1HR1PWM1HR0

----

XXXX

MUX

T1CN

T1CK[1:0]

T1 ( 8-bit )

T1ST

0 : Stop 1 : Clear and Start

CLEAR

COMPARATOR

T1PDR(8-bit)

PWM1HR[1:0]

T1PPR(8-bit)

PWM1HR[3:2]

T1PDR(8-bit)

POL

PWM1O

R56/

PWM1O/T1O

T0 clock source

TM1

ADDRESS : D2H RESET VALUE : 00000000

POL 16BIT PWM1E CAP1

T1CK1 T1CK0 T1CN T1ST

X010

XXXX

[R5FUNC.6]

Period High

Duty High

Slave

Master

Bit Manipulation Not Available

X : The value "0" or "1" corresponding your operation.

[T0CK]

(2-bit)

Page 63

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 57

Figure 12-13 Example of PWM at 4MHz

Figure 12-14 Example of Changing the Period in Absolute Duty Cycle (@4MHz)

Source

PWM1O

02 03 04 05 7F

81 02 03

[POL=1] PWM1O

[POL=0]

Duty Cycle [ 80H x 250nS = 32uS ]

Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ]

PWM1HR = 0CH T1PPR = FFH T1PDR = 80H

T1CK[1:0] = 00 ( f

)

PWM1HR3 PWM1HR2

PWM1HR1 PWM1HR0

T1PPR (8-bit)

T1PDR (8-bit)

Period

Duty

11 FFH

00 80H

0100

clock

PWM1E

T1ST

T1CN

0100

3FF

Source

PWM1O POL=1

Duty Cycle

Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ]

PWM 1HR = 00H T1PPR = 0EH T1PDR = 05H

T1CK[1:0] = 10 ( 1uS )

02 03 04

06 08 09 0B 0C 0D

02 03 04

06 07 08 09

02 03 0407 0A

[ 05H x 2uS = 10uS ]

Duty Cycle

[ 05H x 2uS = 10uS ]

Period Cycle [ 0AH x 2uS = 20uS, 50KHz ]

Duty Cycle

[ 05H x 2uS = 10uS ]

Write T1PPR to 0AH

Period changed

clock

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13. ANALOG DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AV

of ladder resistance

of A/D module. The A/D module has two registers which are the control

register ADCM and A/D result register ADR. The register ADCM, shown in Figure 13-1, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O.

To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register. Also it is assigned analog input port by setting the bit AN-

SEL[11:8] in R7FUNC register. And selected the corresponding channel to be converted by setting ADS[3:0].

How to Use A/D Converter

The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block di agram of the A /D mo dule is shown in Figu re 13-2. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20 uS (at f

=4 MHz)

Figure 13-1 A/D Converter Control Register

BTCL

76543210

ADST

A/D status bit

Analog input channel select

INITIAL VALUE: -000 0001

ADDRESS: 0EA

ADCM

ADSF

A/D converter Enable bit 0: A/D converter module turn off and

current is not flow.

1: Enable A/D converter

R/W R/W R/W R/W R/W R

0000: Channel 0 (AN0) 0001: Channel 1 (AN1) 0010: Channel 2 (AN2) 0011: Channel 3 (AN3) 0100: Channel 4 (AN4) 0101: Channel 5 (AN5) 0110: Channel 6 (AN6) 0111: Channel 7 (AN7)

0: A/D conversion is in progress 1: A/D conversion is completed

A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware.

ADS1 ADS0ADS3 ADS2

INITIAL VALUE: Undefined

ADDRESS: 0EB

ADCR

A/D Conversion Data

BTCL

76543210

RRRR RR

ADEN

1000: Channel 8 (AN8) 1001: Channel 9 (AN9) 1010: Channel 10 (AN10) 1011: Channel 11 (AN11)

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Figure 13-2 A/D Block Diagram

R60/AN0

S/H

Sample & Hold

“0” “1”

ADEN

ADIF

A/D INTERRUPT

SUCCESSIVE

APPROXIMATION

CIRCUIT

ADR (8-bit)

A/D result register

ADDRESS: E9

RESET VALUE: Undefined

0000

ADS[3:0]

LADDER RESISTOR

8-bit DAC

R61/AN1

0001

R62/AN2

0010

R63/AN3

0011

R64/AN4

0100

R65/AN5

0101

R66/AN6

0110

R67/AN7

0111

ANSEL0

R6FUNC[7:0]

ANSEL1

ANSEL2

ANSEL3

ANSEL4

ANSEL5

ANSEL6

ANSEL7

R70/AN8

1000

R71/AN9

1001

R72/AN10

1010

R73/AN11

1011

ANSEL8

ANSEL9

ANSEL10

ANSEL11

R7FUNC[3:0]

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Figure 13-3 A/D Converter Operation Flow

A/D Converter Cautions

(1) Input range of AN11 to AN0 The input voltage of AN11 to AN0 should be within the

specification range. In particular, if a vo ltage above A

VDD

or below AVSS

is input (even if within the absolute maximum rating range), the con version value for t hat ch annel can n ot be in determinate. The conversion values of the ot her channels may also be affected.

(2) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid to noise on pins AVDD and AN11 to AN0. Since

the effect increases in proportion to the output impedance of the analog input source, it is recommended that

a capacitor be connected

externally as shown in Figure 13-4 in order to reduce noise.

Figure 13-4 Analog Input Pin Connecting Capacitor

(3) Pins AN11/R73 to AN8/R70 and AN7/R67 to AN0/ R60

The analog input pins AN11 to AN0 also function as input/ output port (PORT R7 and R6) pins. When A/D conversion is performed with any of pi ns AN11 t o AN0 select ed, be sure not to execute a PORT input instr uction while conversion is in progress, as this may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/ D conversion, the expe cted A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.

(4) AVDD pin input impeda n ce A series resistor string of approximately 10KΩ is connected be-

tween the AVDD

pin and the AVS S pin.

Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connectio n

to the

series resistor string between the AVDD

pin and the AVSS pin,

and there will be a large reference voltage error.

ENABLE A/D CONVERTER

A/D START ( ADST = 1 )

NOP

ADSF = 1

A/D INPUT CHANNEL SELECT

ANALOG REFERENCE SELECT

READ ADCR

YES

AN11~AN0

100~1000pF

Analog Input

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GMS81C2012/GMS81C2020

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14. SERIAL PERIPHERAL INTERFACE

The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The Se rial Peripheral Interf ace(SPI) is 8-bit

clock synchronous type and consists of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. The SOUT pin is designed to input and output. So Serial Peripheral Interface(SPI) can be operated with minimum two pin

Figure 14-1 SPI Block Diagram

XIN PIN

Prescaler

MUX

SCK[1:0]

00 01 10

SCLK PIN

SPI

Shift

Input shift register

SIOR

Clock

Octal

Serial communication Interrupt

SIOIF

SOUT

Internal Bus

SIOSF

Counter

SCK[1:0]

“11”

overflow

not “11”

Complete

Timer0 Overflow

IOSWIN

SIN PIN

IOSW

SOUT

IOSWIN

CONTROL

CIRCUIT

“0”

“1”

POL

Start

SIOST

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Serial I/O Mode Register(SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected. The serial transmission operation mode is decided by setting the SM1 and SM0, and the polarity of transfer clock is selected by setting the POL.

Serial I/O Data Register(S IOR) is a 8-bit shift regi ster. First LSB is send or is received. When receiving mode, serial input pin is selected by IOSW. The SPI allows 8-bits of data to be synchronously transmitted and received.

To accomplish communication, typically three pins are used:

- Serial Data In R54/SIN

- Serial Data Out R55/SOUT

- Serial Clock R53/SCLK

Figure 14-2 SPI Control Register

BTCL

76543210

IOSWPOL SIOST

Serial transmission status bit

Serial transmission Clock selection

INITIAL VALUE: 0000 0001

ADDRESS: 0E0

SIOM

SIOSF

Serial In put Pin Selection bit 0: SIN Pin Selection

1: IOSWIN Pin Selection

R/W R/W R/W R/W R/W R

00: f

XIN

01: f

XIN

16 10: TMR0OV(Timer0 Overflow) 11: External Clock

0: Serial transmission is in progress 1: Serial transmission is completed

Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware.

SCK1 SCK0SM1

SM0

R/W

Serial transmission Operation Mode 00: Normal Port(R55,R54,R53) 01: Sending Mode(SOUT,R54,SCLK) 10: Receiving Mode(R55,SIN,SCLK) 11: Sending & Receiving Mode(SOUT,SIN,SCLK)

INITIAL VALUE: Undefined

ADDRESS: 0E1

SIOR

BTCL

76543210

R/W R/W R/W R/W R/W R/W

R/W

Sending Data at Sending Mode Receiving Data at Receiving Mode

Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge

Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge

Received Data Latch at Falling Edge

R/W

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14.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycle of SCK, SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at falling edge of SCLK. And input data

is latched at rising edge of SCLK pin. When transmis sion clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and serial I/ O interrupt(IFSIO) occurred.

Figure 14-3 SPI Timing Diagram at POL=0

Figure 14-4 SPI Timing Diagram at POL=1

D1 D2 D3 D4 D6 D7D0 D5

SIOST

SCLK [R53]

(POL=0)

SOUT [R55]

SIN [R54]

SPIIF

(SPI Int. Req)

(IOSW=0)

D1 D2 D3 D4 D6 D7D0 D5

IOSWIN [R 5 5 ]

(IOSW=1)

SIOSF

(SPI Status)

D1 D2 D3 D4 D6 D7D0 D5

SIOST

SCLK [R53]

(POL=1)

SOUT [R55]

SIN [R54]

SPIIF

(SPI Int. Req)

(IOSW=0)

D1 D2 D3 D4 D6 D7D0 D5

IOSWIN [R 5 5 ]

(IOSW=1)

SIOSF

(SPI Status)

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64 JUNE. 2001 Ver 1.00

14.2 The method of Serial I/O

 Select transmission/receiving mode

Note:

When external clock is used, the frequency should

be less than 1MHz and recommended duty is 50%.

 In case of sending mode, write data t o be s end to SIOR.  Set SIOST to “1” to start serial transmission.

Note:

If both transmission mode is selected and transmis-

sion is performed simultaneously it would be made error.

 The SIO interrupt is generated at the completion of SIO and SIOSF is set to “1”. In SIO interrupt service routine, correct transmission should be tested.

 In case of receiving mode, the received data is acquired by reading the SIOR.

14.3 The Method to Test Correct Transmission

Figure 14-5 Serial Method to Test Transmission

Serial I/O Interrupt Service Routine

SE = 0

Write SIOM

Normal Operation

Overrun Error

Abnormal

SIOSF

- SE : Interrupt Enable Register Low IENL(Bit3)

- SR : Interrupt Request Flag Register Low IRQL(Bit3)

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15. BUZZER FUNCTION

The buzzer driver block consists of 6-bit binary counter, buzzer register BUR, and clock source selector. It generates square-wave which has very wide range frequency (480Hz ~ 250kHz at f

XIN

= 4MHz) by user software.

A 50% duty pulse can be output to R03/BUZO pin to use for piezo-electric buzzer drive

. Pin R03 is assigned for output port of Buzzer driver by setting the bit 3 of R0FUNC(address 0F4

) to “1”.

At this time, the pin R03 must be defined as

output mode (the bit 3 of R0IO=1). Example: 5kHz output at 4MHz.

LDM R0IO,#XXXX_1XXXB LDM BUR,#0011_0010B

LDM R0FUNC,#XXXX_1XXXB

X means don’t care

The bit 0 to 5 of BUR determines output frequency for buzzer driving.

Equation of frequency calcu lation is shown below .

BUZ

: Buzzer frequency

XIN

: Oscillator frequency

Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUR. Buzzer period value.

The frequency of output signal is controlled by the buzzer control register BUR.The bit 0 to bit 5 of BUR determine output frequency for buzzer driving.

Figure 15-1 Block Diagram of Buzzer Driver

Figure 15-2 R0FUNC and Buzzer Register

BUZ

XIN

2 DivideRatio BUR 1+()××

--------------------------------------------------------------------------- -

Prescaler

BUR

R03/BUZO PIN

R0FUNC

Internal bus line

R03 port data

XIN PIN

6-bit binary

[0DE

]

[0F4

]

0 1

F/F

Comparator

Compare data

6-BIT COUNTER

MUX

00 01 10 11

Port selection

BUR[5:0]

BUR

ADDRESS: 0DE

RESET VALUE: Undefined

WWWWWW

Source clock select 00:

8 01: ÷ 16 10: ÷ 32 11: ÷ 64

Buzzer Period Data

R03/BUZO Selection

R0FUNC

ADDRESS : 0F4

RESET VALUE : ---- 0000

0: R03 port (Turn off buzzer) 1: BUZO port (Turn on buzzer)

BUCK1

BUCK0

BUZO EC0 INT1 INT0

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Note:

BUR is undefined after rese t, so it m ust be in itialize d

to between 1

and 3FH by software.

Note that BUR is a write-only register.

The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00

until

it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is

shown as below table.

BUR [5:0]

BUR[7:6]

BUR [5:0]

BUR[7:6]

00 01 10 11 00 01 10 11

00 01 02 03 04 05 06 07

250.000

125.000

83.333

62.500

50.000

41.667

35.714

31.250

125.000

62.500

41.667

31.250

25.000

20.833

17.857

15.625

62.500

31.250

20.833

15.625

12.500

10.417

8.929

7.813

31.250

15.625

10.417

7.813

6.250

5.208

4.464

3.906

20 21 22 23 24 25 26 27

7.576

7.353

7.143

6.944

6.757

6.579

6.410

6.250

3.788

3.676

3.571

3.472

3.378

3.289

3.205

3.125

1.894

1.838

1.786

1.736

1.689

1.645

1.603

1.563

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

08 09 0A

0B 0C 0D

27.778

25.000

22.727

20.833

19.231

17.857

16.667

15.625

13.889

12.500

11.364

10.417

9.615

8.929

8.333

7.813

6.944

6.250

5.682

5.208

4.808

4.464

4.167

3.906

3.472

3.125

2.841

2.604

2.404

2.232

2.083

1.953

28 29 2A 2B 2C 2D 2E 2F

6.098

5.952

5.814

5.682

5.556

5.435

5.319

5.208

3.049

2.976

2.907

2.841

2.778

2.717

2.660

2.604

1.524

1.488

1.453

1.420

1.389

1.359

1.330

1.302

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

14.706

13.889

13.158

12.500

11.905

11.364

10.870

10.417

7.353

6.944

6.579

6.250

5.952

5.682

5.435

5.208

3.676

3.472

3.289

3.125

2.976

2.841

2.717

2.604

1.838

1.736

1.645

1.563

1.488

1.420

1.359

1.302

30 31 32 33 34 35 36 37

5.102

5.000

4.902

4.808

4.717

4.630

4.545

4.464

2.551

2.500

2.451

2.404

2.358

2.315

2.273

2.232

1.276

1.250

1.225

1.202

1.179

1.157

1.136

1.116

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

1B 1C 1D

10.000

9.615

9.259

8.929

8.621

8.333

8.065

7.813

5.000

4.808

4.630

4.464

4.310

4.167

4.032

3.906

2.500

2.404

2.315

2.232

2.155

2.083

2.016

1.953

1.250

1.202

1.157

1.116

1.078

1.042

1.008

0.977

38 39 3A 3B 3C 3D 3E 3F

4.386

4.310

4.237

4.167

4.098

4.032

3.968

3.907

2.193

2.155

2.119

2.083

2.049

2.016

1.984

1.953

1.096

1.078

1.059

1.042

1.025

1.008

0.992

0.977

0.548

0.539

0.530

0.521

0.512

0.504

0.496

0.488

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16. INTERRUPTS

The GMS81C20xx interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). Nine interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 16-2.

The External Interrupts INT0 and INT1 each can be transition-activated (1-to-0 or 0-to -1 transition) by selection IEDS. The flags that actu ally generate these in terrupts are bit INT0F and INT1F in register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated.

The Timer 0 ~ Timer 1 Interrupts are generated by TxIF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register.

The AD converter Interrupt is generated by ADIF whi ch is set by finishing the analog to digital conversion. The Watchdog timer Interrupt is generated by WDTIF which set by a match in Watchdog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer counter register.

The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 22), the interrupt enable

register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. Below table shows the Interrupt priority.

Vector addresses are shown in Figure 8-6 on page 24. Interrupt enable registers are shown in Figure 16-3. These registers are composed of interrupt enab le flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.

Figure 16-1 Interrupt Request Flag

Reset/Interrupt Symbol Priority

Hardware Reset External Interrupt 0 External Interrupt 1

Timer/Counter 0

Timer/Counter 1

ADC Interrupt

Watchdog Timer

Basic Interval Timer

Serial Communication

RESET

INT0

INT1 TIMER0 TIMER1

ADC

WDT

BIT SCI

1 2 3 4

5 6 7 8

R/W

INT0IF

INITIAL VALUE: 0000 ----

ADDRESS: 0E4

IRQH

INT1IF

MSB

T0IF T1IF

R/W

Timer/Counter 1 interrupt request flag

SPIF

R/W

ADIF

Serial Communication interrupt request flag

INITIAL VALUE: 0000 ----

ADDRESS: 0E5

IRQL

WDTIF

MSB LSB

BITIF

R/W

Timer/Counter 0 interrupt request flag

R/W R/W

Basic Interval imer interrupt request flag Watchdog timer interrupt request flag A/D Conver interrupt request flag

External interrupt 1 request flag External interrupt 0 request flag

LSB

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Figure 16-2 Block Diagram of Interrupt

Figure 16-3 Interrupt Enable Flag

Timer 0

INT1

INT0

INT0IF

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master Enable Flag

I-flag

IENL

Priority Control

I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.

[0E2H]

[0E3

]

[0E4

]

[0E5

]

INT1IF

T0IF

Timer 1

T1IF

A/D Converter

ADIF

SIOIF

BITIF

Watchdog Timer

Serial

BIT

WDTIF

Communication

T1E

R/W

INT0E

INITIAL VALUE: 0000 ----

ADDRESS: 0E2

IENH

INT1E

MSB

T0E

R/W

Timer/Counter 1 interrupt enable flag

SPIE

R/W

ADE

Serial Communication interrupt enable flag

INITIAL VALUE: 0000 ----

ADDRESS: 0E3

IENL

WDTE

MSB LSB

BITE

R/W

Timer/Counter 0 interrupt enable flag

R/W R/W

Basic Interval imer interrupt enable flag Watchdog timer interrupt enable flag A/D Convert interrupt enable flag

External interrupt 1 enable flag External interrupt 0 enable flag

0: Disable 1: Enable

VALUE

LSB

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16.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8

XIN

µs at f

MAIN

=4.19MHz) after the completion of the current instruction execution. The interrupt service task is term inated upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.

2. Interrupt request flag for the interr upt source accepted is cleared to “0”.

3. The contents of the program counter (return address) and the program status word are saved (pushed) ont o the stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter.

5. The instruction stored at the entry address of the interrupt service program is executed.

Figure 16-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced.

When nested interrupt service is required, the I -flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers ar e not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory

V.L.

System clock

Address Bus

SP SP-1

SP-2 V.H. New PC

V.L.

Data Bus

Not used

PCH PCL

PSW ADL OP codeADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step Interrupt Service Task

V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012

0E3

0FFE6

0FFE7

0E312

0E313

Entry Address

Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.

Vector Table Address

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area for saving registers. The following method is used to save/restore the general-

purpose registers. Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop instructions;

16.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in Figure 16-5.

Figure 16-5 Execution of BRK/TCALL0

INTxx: PUSH A

PUSH X PUSH Y

;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.

interrupt processing

POP Y POP X POP A RETI

;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN

main task

interrupt service task

saving registers

restoring registers

acceptance of interrupt

interrupt return

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

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JUNE. 2001 Ver 1.00 71

16.3 Multi Interrupt

If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced.

Figure 16-6 Execution of Multi Interrupt

However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interru pt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.

Example:

During Timer1 interrupt is in progress, INT0 in-

terrupt serviced without any suspen d.

TIMER1: PUSH A

PUSH X PUSH Y LDM IENH,#80H ;

Enable INT0 only

LDM IENL,#0 ;

Disable other

EI ;

Enable Interrupt

: : :

: : : LDM IENH,#0F0H ;

Enable all interrupts

LDM IENL,#0F0H

POP Y POP X POP A RETI

enable INT0

TIMER 1 service

INT0 service

Main Program service

Occur TIMER1 interrupt

Occur INT0

disable other

enable INT0 enable other

In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.

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16.4 External Interrupt

The external interrupt on INT0 and INT1 pins are edge triggered depending o n the edge select ion register IEDS (address 0F8

) as shown in Figure 16-7.

The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.

Figure 16-7 External Interrupt Block Diagram

INT0 and INT1 are mu ltiplexed with general I/O ports (R00 and R01). To use as an external interrupt pin, the bit of R4 port mode regis ter R0FUNC should be set to “1” correspondingly.

Example:

To use as an INT0 and INT1

: :

;

**** Set port as an input port R00,R01

LDM R0IO,#1111_1100B ;

;

**** Set port as an inter rupt port

LDM R0FUNC,#0000_0011B ;

;

**** Set Falling-edge Detection

LDM IEDS,#0000_0101B : : :

Response Time

The INT0 and INT1 edge are latched into INT0IF and INT1IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the reques ted service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.

Figure 16-8shows interrupt response timings.

Figure 16-8 Interrupt Response Timing Diagram

INT1IF

INT1 pin

INT1 INTERRUPT

IEDS

[0E6H]

INT0IF

INT0 pin

INT0 INTERRUPT

Edge selection Register

2 2

Interrupt goes active

Interrupt latched

Interrupt processing

Interrupt routine

8 f

XIN

max. 12 f

XIN

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Figure 16-9 R0FUNC and IEDS Registers

BTCL

WWWWWWWW

---

INT1

0: R00 1: INT0

INITIAL VALUE: ---- 0000

ADDRESS: 0F4

R0FUNC

INT0

EC0BUZO

0: R01 1: INT1

0: R02 1: EC0

0: R03 1: BUZO

LSBMSB

BTCL

R/W R/W R/W R/W

---IED0H

INITIAL VALUE: ---- 0000

ADDRESS: 0E6

IEDS

-IED0LIED1LIED1H

LSBMSB

Edge selection register

00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)

INT0

INT1

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17. Power Saving Mode

For applications where power consumption is a critical factor, device provides four kinds of power saving functions, STOP mode, Sub-active mode and Wake-up Timer

mode (Stand-by mode, Watch m ode). Table 17-1 shows the status of each Power Saving Mode.

The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding sta tus (WAKEUP) of

CKCTLR. We shows the release sources from each Power Saving Mode

Peripheral STOP Mode Sub-active Mode

Wake-up Timer Mode

Stand-by Mode W atch Mode

RAM Retain Retain Retain Retain

Control Registers Retain Retain Retain Retain

I/O Ports Retain Retain Retain Retain

CPU Stop Operation Stop Stop

Timer0 Stop Operation Operation Operation

Oscillation Stop Stop Oscillation Stop

Sub Oscillation Stop Oscillation Stop Oscillation

Prescaler Stop Oper ation

2048 only

Entering Condition

[WAKEUP]

00 11

Table 17-1 Power Saving Mode

Release Source STOP Mode

Sub-active

Mode

Wake-up Timer Mode

Stand-by Mode Watch Mode

RESET O O O O

RCWDT O O O O

EXT.INT0

OOOO

EXT.INT1

Timer0 X X O O

Table 17-2 Release Sources from Power Saving Mode

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17.1 Operating Mode

ACTIVE Mode

SCMR.1 = 0 f

: oscillation

SXI

: oscillation

cpu : f

SYS

tmr : f

SYS

peri : f

SYS

SCMR.0 = 0

SCMR.1 = 0

SCMR.1 = 1

SUB-ACTIVE Mode

SCMR.1 = 1

: stop

SXI

: oscillation

cpu : f

SUB

tmr : f

SUB

peri : f

SUB

SCMR.0 = 0/1

STANDBY Mode

SCMR.1 = 0 f

: oscillation

SXI

: oscillation cpu : stop tmr : ps11(f

)

peri : stop

CKCTLR[10]

STOP

TIMER0 EXT_INT RESET RC_WDT

WATCH Mode

SCMR.1 = 1 f

: stop

SXI

: oscillation cpu : stop tmr : ps11(f

SXI

)

peri : stop

CKCTLR[10]

STOP

TIMER0 EXT_INT RESET RC_WDT

STOP Mode

SCMR.2 = 1

: stop

SXI

: stop cpu : stop tmr : stop peri : stop

(SUB_CLK OFF)

EXT_INT RESET RC_WDT

CKCTLR[00]

STOP

EXT_INT RESET RC_WDT

CKCTLR[00]

STOP

System Clock Mode Register

SCMR

ADDRESS : FAH RESET VALUE : ---00000

- - - CS1 CS0 SUBON CLKSEL MAINOFF

CS[1:0] Clock selection enable bits

00 : fXI 10 : fXI ÷ 8 01 : f

÷ 4 11 : fXI ÷ 32

CLKSEL Clock selection bit

0 : Main clock selection 1 : Sub clock selection

SUBON Sub clock control bit

0: Off sub clock 1: On sub clock

MAINOFF Main clock control bit

0: On main clock 1: Off main clock

SXI

: sub clock frequency

SYS

: fXI,f

÷4

8,f

SUB

: f

SXI,fSXI

÷4

SXI

8,f

SXI

32 cpu : system clock tmr : timer0 clock peri : peripheral clock

CKCTLR = CKCTLR[6:5]

fXI : Main clock frequency

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17.2 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.

• The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode.

The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to “0”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)

In the Stop mode of operation, V

can be reduced to minimize power consumption. Care must be taken, however, to ensure that V

is not reduced before the Stop mode is

invoked, and that V

is restored to its normal op erating

level, before the Stop mode is terminated. The reset should not be activated before V

is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize.

Note:

After STOP instruction, at least two or more NOP in-

struction should be writ ten

Ex) LDM CKCTLR,#0000_1110B

STOP NOP NOP

In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determ ined by the hard ware operatio n of the STOP feature. This point should be little current flows when the input level is s table at the power voltage level (V

DD/VSS

); however, when the input lev el get s high -

er than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means.

Release the STOP mode

The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Contro l registers but do es not change the on-chip RAM. External interrupts allow both on-chip RAM and Co ntrol regi sters to reta in their v alues.

If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 17-1)

When exit from Stop mode by external interrupt, enough oscillation stabilization t ime is required to normal o peration. Figure 17-2 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00

until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.

By reset, exit from Stop mode is shown in Figure .

Figure 17-1 STOP Releasing Flow by Interrupts

IEXX

STOP

INSTRUCTION

STOP Mode

Interrupt Request

STOP Mode Release

I-FLAG

Interrupt Service Routine

INSTRUCTION

Master Interrupt

Enable Bit PSW[2]

Corresponding Inte rr upt Enable Bit (IENH, IENL)

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Figure 17-2 STOP Mode Release Timing by External Interrupt

Figure 17-3 Timing of STOP Mode Release by RESET

17.3 Wake-up Timer Mode

In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler(onl y 2048 divi ded ratio) and Timer0, all functions are stopped, but the on-c hip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers.

The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to “1”. (This register should be written by byte operation. If this register is set by bit ma nipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)

Note:

After STOP instruction, at least two or more NOP in-

struction should be written

Ex) LDM TDR0,#0FFH

LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP

In addition, the clock source of timer0 should be selected to 2048 divided ratio. Otherwise, the wake-u p function can not work. And the timer0 can be operated as 16-bit timer with timer1. (refer to timer function)The period of wakeup function is varied by setting the timer data register 0, TDR0.

Before executing Stop instruction, Basic Interval Timer must be set

Oscillator

pin)

BIT Counter

n+1 n+2 n+3

Normal Operation Stop Operation Normal Operation

tST > 20ms

External Interrupt

Internal Clock

Clear

STOP Instruction Executed

properly by software to get stabilization time which is longer than 20ms.

by software

STOP Mode

Time can not be control by software

Oscillator

(XI pin)

STOP Instruction Execution

Stabilization Time

= 64mS @4MHz

Internal

Clock

Internal

RESETB

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Release the Wake-up Timer mode

The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values.

If I-flag = 1, the normal in terrupt response takes place. I f I-

flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 17-1)

When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 17-4.

Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt

17.4 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Wat chdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers.

The Internal RC-Oscillated Watchdog Timer mode i s activated by execution of STOP instruction afte r setting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be u ndesired operation)

Note:

Caution: After STOP instruction, at le ast two or more

NOP instruction should be written

Ex)

LDM WDTR

,#1111_1111B

LDM CKCTLR

,#0010_1110B

STOP

NOP NOP

The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM

and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In

this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 17-5) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 17-6)

If I-flag = 0, the chip will resume execution starting wi th the instruction following the STOP instruction. It wil l not vector to interrupt service routine.(refer to Figure 17-1)

When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to norma l operation. Figure 17-5 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00

By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 17-6.

Wake-up Timer Mode

Oscillator

(XI pin)

STOP Instruction

Normal Operation

CPU

Clock

Request

Interrupt

Execution

Do not need Stabilization Time

( stop the CPU clock )

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Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt

Figure 17-6 Internal RCWDT Mode Releasing by RESET

17.5 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.

Note:

In the STOP operation, the power dissipation asso-

ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. Th is point sh ould be little c urrent flows when the input level is stable at the power voltage level (V

DD/VSS

); however, when the input level becomes higher

RCWDT Mode Normal Operation

Oscillator

(XI pin)

N+1N N+2

00 01 FE FF 00 00

N-1

N-2

Clear Basic Interval Timer

STOP Instruction Execution

Normal Operation

Stabilization Time

> 20mS

Internal

Clock

External Interrupt

BIT

Counter

Internal

RC Clock

( or WDT Interrupt )

Oscillator

(XI pin)

Internal

Clock

Internal

RC Clock

Time can not be control by software

STOP Instruction Execution

Stabilization Time

= 64mS @4MHz

Internal

RESET by WDT

RESET

RCWDT Mode

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than the power voltage level (by approximately 0.3V), a cu rrent begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a curr ent flow across th e ports input transistor, requiring it to fix the level by pull-up or other means.

It should be set properly in order that current flow through port doesn't exist.

First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship wi th external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current does n’t flow.

But input voltage lev el shou ld be V

or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not V

or VDD) is applied to input pin, there can be little

current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input m ode, then set to

output mode considering th ere is no current flow. Settin g to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-u p resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.

Figure 17-7 Application Example of Unused Input Port

Figure 17-8 Application Example of Unused Output Port

INPUT PIN

GND

Weak pull-up current flows

internal pull-up

INPUT PIN

Very weak current flows

OPEN

i=0

GND

When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.

OUTPUT PIN

GND

In the left case, much current flows from port to GND.

OFF

OUTPUT PIN

GND

In the left case, Tr. base current flows from port to GND.

i=0

OFF

OPEN

GND

OFF

To avoid power consumpt ion, there should be low output

OFF

to the port .

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18. OSCILLATOR CIRCUIT

The GMS81C20xx has two oscillation circuits internally. X

and X

OUT

are input and output for main frequency and

and SX

OUT

are input and output for sub frequency,

respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 18-1.

Figure 18-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

In addition, see Figure 18-2 for the layout of the crystal.

Note:

Minimize the wiring leng th. Do not allow the wiring to intersect with other signa l cond uctors . Do not all ow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of V

. Do not ground it to any g round pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 18-2 Layout of Oscillator PCB circuit

OUT

Recommend

C1,C2 = 20pF

OUT

External Clock

Open

OUT

External Oscillator RC Oscillator

(mask option)

Crystal or Ceramic Oscillator

OUT

Recommend C1,C2 = 100~120pF

32.768KHz

4.19MHz

Crystal Oscillator Ceramic Resonator

C1,C2 = 30pF

Refer to AC Characteristics

For selection R value,

EXT

OUT

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19. RESET

The GMS81C20xx have two types of reset generatio n procedures; one is an external reset input, the other is a watch-

dog timer reset. Table 19-1 shows on-chip hardwar e initialization by reset action.

Table 19-1 Initializing Internal Status by Reset Action

19.1 External Reset Input

The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. A fter reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 19-2.

Internal RAM is not affected by reset. When V

is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it.

When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFE

- FFFFH.

A connection for simple p ower-on-reset is shown in Figure 19-1.

Figure 19-1 Simple Power-on-Reset Circuit

Figure 19-2 Timing Diagram after RESET

19.2 Watchdog Timer Reset

Refer to “11. WATCHDOG TIMER” on page 41.

On-chip Hardware Initial Value On-chip Hardware Initial Value

Program counter (PC)

(FFFF

) - (FFFEH)

Peripheral clock Off RAM page register (RPR) 0 Watchdog timer Disable G-flag (G) 0 Control registers Refer to Table 8-1 on page 28 Operation mode Main-frequency clock Power fail detector Disable

7036P

10uF

10k

Ω

to the RESET pin

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilization Time

= 62.5mS at 4.19MHz

RESET

ADDRESS

DATA

1 2 3 4 5 6 7

Start

FE?ADL

ADH

BUS

RESET Process Step

= x 256

MAIN

÷1024

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20. POWER FAIL PROCESSOR

The GMS81C20xx has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the po wer fail detect circuitry. Whenever V

falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to “7.4 DC Electrical Characteristics for Standard Pins(5V)” on page 15.

In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Theref ore, af ter final development of user program, this function may be experimented or evaluated.

Note:

User can select po wer fail v olt age le vel ac cordi ng to

PFD0, PFD1 bit of CONFIG register(703F

) at the OTP

(GMS87C20xx) but

must select

the power fail v oltage leve l to define PFD option of “Mask Order & Verification Sheet” at the mask chip(GMS81C20xx). Because the power fail voltage level of mask chip (GMS81C20xx) is determined according to mask option.

Note:

If power fail voltage is selected to 3.0V on 3V oper-

ation, MCU is freezed at all the times.

Table 20-1 Power fail processor

Figure 20-1 Power Fail Voltage Detector Register

Power FailFunction OTP MASK

Enable/Disable PFDIS flag PFDIS flag Level Selection

PFS0 bit PFS1 bit

Mask option

PFDM

76543210

PFS

INITIAL VALUE: ---- -100

ADDRESS: 0EF

PFDR

R/W R/W R/W

PFDIS

Operation Mode

0 : Normal operation regardless of powe r fail 1 : MCU will be reset by power fail detection

Disable Flag

0: Power fail detection enable 1: Power fail detection disable

Power Fail Status

0: Normal operate 1: Set to “1” if power fail is detected

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Figure 20-2 Example S/W of RESET flow by Power fail

Figure 20-3 Power Fail Processor Situations

FUNTION

EXECUTION

INITIALIZE RAM DATA

PFS =1

RESET VECTOR

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

RAM CLEAR

YES

Skip the

initial routine

PFS = 0

Internal RESET

PFD

MAX

PFD

MIN

PFD

MAX

PFD

MIN

PFD

MAX

PFD

MIN

64mS

t <64mS

64mS

When PFR = 1

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21. OTP PROGRAMMING

21.1 DEVICE CONFIGURATION AREA

The Device Configuration Area can be programm ed or left unprogrammed to select device configuration such as security bit. Sixteen memory locatio ns (7030

~ 703FH) are designated

as Customer ID recording locat ions where the user can store check-sum or other customer iden tification n umbers. This area is not accessible during normal execution but is readable and writable during program / verify.

Figure 21-1 Device Configuration Area

DEVICE

7030

703F

CONFIG

CONFIGURATION

AREA

7031

7032

7033

7034

7035

7036

7037

7038

7039

703A

703B

703C

703D

703E

76543210

RCO

INITIAL VALUE: -000 -0-0

ADDRESS: 703F

CONFIG

LOCK

Code Protect

0 : Allow Code Read Out 1 : Lock Code Read Out

PFD Level Selection

00: PFD = 2.7V 01: PFD = 2.7V

External RC OSC Selection

0: Crystal or Resonator Oscillator 1: External RC Oscillator

PFS0PFS1R7X

10: PFD = 3.0V 11: PFD = 2.4V

R74, R75 Port Selection

0 : Sub Clock 1 : R74, R75

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Figure 21-2 Pin Assignment (64SDIP)

VDD

VPP

A_D0 A_D1 A_D2 A_D3

EPROM Enable

A_D7

A_D6

A_D5

A_D4

CTL2 CTL1 CTL0

VSS

R40 R42

R43 R50 R51 R52 R53 R54 R55 R56 R57

RESET

VSS

SXI

SXO

AVSS

R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73

AVDD

RA/Vdisp R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

R41

CTL3

64SDIP

Pin No.

User Mode EPROM MODE

Pin Name Pin Name Description

8 R53 CTL3 Read/Writ e Control

P_Vb

9 R54 CTL2 Address/Data Control

D_Ab

10 R55 CTL1 Write Control 1 11 R56 CTL0 Write Control 0 13 RESET

VPP P rogram ming Power (0V, 12V) 14 XIN EPROM Enable High Active, Latch Address in falling edge 15 XOUT NC No connection 16 VSS VSS

Connect to VSS

(0V)

20 R60 A_D0

Address Input

Data Input/Output

A8 A0 D0 21 R61 A_D1 A9 A1 D1 22 R62 A_D2 A10 A2 D2 23 R63 A_D3 A11 A3 D3 24 R64 A_D4

Address Input

Data Input/Output

A12 A4 D4 25 R65 A_D5 A13 A5 D5 26 R66 A_D6 A14 A6 D6 27 R67 A_D7 A15 A7 D7 33 VDD VDD

Connect to VDD

(6.0V)

Table 21-1 Pin Description in EPROM Mode (GMS81C2020)

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Figure 21-3 Timing Diagram in Program (Write & Verify) Mode

VPP

CTL0/1

 

High 8bit

DATA IN

DATA

OUT

LA DATA IN

DATA

OUT

EPROM Enable

CTL2

CTL3

A_D7~

VDD

DD1H

Address Input

Low 8bit Address Input

Write Mode

Verify

Low 8bit Address Input

Write Mode

Verify

A_D0

VDDS

VPPR

VPPS

DD1H

IHP

HLD1

HLD2

SET1

DLY1

DLY2

CD1

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GMS81C2012/GMS81C2020

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Figure 21-4 Timing Diagram in READ Mode

Parameter Symbol MIN TYP MAX Unit

Programming Supply Current

VPP

--50mA

Supply Current in EPROM Mode

VDDP

--20mA

VPP Level during Programming

IHP

11.5 12.0 12.5 V

VDD Level in Program Mode

DD1H

566.5V

VDD Level in Read Mode

DD2H

-2.7-V

CTL3~0 High Level in EPROM Mode

IHC

0.8V

--V

CTL3~0 Low Level in EPROM Mode

ILC

0.2V

A_D7~A_D0 High Level in EPROM Mode

IHAD

0.9V

--V

A_D7~A_D0 Low Level in EPROM Mode

ILAD

0.1V

VDD Saturation Time

VDDS

1--mS

VPP Setup Time

VPPR

--1mS

VPP Saturation Time

VPPS

1--mS

EPROM Enable Setup Time after Data Input

SET1

200 nS

EPROM Enable Hold Time after T

SET1

HLD1

500 nS

Table 21-2 AC/DC Requirements for Program/Read Mode

VPP

CTL0/1

High 8bit

DATA

LA DATA

DATA

EPROM Enable

CTL2

CTL3

A_D7~

VDD

DD2H

Address Input

Low 8bit Address Input

DATA

A_D0

VDDS

VPPR

VPPS

DD2H

IHP

HLD1

HLD2

SET1

DLY1

DLY2

CD1

CD2

CD1

Output

Low 8bit Address Input

High 8bit Address Input

Low 8bit Address Input

DATA Output

After input a high address,

output data following low address input

Anothe high address step

Page 95

GMS81C2012/GMS81C2020

JUNE. 2001 Ver 1.00 89

Figure 21-5 Programming Flow Chart

EPROM Enable Delay Time after T

HLD1

DLY1

200 nS

EPROM Enable Hold Time in Write Mode

HLD2

100 nS

EPROM Enable Delay Time after T

HLD2

DLY2

200 nS

CTL2,1 Setup Time after Low Address input and Data input

CD1

100 nS

CTL1 Setup Time before Data output in Read and Verify Mode

CD2

100 nS

Table 21-2 AC/DC Requirements for Program/Read Mode

START

Set VDD=V

DD1H

Set VPP=V

IHP

Verify blank

First Address Location

EPROM Write

N=1

Verify

Last address

Apply 3x program cycle

100uS program time

Next address location



Report

Programming failure

Verify of all address

VDD=6V & 2.7V

Report

Verify failure

Report

Programming OK

VDD=0V

END

FAIL

PASS

YES

FAIL

YES

PASS

VPP=0V

Verify

N=N+1

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Page 97

APPENDIX

Page 98

GMS800 Series

JUNE. 2001 i

A. CONTROL REGISTER LIST

Address Register Name Symbol R/W

Initial Value

Page

76543210

00C0 R0 port data register R0 R/W Undefined 35 00C1 R0 port I/O direction register R0IO W 0 0 0 0 0 0 0 0 35 00C2 R1 port data register R1 R/W Undefined 36 00C3 R1 port I/O direction register R1IO W 0 0 0 0 0 0 0 0 36 00C4 R2 port data register R2 R/W Undefined 36 00C5 R2 port I/O direction register R2IO W 0 0 0 0 0 0 0 0 36 00C6 R3 port data register R3 R/W Undefined 36 00C7 R3 port I/O direction register R3IO W - - 0 0 0 0 0 0 36 00C8 R4 port data register R4 R/W Undefined 36

00C9 R4 port I/O direction register R4IO W - - - - 0 0 0 0 36 00CA R5 port data register R5 R/W Undefined 37 00CB R5 port I/O direction register R5IO W 0 0 0 0 0 0 0 0 37 00CC R6 port data register R6 R/W Undefined 37 00CD R6 port I/O direction register R6IO W 0 0 0 0 0 0 0 0 37 00CE R7 port data register R7 R/W Undefined 38 00CF R7 port I/O direction register R7IO W - - 0 0 0 0 0 0 38

00D0 Timer mode register 0 TM0 R/W - -000000 45

00D1

Timer 0 register T0 R 00000000 46 Timer 0 data register TDR0 W 1 1 1 1 1 1 1 1 45 Capture 0 data register CDR0 R 0 0 0 0 0 0 0 0 52

00D2 Timer mode register 1 TM1 R/W 00000000 45

00D3

Timer 1 data register TDR1 W 1 1 1 1 1 1 1 1 45 PWM 1 period register T1PPR W 1 1 1 1 1 1 1 1 57

00D4

Timer 1 register T1 R 00000000 46 PWM 1 duty register T1PDR R/W 0 0 0 0 0 0 0 0 57 Capture 1 data register CDR1 R 0 0 0 0 0 0 0 0 52

00D5 PWM 1 High register PWM1HR W - - - - 0 0 0 0 56 00DE Buzzer driver register BUR W 1 1 1 1 1 1 1 1 65

00E0 Serial I/O mode register SIOM R/W 0 0 0 0 0 0 0 1 62

00E1 Serial I/O data register SIOR R/W Undefined 62

00E2 Interrupt enable register high IENH R/W 0 0 0 0 - - - - 68

00E3 Interrupt enable register low IENL R/W 0 0 0 0 - - - - 68

00E4 Interrupt request flag register high IRQH R/W 0 0 0 0 - - - - 67

00E5 Interrupt request flag register low IRQL R/W 0 0 0 0 - - - - 67

00E6 External interrupt edge selection register IEDS R/W - - - - 0 0 0 0 73 00EA A/D converter mode register ADCM R/W - 0 0 0 0 0 0 1 58

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GMS800 Series

ii JUNE. 2001

00EB A/D converter data register ADCR R Undefined 58

00EC

Basic interval timer mode register BITR R 0 0 0 0 0 0 0 0 40 Clock contr ol register CKCTLR W - 0 0 1 0 1 1 1 40

00ED

Watchdog Timer Register WDTR R 0 0 0 0 0 0 0 0 42

Watchdog Timer Register WDTR W 0 1 1 1 1 1 1 1 42 00EF Power fail detection register PFDR R/W - - - - - 1 0 0 83 00F4 R0 Function selection register R0FUNC W - - - - 0 0 0 0 35 00F5 R4 Function selection register R4FUNC W - - - - - - - 0 36 00F6 R5 Function selection register R5FUNC W - 0 - - - - - - 37 00F7 R6 Function selection register R6FUNC W 0 0 0 0 0 0 0 0 37 00F8 R7 Function selection register R7FUNC W - - - - 0 0 0 0 38 00F9 R5 N-MOS open drain selection register R5MPDR W 0 0 0 0 0 0 0 0 37 00FA System clock mode register SCMR R/W - - - 0 0 0 0 0 75 00FB RA port data register RA R Undefined 35

Address Register Name Symbol R/W

Initial Value

Page

76543210

Page 100

GMS800 Series

JUNE. 2001 iii

B. INSTRUCTION

B.1 Terminology List

Terminology Description

A Accumulator X X - register Y Y - register

PSW Program Status Word

#imm 8-bit Immediate data

dp Direct Page Offset Address

!abs Absolute Address

[ ] Indirect expression

{ } Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position

A.bit Bit Position of Accumulator

dp.bit Bit Position of Direct Page Memory

M.bit

Bit Position of Memory Data (000

~0FFFH)

rel Relative Addressing Data

upage

U-page (0FF00H~0FFFFH) Offset Address n Table CALL Number (0~15) + Addition

Upper Nibble Expression in Opcode

−

Subtraction

Multiplication

/ Division

( ) Contents Expression

∧

AND

∨

⊕

Exclusive OR ~NOT

←

Assignment / Transfer / Shift Left

→

Shift Right

↔

Exchange = Equal

≠

Not Equal

Bit Position

Datasheet GMS87C2020Q, GMS87C2020LQ, GMS87C2020K, GMS81C2020K, GMS81C2012Q Datasheet (HYNIX)

Specifications and Main Features

Frequently Asked Questions

User Manual