Datasheet GM71CS17800CLJ-5, GM71CS17800CJ-7, GM71CS17800CJ-6, GM71CS17800CJ-5, GM71CS17800CT-7 Datasheet (HYNIX)

The GM71C(S)17800C/CL is the new
generation dynamic RAM organized 2,097,152
x 8 bit. GM71C(S)17800C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)17800C/CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
GM71C(S)17800C/CL to be packaged in
standard 400 mil 28pin plastic SOJ, and standard
400mil 28 pin plastic TSOP II. The package size
provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.

Description Features

* 2,097,152 Words x 8 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time

(Unit: ns)

* Low Power
Active : 715/660/605mW (MAX)
Standby : 11mW (CMOS level : MAX)

0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L- version)
* Battery Back Up Operation (L- version)
* Self Refresh Operation (L-version)

Pin Configuration

2,097,152 WORDS x 8 BIT

CMOS DYNAMIC RAM

28 SOJ

(Top View)

VSS
I/O0
I/O1
I/O2
I/O3

1
2
3
4
5

WE

RAS

A10

A0
A1

7
8

9
10
11

6

A2
A3

VCC

12
13
14

VSS
I/O7
I/O6
I/O5
I/O4

24

25

26

27

28

OE

A8
A7
A6

18

19

20

21

22

CAS

23

A5
A4
VSS

15

16

17

NC A9

28 TSOP II

VSS
I/O0
I/O1
I/O2
I/O3

1
2
3
4
5

WE

RAS

A10

A0
A1

7
8

9
10
11

6

A2
A3

VCC

12
13
14

VSS
I/O7
I/O6
I/O5
I/O4

24

25

26

27

28

OE

NC

A8
A7
A6

18

19

20

21

22

CAS

23

A5
A4
VSS

15

16

17

A9

GM71C(S)17800C/CL-5
GM71C(S)17800C/CL-6

GM71C(S)17800C/CL-7

tRAC tCAC tRC tPC

5060131590

1103540

70 18 130 45

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Pin Description

Pin Function Pin Function

A0-A10
A0-A10

I/O0-I/O7

RAS

WE

VCC

VSS
NC

Address Inputs
Refresh Address Inputs
Data-In/Out
Row Address Strobe

Read/Write Enable

Power (+5V)
Ground
No Connection

Ordering Information

CAS Column Address Strobe

OE Output Enable

Absolute Maximum Ratings*

PT 1.0

Power Dissipation

W

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Symbol Parameter Rating Unit

TA
TSTG
VIN/OUT
VCC
IOUT

0 ~ +70

-55 ~ +125

50

Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current

C
C

V
V

mA

-1.0 ~ +7.0V

-1.0 ~ +7.0V

Recommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol Parameter Unit

VCC

VIH
VIL

Supply Voltage
Input High Voltage
Input Low Voltage

V
V
V

Max

5.5

6.0

0.8

Typ

5.0

-

-

Min

4.5

2.4

-1.0

Note: All voltage referred to Vss.

Type No. Access Time Package

GM71C(S)17800CJ/CLJ -5
GM71C(S)17800CJ/CLJ -6
GM71C(S)17800CJ/CLJ -7

50ns
60ns
70ns

400 Mil
28 Pin
Plastic SOJ

50ns
60ns
70ns

400 Mil
28 Pin
Plastic TSOP II

GM71C(S)17800CT/CLT -5
GM71C(S)17800CT/CLT -6
GM71C(S)17800CT/CLT -7

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)

Symbol Parameter Note

VOH

VOL

Output Level
Output "H" Level Voltage (IOUT = -5mA)

UnitMax

VCC

0.4

Min

2.4

0

Output Level
Output "L" Level Voltage (IOUT = 4.2mA)

ICC1

Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)

ICC2 Standby Current (TTL)

Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)

2-

ICC3 RAS Only Refresh Current

Average Power Supply Current
RAS Only Refresh Mode

(tRC = tRC min)

ICC4

ICC5 Standby Current (CMOS)

Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, Dout = High-Z)

1

-

ICC6 CAS-before-RAS Refresh Current

(tRC = tRC min)

150

-

IL(I)

10-10

IL(O)

10-10

Input Leakage Current
Any Input (0V<=VIN<= 6V)

Output Leakage Current

(DOUT is Disabled, 0V<=VOUT<= 6V)
Note: 1. ICC depends on output load condition when the device is selected.
ICC(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL.

3. Address can be changed once or less while CAS = VIH.

4. CAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
(tPC = tPC min)

110-50ns
60ns
70ns

100

90

-

-

-

110-50ns
60ns
70ns

100

90

-

-

100-50ns

60ns
70ns

90
85

-

110-50ns
60ns

70ns

-

-

100

90

ICC7

ICC8

V

V

mA

mA

uA

uA

uA

mA 1, 2

mA 2

mA 1, 3

mA

5-

Standby Current RAS = VIH

CAS = VIL
DOUT = Enable

mA 1

Battery Back Up Operating Current
(Standby with CBR Refresh)
(tRC=62.5us, tRAS<=0.3us, DOUT=High-Z)

500- 4,5uA

ICC9

uA

Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z)

300-

5

5

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Capacitance (VCC = 5V+/-10%, TA = 25C)

Symbol Parameter Note

CI1
CI2
CI/O

Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)

1
1

1, 2

Unit

pF
pF
pF

Max

5
7

7

Min

-

-

-

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. CAS = VIH to disable DOUT.

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Vss = 0V, Note 1, 2, 18)

Test Conditions

Input rise and fall times : 5 ns Output timing reference levels : 0.4V, 2.4V
Input timing reference levels : 0.8V, 2.4V Output load : 2TTL gate + CL (100 pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Symbol Parameter

Note

Max

Unit

Min MaxMin MaxMin

tRC

Random Read or Write Cycle Time 90 - 110 - 130 -

tRP

RAS Precharge Time 30 - 40 - 50 -

tRAS RAS Pulse Width 50 10,000

60

10,000

70

10,000

tCAS CAS Pulse Width 10,000 10,000 10,00015 18
tASR Row Address Set up Time 0 - - -0 0
tRAH Row Address Hold Time 7 - - -10 10
tASC Column Address Set-up Time 0 - - -0 0
tCAH Column Address Hold Time - - -10 15

tRCD

RAS to CAS Delay Time 17 45 45 5220 20 3

tRAD RAS to Column Address Delay Time 12 30 30 3515 15 4
tRSH RAS Hold Time 13 - - -15 18
tCSH

CAS Hold Time 50 - - -60 70

tCRP

CAS to RAS Precharge Time 5 - - -5 5

tT Transition Time (Rise and Fall) 3 50 50 503 3 7

tDZO OE Delay Time from DIN 0 - - -0 0
tDZC

CAS Delay Time from DIN 0 - - -0 0

GM71C(S)17800
C/CL-5

OE to DIN Delay Time 13 - - -15 18 5

6
6

tCP

CAS Precharge Time 7 - 10 - 10 -

tODD

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

13

7

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Read Cycle

Write Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin

tRAC

- 60 - 70

tCAC

- 15 - 18

tAA

- 30 - 35

tRCS

0 -

0

-

tRCH

0 - -0

- 15 - 18

GM71C(S)17800
C/CL-6

tOAC

GM71C(S)17800
C/CL-7

tRRH

5

- -

5

tRAL

30

-

-35

tOFF

15 15

-

-

tCAL

30 - -35

tCLZ

0 -

-

0

tOEZ

15 15

-

-

tOH

3 -

-

3

tOHO

3 -

-

3

tCDD

15

-

-18

Access Time from RAS
Access Time from CAS
Access Time from Address

Read Command Setup Time
Read Command Hold Time to CAS

Access Time from OE

Column Address to RAS Lead Time

Read Command Hold Time to RAS

Output Buffer Turn-off Time

Column Address to CAS Lead Time

CAS to Output in Low-Z

Output Buffer Turn-off Time to OE

Output Data Hold Time
Output Data Hold Time from OE

CAS to DIN Delay Time

MaxMin

- 50

- 13

- 25

0 ­0 -

- 13

GM71C(S)17800
C/CL-5

5

-

25 -

13

-

25

-

0 -

13-

3 ­3 -

13 -

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Symbol Parameter Note

Max

Unit

Min

tWCS

0 -

tWCH

10

-

tWP

10

-

tRWL

15

-

tCWL

15

-

tDS

0 -

tDH

10

-

MaxMin

0 -

15

-

10

-

18

-

-

18

-0

-

15

Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time

8,9

9,10,17

9,11,17

9

12
12

13
13

5

15

15

14

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

ns

Min

0 -

-

7

-

-

-

0 -

-

Max

GM71C(S)17800
C/CL-5

ns
ns
ns
ns
ns
ns

7

13
13

7

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Read- Modify-Write Cycle

Refresh Cycle

Symbol Parameter

Note

Max

Unit

Min MaxMin

155 - 181 -

85 - 98 ­40 - 46 ­55 - 63 - 14

14

14

15 - 18 -

Read-Modify-Write Cycle Time
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
OE Hold Time from WE

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

ns
ns
ns
ns
ns

Min

131 -

73 ­36 ­48 ­13 -

Max

GM71C(S)17800
C/CL-5

Symbol Parameter

Note

Max

Unit

Min MaxMin

5 - 5 - ns

10 - 10 - ns

5 - 5 - ns

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

0 - 0 - ns

10 - 10 - ns

CAS Setup Time
(CAS-before-RAS Refresh Cycle)

CAS Hold Time
(CAS-before-RAS Refresh Cycle)

RAS Precharge to CAS Hold Time

WE Setup Time
(CAS-before-RAS Refresh Cycle)

WE Hold Time
(CAS-before-RAS Refresh Cycle)

Min

5 -

10 -

5 -

GM71C(S)17800
C/CL-5

0 -

7 -

Max

Symbol Parameter

Note

Max

Unit

Min MaxMin

40 - 45 - ns

ns

35 - 40 -

ns

tRWC
tRWD
tCWD
tAWD
tOEH

tCSR

tCHR

tRPC

tWRP

tWRH

tPC
tRASP
tACP
tRHCP

ns

9,17- -

16

100,000 100,000

- ­35 40

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

Fast Page Mode Cycle

Access Time from CAS Precharge
RAS Hold Time from CAS Precharge

Fast Page Mode RAS Pulse Width

Fast Page Mode Cycle Time

Min

35 -

30 -

--30

GM71C(S)17800
C/CL-5

Max

100,000

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Fast Page Mode Read-Modify-Write Cycle

Symbol Parameter

Note

Max

Unit

Min MaxMin

tPRWC

85 - 96 - ns

tCPW

60 - 68 - ns

14

Fast Page Mode Read-Modify-Write
Cycle Time

WE Delay Time from CAS Precharge

GM71C(S)17800
C/CL-6

GM71C(S)17800
C/CL-7

GM71C(S)17800
C/CL-5

MaxMin

76 -

53 -

Self Refresh Mode ( L-version )

Symbol Parameter

Note

Max

Unit

Min MaxMin

GM71CS17800
CL-6

GM71CS17800
CL-7

tRASS

100 - 100 - µs

tRPS

110 - 130 - ns

tCHS

-50 - -50 - ns

RAS Pulse Width ( Self-refresh )
RAS Precharge Time ( Self-refresh )

CAS Hold Time ( Self-refresh )

Min

100 -

90 -

-50 -

Max

GM71CS17800
CL-5

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

AC Measurements assume tT = 5ns.
An initial pause of 200 is required after power up followed by a minimum of eight

initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before­RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.

Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.

Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.

Either tODD or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH (min) and VIL (max).
Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max). If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 2TTL loads and 100pF.(V

OH

=2.4V , V

OL

= 0.4V)
Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max).
Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition

and are not referred to output voltage levels.
tWCS, tRWD, tCWD and tAWD and tCPW are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min) or tCWD>=tCWD(min),
tAWD>=tAWD(min), and tCPW>=tCPW(min), the cycle is a read -modify- write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.

These parameters are referred to CAS leading edge in early write cycle and to WE leading edge
in a delayed write or a read modify write cycle.

tRASP defines RAS pulse width in fast page mode cycles.
Access time is determined by the longer of tAA or tCAC or tACP.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance): if tOEH<=tCWL, invalid data will be out at each I/O.

Notes:

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

us

GM71C17800C

GM71CS17800CL

Rev 0.1 / Apr’ 01

Package Dimensions

Unit: Inches (mm)

28 SOJ

28 TSOP (TYPE II)

0.405(10.29) MAX

0.394(10.03) MIN

0.455(11.56) MIN

0.471(11.96) MAX

0.730(18.54) MAX

0.720(18.28) MIN

0.020(0.50) MAX

0.012(0.30) MIN
TYP

0.050(1.27)

0.007(0.18) MAX

0.003(0.08) MIN

0.047(1.20)
MAX

0.041(1.05) MAX

0.037(0.95) MIN

0.024(0.60) MAX

0.016(0.40) MIN

0.008(0.21) MAX

0.004(0.12) MIN

0 ~ 5

o

0.395(10.03) MIN

0.435(11.06) MIN

0.445(11.30) MAX

0.366(9.30) MIN

0.375(9.55) MAX

0.025(0.64)
MIN

0.405(10.29) MAX

0.032(0.81) MAX

0.026(0.66) MIN

TYP

0.050(1.27)

0.020(0.50) MAX

0.015(0.38) MIN

0.148(3.75) MAX

0.128(3.25) MIN

0.710(18.04) MIN

0.720(18.30) MAX

0.083(2.10)

MIN