Datasheet GM71CS17403CT-7, GM71CS17403CT-5, GM71CS17403CLT-7, GM71CS17403CLT-6, GM71CS17403CLT-5 Datasheet (HYNIX)

GM71C(S)17403C/CL

4,194,304 WORDS x 4 BIT

CMOS DYNAMIC RAM

Description

The GM71C(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17403C/CL
offers Extended Data Out (EDO) Mode as a
high speed access mode. Multiplexed address
inputs permit the GM71C(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ
and a standard 300mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 5V+/-10% tolerance, direct
interfacing capability with high performance
logic families such as Schottky TTL.

Features

* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time

* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode

(Unit: ns)

tRAC tCAC tRC tHPC

GM71C(S)17403C/CL-6
GM71C(S)17403C/CL-7

60701518104

1242530

GM71C(S)17403C/CL-5

50 13 84 20

Pin Configuration

(Top View)

VCC
I/O1
I/O2

WE

RAS

NC

A10

A0
A1
A2
A3

VCC

VSS
I/O4
I/O3
CAS
OE
A9

A8
A7
A6
A5
A4
VSS

1

2
3

4
5
6

8
9

10
11
12
13 14

15

16

17

18

19

21

22

23

24

25

26

24(26) SOJ 24(26) TSOP II

VCC
I/O1
I/O2

WE

RAS

A11

A10

A0
A1
A2
A3

VCC

VSS
I/O4
I/O3
CAS
OE
A9

A8
A7
A6
A5
A4
VSS

1

2
3

4
5
6

8
9

10
11
12
13 14

15

16

17

18

19

21

22

23

24

25

26

Rev 0.1 / Apr’ 01

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Pin Description

Pin Function Pin Function

A0-A10
A0-A10

I/O1-I/O4 VCC

VSS

Address Inputs
Refresh Address Inputs
Data-input/Data-output
Row Address Strobe
Column Address Strobe

Read/Write Enable
Output Enable
Power (+5V)
Ground

Ordering Information

Absolute Maximum Ratings*

Symbol Parameter Rating Unit

TA
TSTG
VIN/VOUT
VCC
IOUT

0 ~ 70

-55 ~ 125

-1.0 ~ 7.0

-1.0 ~ 7.0
50

Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current

V
V

mA

PD

1.0Power Dissipation W

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

RAS
CAS

Recommended DC Operating Conditions (TA = 0 ~ 70C)

Symbol Parameter Unit

VCC

VIH

VIL

Supply Voltage
Input High Voltage
Input Low Voltage

V
V
V

Max

5.5

6.5

0.8

Typ

5.0

-

-

Min

4.5

2.4

-1.0

WE

OE

C
C

NC No Connection

Type No. Access Time Package

GM71C(S)17403CJ/CLJ-5
GM71C(S)17403CJ/CLJ-6
GM71C(S)17403CJ/CLJ-7

50ns
60ns
70ns

300 Mil
24(26) Pin
Plastic SOJ

GM71C(S)17403CT/CLT-5
GM71C(S)17403CT/CLT-6
GM71C(S)17403CT/CLT-7

300 Mil
24(26) Pin
Plastic TSOP II

50ns
60ns
70ns

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

DC Electrical Characteristics (VCC = 5.0V+/-10%, VSS = 0V, TOPR = 0 ~ 70C)

Symbol Parameter Note

VOH

VOL

Output Level
Output "H" Level Voltage (IOUT = -2mA)

UnitMax

VCC

0.4

Min

2.0

0

Output Level
Output "L" Level Voltage (IOUT = 2mA)

ICC1

Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling : tRC = tRC min)

ICC2

Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)

ICC3

RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode

(tRC = tRC min)

ICC4

ICC5

Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, DOUT = High-Z)

1

-

ICC6

CAS-before-RAS Refresh Current
(tRC = tRC min)

ICC7

150-

ICC8

IL(I)

10-10

IL(O)

10-10

Input Leakage Current
Any Input (0V<=VIN<= 6V)

Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 6V)

Note: 1. ICC depends on output load condition when the device is selected.
ICC(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL.

3. Address can be changed once or less while CAS = VIH.

4. CAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(tHPC = tHPC min)

120-50ns
60ns
70ns

110

100

-

2-

-

100-50ns
60ns

70ns

90
80

-

-

-

90-50ns

60ns

70ns

80
70

-

V

V

mA

uA

uA

-

Standby Current RAS = VIH

CAS = VIL
DOUT = Enable

5 1mA

Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, tRC = 62.5us, tRAS <= 0.3us,
DOUT = High-Z, CMOS interface)

350- uA 4,5

uA 5

mA 1, 2

mA

mA 2

mA 1, 3

mA

100-50ns

60ns

70ns

-

-

90
80

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Capacitance (VCC = 5V+/-10%, TA = 25C)

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 2, 18, 19)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Symbol Parameter Note

CI1
CI2
CI/O

Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)

1
1

1, 2

Unit

pF
pF
pF

Max

5
7
7

Min

-

-

-

Test Conditions
Input rise and fall times: 2 ns
Input timing reference levels: 0.8V, 2.4V

Output timing reference levels: 0.8V, 2.0V
Output load : 1 TTL gate + CL (100pF)
(Including scope and jig)

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. CAS = VIH to disable DOUT.

Symbol Parameter

Note

Max

Unit

Min MaxMin MaxMin

tRC

84 - 104 - 124 -

tRP

30 - 40 - 50 -

tRAS 50 10,000

60

10,000

70

10,000

tCAS 7 10,000 10,000 10,00010 13
tASR 0 - - -0 0
tRAH 7 - - -10 10
tASC 0 - - -0 0
tCAH 7 - - -10 13

tRCD

11 37 45 5214 14 3

tRAD 9 25 30 3512 12 4
tRSH 10 - - -13 13
tCSH

35 - - -40 45

tCRP

5 - - -5 5

tT 2 50 50 502 2 7

tDZO 0 - - -0 0
tDZC

0 - - -0 0

GM71C(S)17403
C/CL-5

13 - - -15 18 5

6
6

tCP

7 - 10 - 13 -

Random Read or Write Cycle Time
RAS Precharge Time

RAS Pulse Width
CAS Pulse Width
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time

RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time

Transition Time (Rise and Fall)

OE Delay Time from DIN
CAS Delay Time from DIN

OE to DIN Delay Time

CAS Precharge Time

tODD

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

21
22

24

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Read Cycle

Symbol Parameter

Note

Max

Unit

Min MaxMin

tRAC

- 60 - 70

tCAC

- 15 - 18

tAA

- 30 - 35

tRCS

0 -

0

-

tRCH

0 - -0

8,9,19

9,10,17,19

9,11,17,19

- 15 - 18 9

12

GM71C(S)17403
C/CL-6

tOAC

GM71C(S)17403
C/CL-7

tRRH

5

- -

5 12

tRAL

30

-

-35

tOFF

15 15 13

-

-

tCAL

18 - -23

tCLZ

0 -

-

0

tOEZ

15 15 13,23

-

-

tOH

3 -

-

3

tOHO

3 -

-

3

tCDD

15

-

-18

5

tRCHR
tOHR
tOFR
tWEZ

tWDD

tRDD

60

70

3

3

15

15

15

15

18

18

-

-

-

-

-

-

-

-

-

-

-

-

Access Time from RAS
Access Time from CAS
Access Time from Address

Read Command Setup Time
Read Command Hold Time to CAS

Access Time from OE

Read Command Hold Time to RAS

Column Address to RAS Lead Time

Output Buffer Turn-off Time

Column Address to CAS Lead Time

CAS to Output in Low-Z

Output Buffer Turn-off Time to OE

Output Data Hold Time
Output Data Hold Time from OE

CAS to DIN Delay Time

Read Command Hold Time from RAS
Output Data hold Time from RAS
Output Buffer turn off to RAS

Output Buffer turn off to WE

WE to DIN Delay Time

RAS to DIN Delay Time

MaxMin

- 50

- 13

- 25

0 ­0 -

- 13

GM71C(S)17403
C/CL-5

5

-

25 -

13

-

15

-

0 -

13-

3 ­3 -

13 ­50

3

13

13

13

-

-

-

-

-

-

ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns

ns

13

15 15

13,23

13

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Read- Modify-Write Cycle

Write Cycle

Symbol Parameter

MaxMin MaxMin

tWCS

0 - 0 -

tWCH

10

-

13

-

tWP

10

-

10

-

tRWL

10

-

13

-

tCWL

10

- -

13

tDS

0 - -0

tD

H

10

- -

13

Write Command Setup Time

Write Command Hold Time

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Setup Time

Data-in Hold Time

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

Min

0 -

7

-

7

-

-

-

0 -

-

Max

GM71C(S)17403
C/CL-5

7
7

7

Refresh Cycle

Symbol Parameter

MaxMin MaxMin

tCSR

5 - 5 -

tCHR

10 - 10 -

tRPC 5 - 5 -

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

tWRP

0 - 0 -

tWRH

10 - 10 -

CAS Setup Time

(CAS-before-RAS Refresh Cycle)

CAS Hold Time

(CAS-before-RAS Refresh Cycle)

RAS Precharge to CAS Hold Time

WE Setup Time

(CAS-before-RAS Refresh Cycle)

WE Hold Time

(CAS-before-RAS Refresh Cycle)

Min

5 -

7 -

5 -

GM71C(S)17403
C/CL-5

0 -

10 -

Max

Symbol Parameter

MaxMin MaxMin

tRWC 136 - 161 -
tRWD 79 - 92 -
tCWD 34 - 40 -
tAWD 49 - 57 -

Note

15

15

14

Note

Note

14

14

14

tOEH 15 - 18 -

Read-Modify-Write Cycle Time

RAS to WE Delay Time

CAS to WE Delay Time

Column Address to WE Delay Time

OE Hold Time from WE

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

Unit

ns
ns
ns
ns
ns
ns
ns

Unit

ns

ns

ns

ns

ns

Unit

ns
ns
ns
ns
ns

Min

111 -

67 ­30 ­42 ­13 -

Max

GM71C(S)17403
C/CL-5

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Symbol Parameter

Note

Max

Unit

Min MaxMin

25 - 30 -

35 - 40 -

9,17,19- -

16

100,000 100,000

- ­35 40

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

EDO Page Mode Cycle

20

3 3-

-

-

-

9

10 13

5 5

35

40

ns
ns
ns
ns
ns

ns

ns

ns

Min

20 -

30 -

-

-

GM71C(S)17403
C/CL-5

3 -

-

-

-

5

30

Max

100,000

7

Access Time from CAS Precharge

RAS Hold Time from CAS Precharge

EDO Page Mode RAS Pulse Width

EDO Page Mode Cycle Time

Output data Hold Time from CAS low

CAS Hold Time referred OE

CAS to OE Setup Time

Read command Hold Time
from CAS Precharge

Refresh

Symbol Parameter

Note

Max

Unit

Min MaxMin

32

-

-

ms

Refresh period

Refresh period (L -Series) 128- 128

- ms

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

32

2048
cycles

2048
cycles

EDO Page Mode Read-Modify-Write Cycle

Symbol Parameter

Note

Max

Unit

Min MaxMin

68 - 79 - ns

54 - 62 -

ns

14

EDO Page Mode Read-Modify-Write
Cycle Time

WE Delay Time from CAS Precharge

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

MaxMin

57 -

45 -

GM71C(S)17403
C/CL-5

MaxMin

32

-

128-

GM71C(S)17403
C/CL-5

30

Test Mode Cycle

∗19

Symbol Parameter

Unit

Max

Note

Min MaxMin

0 - 0 - ns

10 - 10 - ns

GM71C(S)17403
C/CL-6

GM71C(S)17403
C/CL-7

MaxMin

0 -

10 -

GM71C(S)17403
C/CL-5

tHPC
tRASP

tACP
tRHCP

tDOH
tCOL

tCOP
tRCHP

tREF

tREF

tHPRWC

tCPW

tWTS
tWTH

Test Mode WE Setup Time
Test Mode WE Hold Time

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

AC Measurements assume tT = 2ns.
An initial pause of 200us is required after power up followed by a minimum of eight

initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before­RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.

Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.

Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.

Either tODD or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL(max).
Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 1 TTL loads and 100pF.

Assume that tRCD>=tRCD(max) and tRAD<=tRAD(max).
Assume that tRCD<=tRCD(max) and tRAD>=tRAD(max).
Either tRCH or tRRH must be satisfied for a read cycles.

tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition

and are not referenced to output voltage levels.

tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycles is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

tRWD>=tRWD(min), the tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=
tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain

data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.

These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.

tRASP defines RAS pulse width in fast page mode cycles.

Access time is determined by the longer of tAA or tCAC or tACP

Notes:

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance); if tOEH<=tCWL, invalid data will be out at each I/O.

The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before­RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data
output pin is high state during test mode read cycle, then the device has passed. If they are not
equal, data output pin is a low state, then the device has failed. Refresh during test mode
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh
cycle or RAS-only refresh cycle.

In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.

tRAS(min) = tRWD(min) + tRWL(min) + tT in Read - Modify - Write cycle.
tCAS(min) = tCWD(min) + tCWL(min) + tT in Read - Modify - Write cycle.
tOFF and tOFR are determined by the later rising edge of RAS or CAS.
tCSH(min) can be achieved when tRCD <= tCSH(min) - tCAS(min).

18.

19.

20.

21.

22.

23.

24.

GM71C(S)17403C/CL

Rev 0.1 / Apr’ 01

Package Dimension

Unit: Inches (mm)

24(26) TSOP (TYPE II)

24(26) SOJ

0.669(17.00) MAX

0.661(16.80) MIN

0.295(7.49) MIN

0.329(8.38) MIN

0.340(8.64) MAX

0.147(3.75) MAX

0.128(3.25) MIN

0.020(0.50) MAX

0.015(0.38) MIN

TYP

0.050(1.27)

0.305(7.75) MAX

0.260(6.60) MIN

0.275(6.99) MAX

0.025(0.64)
MIN

0.032(0.81) MAX

0.026(0.66) MIN

0.085(2.16)
MIN

0.020(0.50) MAX

0.012(0.30) MIN
TYP

0.050(1.27)

0.007(0.18) MAX

0.003(0.08) MIN

0.047(1.20)
MAX

0.041(1.05) MAX

0.037(0.95) MIN

0.296(7.52) MIN

0.303(7.72) MAX

0.678(17.24) MAX

0.670(17.04) MIN

0.355(9.02) MIN

0.371(9.42) MAX

0.024(0.60) MAX

0.016(0.40) MIN

0.008(0.21) MAX

0.004(0.12) MIN

0 ~ 5

o