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GLT7256L08-8TS
Datasheet (G-LINK)
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Datasheet GLT7256L08-8TS, GLT7256L08-8J3, GLT7256L08-15TS, GLT7256L08-15J3, GLT7256L08-12TS Datasheet (G-LINK)

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Page 1
G-LINK
∗
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Features : Description :
GLT7256L08
Mar 2000(REV. 2.0)
∗ 32K x 8-bit organization. ∗ Very high speed – 8,10,12,15 ns. ∗ Low standby power.
Maximum 2mA for GLT7256L08.
∗ Fully static operation ∗ 3.3V±5% power supply. ∗ TTL compatible I/O. ∗ Three state output. ∗ Chip enable for simple memory expansion.
Available in 28 PIN 300 mil SOJ and TSOP packages.
GLT7256L08 are high performance 256K bit static random access memories organized as 32K by 8 bits and operate at a single 3.3 volt supply. Fabricated with G-Link Technology's very advanced CMOS sub­micron technology, GLT7256L08 offer a combination of features: very high speed and very low stand-by current. In addition, this device also supports easy memory expansion with an active LOW chip enable
(CE) as well as an active LOW output enable (OE) and three state outputs.
Pin Configurations : Function Block Diagram :
GLT7256L08
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
CE
OE
WE
WECEOE
0C to + 70
C
Capacitance
(1)
TA=25°°C,f=1.0MHZ :
Pin Descriptions:
Name Function
GLT7256L08
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Mar 2000(REV. 2.0)
A0 - A
14
Address Inputs Chip Enable Input
Output Enable Input Write Enable Input
I/OO - I/O V
CC
7
Data Input and Data Output +3.3V Power Supply
GND Ground
Truth Table:
Mode
Not Selected
X H X High Z
I/O Operation
(Power Down) Output Disabled H L H High Z
Read H L L Write L L X
D
D
OUT
IN
V Current
CC
I ,I
CCSB CCSB1
I
CC
I
CC
I
CC
Absolute Maximum Ratings: Operation Range:
Range Temperature
Commercial
Ambient Temperature
Under Bias...................................-10°C to +80°C
Storage Temperature(plastic)....-55°C to +125°C
Voltage Relative to GND.............-0.5V to + 4.6V
Data Output Current..................................50mA
Power Dissipation......................................1.0W
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
Sym. Parameter Conditions Max. Unit
C
Input Capacitance
IN
C
I/O
Input/Output Capacitance
G-Link Technology Corporation,Taiwan
- 2 -
o o
VIN=0V
V
I/O
=0V
V
CC
3.3V±5%
8
10pFpF
Page 3
G-LINK
CE
CCDR
(1)
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
DC Characteristics
Sym. Parameter Test Conditions Min. Typ
V V I
LI
I
LO
V V I
CC
I
CCSB
I
CCSB1
Guaranteed Input Low
IL
Voltage Guaranteed Input High
IH
Voltage Input Leakage Current VCC=Max., VIN=0V to V Output Leakage Current
Output Low Voltage VCC=Min.,IOL =8mA - - 0.4 V
OL
Output High Voltage VCC=Min., IOH =-4mA 2.4 - - V
OH
Operating Power Supply Current
Standby Power Supply Current
Power Down Power Supply Current
(2)
(2)
CC
VCC=Max.,CE≥V
VCC=Max., CE≤VIL, I
=0mA., F=F
I/O
VCC=Max., CE≥VIH, I
=0mA., F=F
I/O
max
max
IH
(3)
(3)
VCC=Max., CE≥VCC.-0.2V, VIN≥VCC. -0.2V or
-0.3 - +0.8 V
2.0 - VCC+0.3 V
-5 - 5
-5 - 5
- - -8 -10 -12 -15
- -
- - 2 mA
GLT7256L08
Mar 2000(REV. 2.0)
(1)
Max. Unit
110 100 90 90 mA
15 mA
µA µA
1. Typical characteristics are at VCC=3.3V, TA=25°C.
2. These are absolute values with repeat to device ground and all overshoots due to system or tester noise are included.
3. F
MAX
=1/tRC.
Data Retention (L version only)
Sym. Parameter Test Conditions Min. Typ
V
I t
CDR
t
R
1. CE≥VDR -0.2V, VIN≥VDR -0.2V or VIN≤0.2V.
2. tRC =Read Cycle Time.
VCC for Data retention
DR
≥VCC -0.2V,
2.0 - 3.6 V
VIN≥VCC -0.2V or VIN≤0.2V Data Retention Current VDR=2.0V 30 Chip Deselect to Data
Retention Waveform 0 - - ns Retention Time Operating Recovery Time t
RC
(2)
(1)
Max. Unit
- - ns
µA
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
CE
CE
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Low VCC Data Retention Waveform (CE Controlled)
AC Test Conditions
Input Pulse Levels 0V to 3.0V Input Rise and Fall Times
Timing Reference Level
AC Test Loads and Waveforms
3 ns
1.5V
Ω
GLT7256L08
Mar 2000(REV. 2.0)
Ω
Ω
Ω
AC Electrical Characteristics (over the commercial operating range) Read Cycle
-8 -10 -12 -15Parameter
Name Parameter
t t
t
ACS
t
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
RC AA
OE
OH
Read Cycle Time 8 10 12 15 Address Access Time 8 10 12 15 Chip Select Access Time, 8 10 12 15 Output Enable to Output Valid 5 6 7 8
Chip Select to Output Low Z, Output Enable to Output in Low Z 0 0 0 0
Chip Deselect to Output in High Z, Output Disable to Output in High Z 4 0 5 0 6 0 6
Output Hold from Address Change 3 3 3 3
Min Max Min Max Min Max Min Max
3 3 3 3
4 0 5 0 6 0 6
Ω
Unit
ns ns ns ns ns
ns ns
ns ns
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
WE
GLT7256L08
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Mar 2000(REV. 2.0)
Switching Waveform (Read Cycle)
READ CYCLE1
READ CYCLE 2
READ CYCL E 3
(1,2,4)
(1,3,4)
(1)
Notes:
1.
2. Device is continuously selected CE≤VIL.
3. Address valid prior to or coincident with CE transition low and/or transition high.
4. OE≤VIL.
5. Transition is measured 200mV from steady state with CL=5pF.
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
is High for READ Cycle.
G-Link Technology Corporation,Taiwan
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G-LINK
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
AC Electrical Characteristics (over the commercial operating range) Write Cycle
-8 -10 -12 -15Parameter
Name Parameter
t t
t t t t
t
WHZ
t
t t
WC CW
AS AW WP WR
DW
DH OW
Write Cycle Time 8 10 12 15 ns Chip Select to End of Write 6 8 10 12 ns Address Set up Time 0 0 0 0 ns Address Valid to End of Write 6 8 10 12 ns Write Pulse Width 6 8 10 12 Write Recovery Time 0 0 0 0 ns Write to Output in High Z 0 4 0 5 0 6 0 ns Data to Write Time Overlap 5 6 8 10 6 ns Data Hold from Write Time 0 0 0 0 ns End of Write to Output Active 0 0 0 0 ns
Switching Waveforms(Write Cycle)
WRITE CYCLE 1
(1)
Min Max Min Max Min Max Min Max
GLT7256L08
Mar 2000(REV. 2.0)
Unit
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
WE
WE
WE
WE
Switching Waveform (Write Cycle)
WRITE CYCLE 2
(1,6)
GLT7256L08
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Mar 2000(REV. 2.0)
Note:
1.
2. The internal write time of the memory is defined by the overlap CE low and WE low. All signals
3. TWR is measured from the earlier of CE or
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
5. If the CE low transition occurs simultaneously with the
6. OE is continuously low (OE=VIL).
7. D
8. D
9. If CE is low during this period, I/O pins are in the output state. Then the data input signals of
10. Transition is measured ±200mV from steady state with CL=5pF.
11. tCW is measured from CE going low to the end of write.
must be high during address transitions.
must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.
going high at the end of write cycle.
the outputs must not be applied.
low transitions or after the
transition, outputs remain in a high impedance state.
is the same phase of write data of this write cycle.
OUT
is the read data of next address.
OUT
opposite phase to the outputs must not be applied to them.
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
Parts Numbers (Top Mark) Definition :
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Ordering Informstion
Part Number Cycle Time Power Package
GLT7256L08-8J3 8ns Low Power SOJ 300mil 28L GLT7256L08-10J3 10ns Low Power SOJ 300mil 28L GLT7256L08-12J3 12ns Low Power SOJ 300mil 28L GLT7256L08-15J3 15ns Low Power SOJ 300mil 28L
GLT7256L08-8TS 8ns Low Power TSOP GLT7256L08-10TS 10ns Low Power TSOP GLT7256L08-12TS 12ns Low Power TSOP GLT7256L08-15TS 15ns Low Power TSOP
GLT7256L08
Mar 2000(REV. 2.0)
4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM
GLT 7 256 L 08 - 10 J3
-SRAM
064 : 8K 256 : 256K 512 : 512K 100 : 1M
-DRAM
10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note
CONFIG.
04 : x04 08 : x08 16 : x16 32 : x32
VOLTAGE
Blank : 5V L : 3.3V M : Mix Voltage
SPEED
-SRAM
10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns
-DRAM
35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns
PACKAGE
T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP
Note : CÙCDROM , HÙHDD. Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
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G-Link Technology Corporation,Taiwan
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G-LINK
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Package Information
300mil 28 pin Small Outline J-form Package (SOJ)
GLT7256L08
Mar 2000(REV. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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G-LINK
TSOP 28 pin Plastic Dual Inline Package
GLT7256L08
Ultra High Performance 3.3V 32K x 8 Bit CMOS STATIC RAM
Mar 2000(REV. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
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