Datasheet G571SZ, G571S1 Datasheet (GMT)

Global Mixed-mode Technology Inc.

G571

Single-Slot PCMCIA/CardBus Power Controllers

Features

Fully Integrated VCC and VPP Switching for Sin-



gle-Slot PC Card
Low r



Switch)
Compatible With Controllers From Cirrus, Ri-



coh, O

3.3V Low-Voltage Mode



Meets PC Card Standards



12V Supply Can Be Disabled Except During



12V Flash Programming
Short Circuit and Thermal Protection



Space-Saving 16 Pin SSOP



Compatible With 3.3V, 5V, and 12V PC Cards



Break-Before-Make Switching



Application

Notebook PC



Electronic Dictionary



Personal Digital Assistance



Digital still Camera



TM

Interface

(180-m

DS(on)

Micro, Intel, and Texas Instruments

2

5V VCC Switch and 3.3V VCC

ΩΩΩΩ

Description

The G571 PC Card power-interface switch provides an
integrated power-management solution for a single PC
Cards. All of the discrete power MOSFETs, a logic
section, current limiting, and thermal protection for PC
Card control are combined on a single integrated cir­cuit. The circuit allows the distribution of 3.3V, 5V,
and/or 12V card power, and is compatible with many
PCMCIA controllers. The current-limiting feature
eliminates the need for fuses, which reduces compo­nent count and improves reliability. Current-limit re­porting can help the user isolate a system fault to the
PC Card.
The G571 features a 3.3V low voltage mode that al­lows for 3.3V switching without the need for 5V. Bias
power can be derived from either the 3.3V or 5V inputs.
This facilitates low-power system designs such as
sleep mode and pager mode where only 3.3V is
available.
End equipment for the G571 includes notebook com­puters, desktop computers, personal digital assistants
(PDAs), digital cameras and bar-code scanners.

Pin Configuration

VCCD0

VCCD1

3.3V

3.3V

5V

5V

GND

Ordering Information

PART NUMBER TEMP. RANGE PACKAGE

G571SZ -40°C to +85°C SSOP-16L (150mil)

G571S1 -40°C to +85°C SSOP-16L (209mil)

G571

1

2

3

4

5

6

7

16

15

14

13

12

11

10

SHDN

VPPD0

VPPD1

AVCC

AVCC

AVCC

AVPP

Ver: 1.3

Feb 18, 2003

OC

9

8

12V

16Pin SSOP

1

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Typical PC-card Power-distribution application

AVCC

AVCC

AVCC

AVPP

12V

5V

5V

3.3V

3.3V

GND

G571

VCCD0

VCCD1

VPPD0

VPPD1

OC

SHDN

5V

3.3V

0.1µF

0.1µF

12V

1µF

1µF

0.1µF

0.1µF

To CPU

V

CC1

V

PC Card

CC2

Connector

V

PP1

V

PP2

PCMCIA

Controller

VCC_EN0
VCC_EN1
VPP_EN0

VPP_EN1

G571

CS

Shutdown Signal From CPU

Terminal Functions

TERMINAL

NAME NO.

3.3V 3,4 I 3.3V VCC input for card power and/or chip power if 5V is not present

5V 5,6 I 5V VCC input for card power and/or chip power

12V 9 I 12V VPP input card power

AVCC 11,12,13 O Switched output that delivers 0V, 3.3V, 5V, or high impedance to card

AVPP 10 O Switched output that delivers 0V, 3.3V, 5V, 12V or high impedance to card

GND 7 Ground

OC

SHDN

0VCCD

1VCCD

VPPD0 15 I Logic input that controls voltage of AVPP (see control-logic table)

VPPD1 14 I Logic input that controls voltage of AVPP (see control-logic table)

8 O Logic-level overcurrent reporting output that goes low when an overcurrent condition exists

16 I Logic input that shuts down the G571 and sets all power outputs to high-impedance state

1 I Logic input that controls voltage of AVCC (see control-logic table)

2 I

I/O DESCRIPTION

Logic input that controls voltage of AVCC (see control-logic table)

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Absolute Maximum Ratings Over Operating
Free-Air Temperature

Input voltage range for card power:
V

..........................................………..…….-0.3V to 7V

I(5V)

V

..........…...........................…….……... -0.3V to 7V

I(3.3V)

V

..........................................……..…….-0.3V to 14V

I(12V)

Logic input voltage....................…...........…….-0.3V to 7V

Output current (each card):I
I
Operating virtual junction temperature range, T

.........…..............…………..…….………-40°C to 150°C

Operating free-air temperature range,.T

*

Stresses beyond those listed under "absolute maximum ratings”may cause permanent damage to the device. These are stress

rating only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended op­erating conditions”is not implied. Exposure to absolute–maximum-rated conditions for extended periods may affect device reliability.

Note 1: ESD (electrostatic discharge) sensitive device. Proper ESD precautions are recommended to avoid performance degradation or

less of functionality.

(unless other-wise noted)*

...……internally limited

O (VCC).

............internally limited

O(VPP)

J.

A

………………………………………………………………………….

Storage temperature range, T

………………………...........….....……...-55°C to 150°C

STG

Lead temperature 1.6 mm (1/16 inch) from case for
10 seconds.……..……………………………….….260°C
Thermal resistance

θ

JA

SSOP-16L (150mil)…..…….……….…………178°C/W
SSOP-16L (209mil)…..….…………….………161°C/W
Power dissipation P

D

(T

+25°C)

≤

A

SSOP-16L (150mil)……………………………..700mW
SSOP-16L (209mil)..……………………………775mW
ESD…………………………..………………..……Note1

G571

-40°C to 85°C

Recommended Operating Conditions

V

0 5.25 V

I(5V)

Input voltage, VI

Output current

Operating virtual junction temperature, TJ -40 125

V

0 5.25 V

I(3.3V)

V

0 13.5 V

I(12V)

I

1.0 A

O(AVCC)

I

150 mA

O(AVPP)

MIN MAX UNIT

°C

(TA=25°C)

Electrical Characteristics

Power Switch

PARAMETER TEST CONDITIONS* MIN TYP MAX UNIT

5V to AVCC V

3.3V to AVCC V

Switch resistance

3.3V to AVCC V

5V to AVPP TJ = 25°C 6

3.3V to AVPP TJ = 25°C 6

12V to AVPP T

V

Clamp low voltage IPP at 10mA 0.8 V

O(AVPP)

V

Clamp low voltage ICC at 10mA 0.8 V

O(AVCC)

I

Leakage current

IKG

I

Input current

I

IPP high-impedance State TA = 25°C 1 10

I

high-impedance State TA = 25°C 1 10

CC

V

= 5V V

I(5V)

V

I(5V)

= 0V, V

= 3.3V V

I(3.3V)

Shutdown mode V

I

Short-circuit Output-

OS

current Limit

*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately.

O(AVCC)

I

O(AVPP)

0.8 2.2 A I

= 5V 130 180

I(5V)

= 5V, V

I(5V)

= 0V, V

I(5V)

= 25°C 6

J

=5V,V

O(AVCC)

=3.3V,V

O(AVCC)

O(AVCC)=VO(AVPP)

=3.3V 130 180

I(3.3V)

=3.3V 130 180

I(3.3V)

=12V 75 150

O(AVPP)

= 12V 75 150

O(AVPP)

= Hi-Z 1 3

output powered into a short to GND

120 400 mA

mΩ

Ω

µA

µA

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G571

Logic Section

PARAMETER TEST CONDITION* MIN MAX UNIT

Logic input current 1 µA

Logic input high level 2 V

Logic input low level 0.8 V

Logic output high level

= 5V, IO=1mA V

I(5V)

V

=0V,IO= 1mA,V

I(5V)

= 3.3V V

I(3.3V)

- 0.4

I(5V)

- 0.4

I(3.3V)

V

V

Logic output low level IO = 1mA 0.4 V

*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately.

Switching Characteristics **

PARAMETER TEST CONDITION MIN TYP MAX UNIT

t

Rise times, output

r

t

Fall times, output

f

V

V

V

V

VI(

t

Propagation delay

pd

(see Figure 1)

VI(

V

**Switching Characteristics are with CL = 147µF.

§ Refer to Parameter Measurement Information

2.6

O (AVCC)

10

O (AVPP)

7.5

O (AVCC)

38

O (AVPP)

VPPD0

(

I

) to V

1VCCD

) to V

0VCCD

) to V

O(AVPP)

O(AVCC)

O(AVCC)

(3.3V)

(5V)

ton 14

t

44

off

ton 3.2

17

t

off

ton 4.4

20

t

off

ms

ms

Parameter Measurement Information

AVPP

C

L

(V

V

I(VPPD1)

V

I(VPPD0)

O(AVPP)

=0V)

LOAD CIRCUIT

50%

t

on

VOLTAGE WAVEFORMS

90%

50%

t

off

10%

V

DD

GND

V

GND

I(12V)

V

I(VCCD1)

(V

I(VCCD0)=VDD

V

O(AVCC)

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

AVCC Propagation Delay and Rise Time With 1µF Load, 3.3V Switch 2
AVCC Propagation Delay and Fall Time With 1µF Load, 3.3V Switch 3
AVCC Propagation Delay and Rise Time With 147µF Load, 3.3V Switch 4
AVCC Propagation Delay and Fall Time With 147µF Load, 3.3V Switch 5
AVCC Propagation Delay and Rise Time With 1µF Load, 5V Switch 6
AVCC Propagation Delay and Fall Time With 1µF Load, 5V Switch 7
AVCC Propagation Delay and Rise Time With 147µF Load, 5V Switch 8
AVCC Propagation Delay and Fall Time With 147µF Load, 5V Switch 9
AVPP Propagation Delay and Rise Time With 1µF Load, 12V Switch 10
AVPP Propagation Delay and Fall Time With 1µF Load, 12V Switch 11
AVPP Propagation Delay and Rise Time W ith 147µF Load, 12V Switch 12
AVPP Propagation Delay and Fall Time With 147µF Load, 12V Switch 13

AVCC

LOAD CIRCUIT

50%

)

t

on

VOLTAGE WAVEFORMS

90%

C

50%

L

V

DD

t

off

10%

GND

V

I(3.3V)

GND

FIGURE

Ver: 1.3

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Parameter Measurement Information

VCCD0=3.3V

VCCD1

AVC C

Figure 2. AVCC Propagation Delay and Rise
Time With 1µF Load, 3.3V Switch

G571

VCCD0=3.3V

VCCD1

AVC C

Figure 3. AVCC Propagation Delay and Fall Time
With 1µF Load, 3.3V Switch

VCCD0=3.3V

VCCD1

AVC C

Figure 4. AVCC Propagation Delay and Rise Time

With 147µF Load, 3.3V Switch

VCCD0=3.3V

VCCD1

AVC C

Figure 5. AVCC Propagation Delay and Fall Time

With 147µF Load, 3.3V Switch

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A

A

A

A

Global Mixed-mode Technology Inc.

VCCD0

VCCD1=5V

VCC

Figure 6. AVCC Propagation Delay and Rise Time
With 1µF Load, 5V Switch

G571

VCCD0

VCCD1=5V

VCC

Figure 7. AVCC Propagation Delay and Fall Time
With 1µF Load, 5V Switch

VCCD0

VCCD1=5V

VCC

Figure 8. AVCC Propagation Delay and Rise Time

With 147µF Load, 5V Switch

Ver: 1.3

Feb 18, 2003

VCCD0

VCC

Figure 9. AVCC Propagation Delay and Fall Time
With 147µF Load, 5V Switch

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Global Mixed-mode Technology Inc.

VPPD0

AVPP

Figure 10. AVPP Propagation Delay and Rise
Time With 1µF Load, 12V Switch

VPPD1=0V

G571

VPPD0

VPPD1=0V

AVPP

Figure 11. AVPP Propagation Delay and Fall Time

With 1µF Load, 12V Switch

VPPD0

AVPP

Figure 12. AVPP Propagation Delay and Rise
Time With 147µF Load, 12V Switch

Ver: 1.3

Feb 18, 2003

VPPD1=0V

VPPD0

VPPD1=0V

AVPP

Figure 13. AVPP Propagation Delay and Fall Time

With 147µF Load, 12V Switch

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Application Information

Overview

PC Cards were initially introduced as a means to add
EEPROM (flash memory) to portable computers with
limited onboard memory. The idea of add-in cards
quickly took hold; modems, wireless LANs, Global
Positioning Satellite (GPS) systems, multimedia, and
hard-disk versions were soon available. As the num­ber of PC Card applications grew, the engineering
community quickly recognized the need for a standard
to ensure compatibility across platforms. To this end,
the PCMCIA (Personal Computer Memory Card Inter­national Association) was established, comprised of
members from leading computer, software, PC Card,
and semiconductor manufactures. One key goal was
to realize the “plug and play” concept, i.e. cards and

termi-

PP

,

CC

hosts from different vendors should be compatible.

PC Card Power Specification

System compatibility also means power compatibility.
The most current set of specifications (PC Card Stan­dard) set forth by the PCMCIA committee states that
power is to be transferred between the host and the
card through eight of the 68 terminals of the PC Card
connectors. This power interface consists of two V
two V

, and four ground terminals. Multiple VCC and

PP

ground terminals minimize connector-terminal and line
resistance. The two V

terminals were originally

PP

specified as separate signals but are commonly tied
together in the host to form a single node to minimize
voltage losses. Card primary power is supplied
through the V

terminals; flash-memory programming

CC

and erase voltage is supplied through the V
nals.

Designing for Voltage Regulation

The current PCMCIA specification for output voltage
regulation of the 5V output is 5% (250mV). In a typical
PC power-system design, the power supply will have
an output voltage regulation (V

) of 2% (100mV).

PS(reg)

Also, a voltage drop from the power supply to the PC
Card will result from resistive losses (V

) in the PCB

PCB

traces and the PCMCIA connector. A typical design
would limit the total of these resistive losses to less
than 1% (50mV) of the output voltage. Therefore, the
allowable voltage drop (V

) for the G571 would be the

DS

PCMCIA voltage regulation less the power supply
regula-tion and less the PCB and connector resistive
drops:

V

= V

DS

O(reg)-VPS(reg)-VPCB

Typically, this would leave 100mV for the allowable
voltage drop across the G571. The voltage drop is the
output current multiplied by the switch resistance of
the G571. Therefore, the maximum output current that
can be delivered to the PC Card in regulation is the
allowable voltage drop across the G571 divided by the
output switch resistance.

G571

I

max = V

O

The AVCC outputs deliver 1A continuous at 3.3V and

5.5V within regulation over the operating temperature
range. Using the same equations, the PCMCIA speci­fication for output voltage regulation of the 3.3V output
is 300mV. Using the voltage drop percentages for
power supply regulation (2%) and PCB resistive loss
(1%), the allowable voltage drop for the 3.3V switch is
200mV. The 12V outputs (AVPP) of the G571 can de­liver 150mA continuously.

Overcurrent and overtemperature protection

PC Cards are inherently subuect to damage from mis­handling. Host systems require protection against
short-circuited cards that could lead to power supply
or PCB trace damage. Even systems sufficiently ro­bust to withstand a short circuit would still undergo
rapid battery discharge into the damaged PC Card,
resulting in a sudden loss of system power. Most
hosts include fuses for protection. The reliability of
fused systems is poor, and requires troubleshooting
and repair, usually by the manufacturer. When fuses
are blown.

The G571 uses sense FETs to check for overcurrent
conditions in each of the AVCC and AVPP out­puts.Unlike sense resistors or polyfuses, these FETs
do not add to the series resistance of the switch;
therefore voltage and power losses are reduced.
Overcurrent sensing is applied to each output sepa­rately. When an overcurrent condition is detected, only
the power output affected is limited; all other power

outputs continue to function normally. The
cator, normally a ligic high, is a logic low when an
overcurrent condition is detected providing for initiation
of system diagnostics and/or sending a warning mes­sage to the user.

During power up, the G571 controls the rise time of
the AVCC and AVPP outputs and limits the current
into a faulty card or connector. If a short circuit is ap­plied after power is established (e.g., hot insertion of a
bad card ),current is initially limited only by the im­pedance between the short and the power supply. In
extreme cases, as much as 10A to 15A may flow into
the short before the current limiting of the G571 en­gages. If the AVCC or AVPP outputs are driven below
ground, the G571 may latch nondestructively in an off
state, Cycling power will reestablish normal operation.

Overcurrent limiting for the AVCC outputs is designed
to activate if powered up into a short in the range of

0.8A to 2.2A, typically at about 1.5A. The AVPP out­puts limit from 120mA to 400mA, typically around
200mA. The protection circuitry acts by linearly limiting
the current passing through the switch rather than ini­tiating a full shutdown of the supply. Shutdown occurs
only during thermal limiting.

DS

/ R

DS(on)

OC indi-

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Thermal limiting prevents destruction of the IC from
overheating if the package power dissipation rating
are exceeded. Thermal limiting disables power output
until the device has cooled.

12V Supply Not Required

Most PC Card switches use the externally supplied
12V to power gate drive and other chip functions,
which require that power be present at all times. The
G571 offers considerable power savings by using an
internal charge pump to generate the required higher
voltages from 5V input; Therefore, the external 12V
supply can be disable except when needed for
flash-memory functions, thereby extending battery
lifetime. Do not ground the 12V switch inputs when the
12-V input is not used. Additional power savings are
realized by the G571 during a software shutdown in

I(5V)

= 0).

which quiescent current drops to a maximum of 3µA.

3.3V Low Voltage Mode

The G571 will operates in a 3.3V low voltage mode
when 3.3V is only available input voltage (V
This allows host and PC Cards to be operated in
low-power 3.3V-only modes such as sleep modes or
pager modes. Note that in these operation mode, the
G571 will derive its bias current from the 3.3V input
pin and only 3.3V can be delivered to the PC Card.

Voltage Transitioning Requirement

PC Cards are migrating from 5V to 3.3V to minimize
power consumption, optimize board space, and in­crease logic speeds. The G571 meets all combina­tions of power delivery as currently defined in the
PCMCIA standard. The latest protocol accommodates
mixed 3.3V/5V systems by first powering the card with
5V, then polling it to determine its 3.3V compatibility.
The PCMCIA specification requires that the capacitors
on 3.3V-compatible cards be discharged to below

G571

0.8V before applying 3.3V power. This functions as a
power reset and ensures that sensitive 3.3V circuitry is
not subjected to any residual 5V charge. The G571
offer a selectable V
dance with PCMCIA 3.3V/5V switching specifications.

Output Ground Switches

PC Card specification requires that V
within 100 ms. PC Card resistance can not be relied
on to provide a discharge path for voltages stored on
PC Card capacitance because of possible
high-impedance isolation by power-management
schemes.

Power Supply Considerations

The G571 has multiple pins for each of its 3.3V, and
5V power inputs and for switched V
individual pin can conduct the rated input or output
current. Unless all pins are connected in parallel, the
series resistance is significantly higher than that
specified, resulting in increased voltage drops and lost
power. it is recommended that all input and output
power pins be paralleled for optimum operation.

To increase the noise immunity of the G571, the
power supply inputs should be bypassed with a 1µF
electrolytic or tantalum capacitor paralleled by a

0.047µF to 0.1µF ceramic capacitor. It is strongly
recommended that the switched outputs be bypassed
with a 0.1µF or larger, ceramic capacitor; doing so
improves the immunity of the G571 to electrostatic
discharge (ESD). Care should be taken to minimize
the inductance of PCB traces between the G571 and
the load. High switching currents can produce large
negative voltage transients, which forward biases sub­strate diodes, resulting in unpredictable performance.
Similary, no pin should be taken below -0.3V.

and VPP ground state, in accor-

CC

be discharged

CC

outputs. Any

CC

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3.3V

3.3V

12V

CPU

Controlle r

Global Mixed-mode Technology Inc.

G571

5V

5V

3

4

5

6

9

16

15

14

1
2

8

S3

S1

S2

cs

Internal

Current Monitor

SHDN

VPPD0
VPPD1
VCCD0
VCCD1

OC

cs

GND

See Note A

Thermal

S5

S6

S4

G571

13

12

11

10

17

51

18

52

Card B

V

CC1

V

CC2

V

PP1

V

PP2

7

Note A: MOSFET switch S6 has a back-gate diode from the source to the drain. Unused switch inputs should

never be grounded.

Figure 10. Internal Switching Matrix

G571 Control Logic

AVPP

CONTROL SIGNALS INTERNAL SWITCH SETTINGS OUTPUT

SHDN

1 0 0 CLOSED OPEN OPEN 0V

1 0 1 OPEN CLOSED OPEN AVCC*

1 1 0 OPEN OPEN CLOSED VPP(12V)

1 1 1 OPEN OPEN OPEN Hi-Z

0 × × OPEN OPEN OPEN Hi-Z

* Output depends on AVCC

AVCC

CONTROL SIGNALS INTERNAL SWITCH SETTINGS OUTPUT

SHDN

1 0 0 CLOSED OPEN OPEN 0V

1 0 1 OPEN CLOSED OPEN 3.3V

1 1 0 OPEN OPEN CLOSED 5V

1 1 1 CLOSED OPEN OPEN 0V

0 × × OPEN OPEN OPEN Hi-Z

VPPD0 VPPD1 S4 S5 S6 AVPP

VCCD1

VCCD0

S1 S2 S3 AVCC

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Package Information

7

(4X)

°

y

G571

C

E1

E

L

D

θ

A2 A

e

b

A1

16 Pin SSOP Package (150mil)

Note:

1. Package body sizes exclude mold flash and gate burrs

2. Dimension L is measured in gage plane

3. Tolerance 0.10mm unless other wise specified

4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact.

SYMBOLS

A 1.35 1.60 1.75 0.053 0.064 0.069

A1 0.10 ----- 0.25 0.004 ----- 0.010

A2 ----- 1.45 ----- ----- 0.057 -----

b 0.20 0.25 0.30 0.008 0.010 0.012

C 0.19 ----- 0.25 0.007 ----- 0.010

D 4.80 ----- 5.00 0.189 ----- 0.197

E 5.80 ----- 6.20 0.228 ----- 0.244

E1 3.80 ----- 4.00 0.150 ----- 0.157

e ----- 0.64 ----- ----- 0.025 -----

L 0.40 ----- 1.27 0.016 ----- 0.050

y ----- ----- 0.10 ----- ----- 0.004

θ

MIN NOM MAX MIN NOM MAX

0º ----- 8º 0º ----- 8º

DIMENSION IN MM DIMENSION IN INCH

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G571

θ

θ

L

L1

L1

E

E

E1

E1

D

D

A

A2

A2

A

A2

A

0.10MM C

0.10MM C

0.10MM C

e

e

e

b

b

b

Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not

Note:

A1

A1

A1

L

R1

R1

c

c

exceed 0.006 inch per side.

16 Pin SSOP Package (209mil)

SYMBOL

A ----- ----- 2.00 ----- ----- 0.079
A1 0.05 ----- ----- 0.002 ----- ----­A2 1.65 1.75 1.85 0.065 0.069 0.073

b 0.22 0.30 0.33 0.009 0.012 0.013
c 0.09 0.15 0.21 0.004 0.006 0.008

e 0.65 BASIC 0.026 BASIC
D 5.90 6.20 6.50 0.232 0.244 0.256
E 7.40 7.80 8.20 0.291 0.307 0.323

E1 5.00 5.30 5.60 0.197 0.209 0.220

L 0.55 0.75 0.95 0.022 0.030 0.038

L1 1.25 REF 0.049 REF

R1 0.09 ----- ----- 0.004 ----- 04

θ

JEDEC MO-150 (AC)

MIN. NOM. MAX. MIN. NOM. MAX.

0º 4º 8º 0º 4 8º

DIMENSION IN MM DIMENSION IN INCH

Taping Specification

Feed Direction

Typical SSOP Package Orientation

Typical SSOP Package Orientation

Feed Direction

GMT Inc. d oes not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.

Ver: 1.3

Feb 18, 2003

12

TEL: [phone]

http://www.gmt.com.tw