Datasheet FX623P Datasheet (Consumer Microcircuits Limited)

CML Semiconductor Products

PRODUCT INFORMATION

FX623

Features

Measures Call Progress Tone
Frequencies

[‘Busy’, ‘Dial’, ‘Fax-Tone’ etc.]

Telephone, PABX, Fax and
Dial-Up Modem Applications

Low-Power Requirement
(600µA at 3.3 Volts
for Line-Powered Applications

SIGNAL IN

CHIP SELECT

LIMITER

)

TYP

DIGITAL

FILTER

Call Progress Tone Decoder

Publication D/623/3 July 1994

Provisional Issue

Custom Tone Decoder
[13 Call-Progress Frequencies
Recognized]

Operates to a 3.579545MHz
Telephone System Clock

Operates Under Simple Logic
or µProcessor System Control

V

DD

MEASUREMENT

AND

DECODE

V

SS

XTAL/CLOCK

XTAL

HOLD

PURS

Fig.1 Functional Block Diagram

XTAL/CLOCK
OSCILLATOR

CONTROL

CIRCUITRY

Clocks

TIMER

Brief Description

The FX623 is a low-power decoding microcircuit that
measures the frequency of telephone system call
progress tones.

With progress signals input from the telephone line,
this single-chip product is programmed to recognize up
to thirteen of the World's most commonly used
call-progress frequencies, analyze signal quality and
present the measured result as a 4-bit parallel data
word at the tri-state Data Output.

Using the parallel information from the FX623, the
host system suitably configured, can recognize such
call progress information as: ‘Dial’, ‘Busy’, ‘Number
Unobtainable’, ‘Ringing’ and Fax/Modem system
signals.

Clocks

DATA

CHANGE

FX623

DATA

OUTPUTS

IRQ

Q0
Q1
Q2
Q3

volt power supply, the

[MIN]

OUTPUT

LATCHES

This information can then be employed in telephone
applications (simple or complex) to control telephone
operations. The data output will require a suitable
software format to analyze the frequency information
from the FX623.

Requiring only a single 3.0
FX623 may be line-powered and will operate under
simple logic or system µProcessor control using the
'Data-Change, 'Hold' and 'Chip-Select' functions.

The FX623, whose small size and low power
consumption makes it ideal for remote applications,
requires a 3.579545MHz telephone system clock or Xtal
input, is available in a 16-pin plastic DIL package.

Pin Number Function

FX623P

10

11

1
2
3
4

5

Q3:
Q2:
Q1:
Q0:

V

Data Outputs: A 4-bit parallel data word, forming a HEX character representing the

decoded tone frequency. This word is output after a successful decode. Table 1 details the
Hex character output codes for the relevant decoded tone frequencies. Upon power-up this
output is set to ‘E

: Positive supply rail. A minimum supply voltage of 3.0 volts is required. Levels and voltages within

DD

’, but no Data Change pulse generated. These are tri-state outputs.

H

this decoder are dependent upon this supply.

6

Signal In: The composite audio input. Signals to this pin should be a.c. coupled. The d.c. bias of the

limiter section is set internally; this pin should not be loaded with any other circuitry.

7

8

9

No internal connection. Leave open circuit.

Xtal: The output of the on-chip clock oscillator inverter.

No internal connection. Leave open circuit.

Xtal/Clock: The input to the clock oscillator inverter. A 3.579545MHz Xtal or externally derived clock
should be connected here (see Figure 2).

V

: Negative supply rail (GND).

SS

12

13

14

15

Hold: An input to control the Output Latch condition; employed in combination with the Data Change

output to facilitate, if required, Interrupt and/or handshake operations with a µProcessor.
With Hold placed “Low”, with a tone input, the Data Change output will be held “High” at the next data
change, and the current output code is locked in the Output Latches regardless of any changes to the
input signal.
The output code remains as held until this input is returned “High” (see Figure 3). Whilst this input is
“High” the output data, Q0 - Q3, cycles normally with the input audio.
This pin has an internal 1.0MΩ pullup resistor.

PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic “1” level is required at this pin
for a duration of at least 2.5mS after the Xtal/Clock input and full V

levels are applied.

DD

The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the
time constant of components should be increased accordingly.

IRQ: Interrupt Request. An output for µProcessor operation; normally “High” this output is latched
“Low” when an internal data change occurs if the Chip Select input is “High”. This output is reset
(“High”) the when Chip Select line is taken “Low”.
To permit “wire-OR” connection with other peripherals, this output has a low-impedance when “Low”
and a high-impedance when “High”.

CS: Chip Select- A controlling function. When held “High” the Data Outputs Q0, Q1, Q2 and Q3 and
the Data Change output are disabled.
When taken “Low” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are enabled;
the Interrupt Request (IRQ) is reset (“High”) when CS is taken “Low”. See Figures 3 and 4.

16

Data Change: A positive-going pulse is generated at this output when the data changes (Tone or

N

OTONE). New tone-data is presented to the Q0, Q1, Q2 and Q3 Data Outputs if the Hold input is set

“High”. This is a tri-state output.

2

Application Information

C

5

V

SS

DAT A OUTPUTS

A HEX Code
Output representing
the decoded tone
frequency

See Table 1

COMPOSITE SIGNAL IN

Q3
Q2
Q1
Q0

C

2

V

DD

SIGNAL IN

XTAL

C

3

1
2
3
4
5
6
7
8

V

DD

FX623P

X

1

DAT A CHANGE

16

CS

15

IRQ

14

PURS

13

HOLD

12

V

11

10

SS

XTAL/CLOCK

9

R

2

C

4

C

1

R

1

Fig.2 Recommended External Components

Band Edges (Hz) Nominal

Hex Output Code Lower Upper Centre

Character Q3 Q2 Q1 Q0 Edge Edge Freq.

0 0000 364 386
1 0001 488 520
2 0010 520 580
3 0011 580 618
4 0100 386 412
5 0101 412 436
6 0110 436 463
7 0111 463 487
8 1000 900 1008

9 1001 1273 1325
A 1010 1350 1455
B 1011 1750 1855
C 1100 2062 2140
D 1101 frequency not guaranteed
E 1110 frequency not guaranteed
F 1111 NOTONE

Table 1 Tone Decode Frequencies

375
500
550
600
400
425
450
475

950
1300
1400
1800
2100

V

SS

Component Value

R

1

R

2

C

1

C

2

C

3

C

4

C

5

X

1

Tolerances R = ±10% C = ±20%

1.0MΩ

1.0MΩ

47.0nF

4.7nF

33.0pF

33.0pF

1.0µF

3.579545MHz

Timing Information

With CS Low - Figure 3.

After initial power-up and the Hold input inactive
(High), as frequencies are input, with the Data Change
output as an active (High) indicator, the data is
presented at the Data Outputs.

If/when the Hold input is placed active (Low), the
data at the Data Outputs is frozen and the Data
Change output held High at its next active excursion ­until the Hold input is returned High.

With the Hold input held High - Figure 4.

As frequencies are input a correct decode will

produce an active (Low) interrupt level.

This interrupt (IRQ) is serviced and reset by an

active (Low) CS input.

Note the ‘valid data’ period at the Data Outputs.

3

Application Information

Decoder Timing

V

DD

t

PURS

PURS

SIGNAL IN

NOTONE

Tone 1 Tone 2 Tone 3 Tone ’N’

t

DE

t

RESP

OUTPUTS
Q0 to Q3

t

DC

DATA CHANGE

t

HOLD

HOLD

Fig.3 Timing with the Chip Select Input Held “Low”; CS and IRQ are not used

V

DD

t

PURS

PURS

t

NORM

’N’

NOTONE

t

NT

t

PUL

SIGNAL IN

NOTONE

OUTPUTS

Q0 - Q3

EF

(INTERNAL)

DATA CHANGE

IRQ

t

IR

CS

t

ACS

DATA OUT Q0 - Q3

TRI-STATE TRI-STATE

VALID DATA

(READ DATA)

Fig.4 Timing with the HOLD Input Held “High”; CS and IRQ are used

t

RIRQ

t

HIZ

Tone 1

1

VALID DATA

(READ DATA)

4

Specification

Absolute Maximum Ratings

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.
Supply voltage -0.3 to 7.0V
Input voltage at any pin (ref V

Sink/source current (supply pins) +/- 30mA

(other pins) +/- 20mA
Total device dissipation @ T
Derating 10mW/°C

Storage temperature range: FX623P -40°C to +85°C (plastic)

Operating Limits ...... Min. Max. Unit

Supply Voltage (V

Operating Temperature ...... -40 +85 °C

All device characteristics are measured under the following conditions unless otherwise specified:

= 3.3V, T

V

DD

OP

DD

= -40 to +85 °C. Audio Level 0dB ref: = 775mVrms. Xtal/Clock Frequency = 3.579545MHz

Characteristics See Note Min. Typ. Max. Unit

Static Values

Supply Current - 0.6 1.0 mA
Input Logic “1” 0.7 - - %V
Input Logic “0” - - 0.3 %V
Output Logic “1” 0.8 - - %V
Output Logic “0” - - 0.2 %V

Impedance

CS and PURS Input 10.0 - - MΩ
Hold Input 1 0.5 - - MΩ
Signal Input 0.1 - - MΩ
IRQ Output (logic “1”) - 30.0 100 kΩ
IRQ Output (logic “0”) - 175 500 Ω
Q0 - Q3 & Data-Change Outputs (logic “1”) - 0.7 2.0 kΩ
Q0 - Q3 & Data-Change Outputs (logic “0”) - 175 500 Ω
Q0 - Q3 & Data-Change Outputs (high Z) 1.0 - - MΩ

Dynamic Values

Signal Input Range 2, 5 35.0 1,166 mVrms
Decode Bandedge Tolerance 3 -1.0 - 1.0 %

Xtal Inverter

Voltage Gain 20.0 - - V/V
Input Impedance 10.0 - - MΩ
Output Impedance - - 160 kΩ

Decoder Timing -

Power Up Reset Time t
Data 'E' Time t

OTONE to Tone Response Time t

N
Tone to N

OTONE Response Time t

Data to Data-Change Pulse Time t
Data-Change Pulse Width t
Hold to Data-Change Rise Time t
HOLD to Data-Change Fall Time t
IRQ Tone Response Time t
IRQ Reset Time t
Data Access Time t
CS High to Output Tri-State Time t

Figures 3 and 4

= 0V) -0.3 to (V

SS

25°C 800mW Max.

AMB

+ 0.3V)

DD

) 3.0 5.5 V at 25°C

PURS
DE
RESP
NT
DC
PUL
HOLD
NORM
RIRQ
IR
ACS
HIZ

4 - 27.0 50.0 ms
4 - - 60.0 ms

2.5 - - ms

31.0 - - ms

0.625 - 1.15 ms

- 1.25 - ms

63.0 - - µs

- - 150 µs

- 29.0 52.0 ms

- - 250 n s

- - 250 n s

- - 100 n s

DD
DD
DD
DD

Notes

1. This pin has an on-chip 1.0MΩ pullup resistor.

2. An a.c. coupled sine or squarewave.

3. See Table 1, Tone Decode Frequencies.

4. Delay between the change of input (Tone/N

OTONE) and the change at the Q0 - Q3 outputs.

5. The signal input maximum value is determined by the formula V

5

/2.83.

DD

Package Outlines

The FX623 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.

FX623P 16-pin plastic DIL (P3)

NOT TO SCALE

Handling Precautions

The FX623 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.

Max. Body Length 20.57mm
Max. Body Width 6.60mm

Ordering Information

FX623P 16-pin plastic DIL (P3)

CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.