Datasheet FX406LG, FX406J, FX224LG, FX214LG, FX336LG Datasheet (Consumer Microcircuits Limited)

FX803 Audio
Signalling Processor

XTAL/CLOCK

CLOCK

GENERATOR

TONE 1 OUT

TONE 2 OUT

(Rx) AUDIO IN

COMMAND DATA

REPLY DATA

SERIAL CLOCK

SWITCHED SUM OUT

LOW

PASS

FILTER

SUM IN

SUM OUT

CAL/CUES OUT

SUMMING

AMPLIFIER

AUDIO SWITCH OUT

AUDIO SWITCH IN

TONE 2

GENERATOR

CUES / DTMF 2

LOW

PASS

FILTER

DIGITAL

NOISE

FILTER 1

C-BUS

INTERFACE

AND

CONTROL

LOGIC

Rx FILTER

SWITCH

AUDIO SWITCH

SUMMING

SWITCH

CAL/CUES

SWITCH

XTAL

V

DD

V

BIAS

V

SS

LOGIC INPUT

INTERRUPT

CHIP SELECT

SIGNAL INPUT BIAS

DIGITAL

NOISE

FILTER 2

PROGRAMABLE

NOTONE

TIMER

TONE 1

GENERATOR

5- / 2-TONE

DTMF 1

PROGRAMABLE

(Tx PERIOD)

TIMER

QUALITY

METER

GATE TIME

GENERATOR

FREQUENCY

COUNTER

V

BIAS

CUES

CAL

INPUT

AMPLIFIER

Fig.1 FX803 Audio Signalling Processor

Both tone generators can be individually placed into a

power economical “Powersave” mode.

A general purpose logic input, interfacing directly with the
Status Register, is provided. This could be used as an
auxiliary method of routeing digital information to the
µController via the “C-BUS.”

The output frequencies are produced from data loaded to
the device, with a programmable, general purpose, on-chip
timer available to indicate the tone transmit periods.

A Dual Tone Multi-Frequency (DTMF) output is obtained
by combining the 2 independent output frequencies in the
integral summing amplifier. This Summing Amplifier output
is also available for level adjustment.

Tones produced by the FX803 can also be used in the
DBS 800 system as modulation calibration inputs and for
“CUE” audio indications for the operator.

Received tones are measured and their frequency
indicated to the µController in the form of a received data
word. A poor-quality or incoherent tone will, after a
programmed period, indicate N

OTONE.

The FX803 is a low-power, 5-volt CMOS integrated circuit
and is available in 24-pin DIL cerdip and 24-pin/lead plastic
SMD packages.

FX803 Audio Signalling Processor

As part of the DBS 800 System, this audio signalling
processor will provide an inband tone signalling facility for
PMR radio systems. Signalling systems supported include
Selcall (CCIR, ZVEI I, II and III, EEA), 2-Tone Selcall and
Dual Tone Multi-Frequency (DTMF) encode.

Using a non-predictive tone decoder and versatile
encoders gives the FX803 the capability to work in any
standard or non-standard tone system.

This is a full-duplex device consisting of:

● Two individual tone generators and a
programmable (Tx) period timer.

● A tone decoder with programmable N

OTONE

Timer.

● An on-chip summing amplifier.

For use with Single Tone or Selective Call systems.

Under the control of the µController, via “C-BUS,” the
FX803 will encode and transmit a single or pair of audio
tones, in the frequency range 208Hz to 3kHz,
simultaneously, and detect, decode and indicate the
frequency of non-predicted input tones in the frequency
range 313Hz to 6kHz.

Publication D/803/5 August 1997

2

Pin Number Function

Xtal: The output of the on-chip clock oscillator. External components are required at this input when a

Xtal input is used. See Figure 2.

Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (f

XTAL

)

should be connected here. See Figure 2.

Reply Data: The “C-BUS” serial data output to the µController. The transmission of Reply Data bytes
is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held
at high-impedance when not sending data to the µController. See Timing Diagrams.

Chip Select (CS): The “C-BUS” data loading control function. This input is provided by the µController.
Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagram.

Command Data: The “C-BUS” serial data input from the µController. Data is loaded to this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams.

Logic Input: This ‘real-time’ input is available as a general purpose logic input port which can be read
from the Status Register. See Table 3.

Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by
going to a logic “0.” This is a “wire-or able” output, allowing the connection of up to 8 peripherals to 1
interrupt port on the µController. This pin has a low-impedance pulldown to logic “0” when active and a
high-impedance when inactive. The System IRQ line requires one pullup resistor to V

DD

.

The conditions that cause interrupts are indicated in the Status Register and are shown below:

G/Purpose Timer Period Expired NOTONE Timer Period Expired

Rx Tone Measurement Complete

These interrupts are inactive during relevant Powersave conditions and can be disabled by Bits 5 and 6
in the Control Register.

No internal connection, connect to V

SS

.

No internal connection, connect to V

SS

.

Audio Switch In: The input to the stand-alone, on-chip Audio Switch. This switching function (Control
Register Bit 7) may be used to break the system transmitter modulation path when it is required to
provide a CUE (beep) from Tone Generator 2 to the loudspeaker via the FX806 PLMR Audio
Processor.

Audio Switch Out: The output of the stand-alone, on-chip Audio Switch.

V

SS

: Negative Supply (Signal Ground).

J/LG/LS

1

2

3

4

5

6

7

8

9

10

11

12

DW

1

2

3

5

6

7

8

4

9

10

11

12

3

Pin Number Function

J/LG/LS

13

14

15

16

17

18

19

20

21

22

23

24

(Rx) Audio In: The received audio tone signalling input to the Input Amplifier. This input requires to be

a.c. coupled and connected, using external components, to the Signal Input Bias pin. See Figure 2.

Signal Input Bias: External components are required between this input and the (Rx) Audio In pin
See Figure 2.

V

BIAS

: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C

2

See Figure 2.

Tone 1 Out: Tone 1 Generator (2-/5- tone Selcall or DTMF 1) output. External gain and coupling
components will be required at this output when operating in a complete DBS 800 audio installation.
The frequency of this output is determined by writing to Tx Tone Generator 1 Register (Table 4). See
Figure 2.

Tone 2 Out: Tone 2 Generator (2-/5- tone Selcall, CUES or DTMF 2) output. External gain and
coupling components will be required at this output when operating in a complete DBS 800 audio
installation. The frequency of this output is determined by writing to Tx Tone Generator 2 Register
(Table 5). See Figure 2.

CAL/CUES Out: An auxiliary, selectable tone frequency output, providing a square wave CALibration
signal from Tone 2 Generator or a sine wave CUES (beep) signal from the Summing Amplifier. The
output mode (CAL or CUES) is selected by Bit 14 in the Tx Tone Generator 2 Register (Table 5). In a
DBS 800 audio installation, this output should be connected to the Calibration Input of the FX806
PLMR Audio Processor. When Tone Generator 2 is set to V

BIAS

(NOTONE), the CAL output is pulled to

V

BIAS

and during a powersave of Tone Generator 2 it is held at VSS.

Sum In: The input to the on-chip Summing Amplifier. This amplifier is available for combining Tone 1
and Tone 2 outputs (DTMF). Gain and coupling components should be used at this input to provide the
required system gains. See Figures 2 and 3.

Sum Out: The output of the on-chip Summing Amplifier. Combined tones (1 and 2) are available at
this output. See Figures 2 and 3.

Switched Sum Out: The combined tone output available for transmitter modulation. The switch allows
control of the FX803 final output to the FX806. Control of this switch is by Bit 4 of the Control Register.
See Figures 2 and 3.

No internal connection, connect to V

SS

.

Serial Clock: The “C-BUS” serial clock input. This clock, produced by the µController, is used for
transfer timing of commands and data to and from the Audio Signalling Processor. See Timing
Diagrams.

V

DD

: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within the

Audio Signalling Processor are dependent upon this supply.

NOTE: (i) Further information on external components and DBS 800 system integration of this

microcircuit are contained in the System Support Document.

“C-BUS” is CML’s proprietary standard for the transmission of commands and data between a

µ

Controller and DBS 800 microcircuits. It may be used with any µController, and can, if

desired, take advantage of the hardware serial I/O functions embodied into many types of

µ

Controller. The “C-BUS” data rate is determined solely by the µController.

DW

13

14

15

16

17

18

19

20

21

22

23

24

4

External Components

Component Value

R

1

= 1.0MΩ

R

2

2.0MΩ

*R

3

100kΩ

*R

4

82.0kΩ

*R

5

122kΩ

*R

6

100kΩ

*R

7

100kΩ

C

1

= 0.1µF

C

2

1.0µF

C

3

33.0pF

C

4

33.0pF

C

5

22.0pF

C

6

1.0µF

X

1

f

XTAL

4.032MHz

Tolerance: R = ± 10% C = ± 20%

V

BIAS

XTAL/CLOCK

V

DD

V

DD

SEE INSET

BELOW

V

SS

AUDIO SWITCH IN

REPLY DATA

SERIAL CLOCK

2

1

XTAL/CLOCK

V

SS

INSET

FX803J

R

1

X

1

COMMAND DATA

AUDIO SWITCH OUT

XTAL

SIGNAL BIAS
(Rx) AUDIO IN

TONE 1 OUT

TONE 2 OUT

CAL/CUES OUT

SUM IN

SUM OUT

SWITCHED SUM OUT

V

SS

C

6

C

5

R

3

R

4

R

5

R

2

C

1

C

2

XTAL

C

3

C

4

R

7

*

*

*

*

*

TONE LEVEL

and

GAIN

COMPONENTS

13

14

15

16

17

18

19

20

21

22

23

24

1
2
3
4
5

6
7

8
9

10
11

12

FX803J

R

6

CS

LOGIC INPUT

V

SS

IRQ

Notes

1. Xtal/clock circuitry components shown INSET are

recommended in accordance with CML Application
Note D/XT/2 December 1991. The DBS 800 System
Support Document contains additional notes on the use
of Xtal/clock frequencies (f

XTAL

).

2. It is recommended that, to improve screening and

reduce noise levels around the FX803, Pins 8, 9 and 22
are connected to V

SS

.

3. Resistors marked with an asterisk (*) are System
Components, calculated to operate in a system with
other DBS 800 microcircuits. Figure 3 shows in detail,
these components used in the System signal paths.

R

3

, R4, R5, C5 – Tone mixing components to provide a
3dB tone-differential (twist) when used in a DTMF
configuration. Single tone output levels are set
independently or by the FX806 Modulator Drivers.

R

7

– Modulation level and matching for inputs to the
FX806A.

Fig.2 Recommended External Components

+

–

SUM OUT

BIAS

SWITCHED SUM OUT

CAL

CUES

CAL/CUES OUT

TONE 2 OUT

TONE 1 OUT

SUM IN

AUDIO SWITCH OUT

AUDIO SWITCH IN

SUMMING

AMPLIFIER

FROM FX806

“MAIN PROCESS OUT”

TO FX806

“SUM IN”

TO FX806

“CALIBRATION IN”

DBS 800 “TRANSMIT AUDIO” BUS

17

16

19

20

21

18

11

10

FX803Part of

Fig.3 Output Signal Switching

5

Controlling Protocol

Control of the FX803 Audio Signalling Processor's operation is by communication between the µController and the FX803
internal registers on the “C-BUS,” using Address/Commands (A/Cs) and appended instructions or data (see Figure 7). The use
and content of these instructions is detailed in the following paragraphs and tables.

Address/Commands

The first byte of a loaded data sequence is always
recognized by the “C-BUS” as an Address/Command (A/C)
byte. Instruction and data transactions to and from this
device consist of an Address/Command byte followed by
either:

(i) further instructions or data or,

(ii) a Status or data Reply.

Instructions and data are loaded and transferred, via
“C-BUS,” in accordance with the timing information given in
Figures 7 and 8.

Table 1 shows the list of A/C bytes relevant to the FX803.
A complete list of DBS 800 “C-BUS” Address allocations is
published in the System Support Document.

(Rx) HIGH BAND

Frequency (Hz)

(Tx) TONE GENERATORS 1 and 2

(Rx) EXTENDED BAND

(Rx) HIGH BAND

0 1000 2000 3000 4000 5000 6000

208Hz to 3000Hz

1250Hz to 6000Hz

625Hz to 3000Hz

313Hz to 1500Hz

(Rx) MID BAND

0 1000 2000 3000 4000 5000 6000

Frequency (Hz)

FX803 Internal Registers

FX803 internal registers are detailed below:
Control Register (30

H

) – Write Only, control and

configuration of the FX803.

Status Register (31

H

) – Read Only, reporting of device

functions.

Rx Tone Frequency Register (32H) – Read Only, indicates

frequency of the last received input.

Rx N

OTONE Timer Register (33

H

) – Write Only, setting of the

Rx N

OTONE period.

Tx Tone Generator 1 Register (34

H

) – Write Only, setting

the required output frequency from Tx Tone Generator 1.

Tx Tone Generator 2 Register (35H) – Write Only, setting

required output frequency from Tx Tone Generator 2.

General Purpose Timer Register (36

H

) – Write Only,

setting of a general purpose, sequential time period.

Command Address/Command (A/C) Byte + Data
Assignment Hex. Binary Byte/s

MSB LSB

General Reset 01 0 0 0 00001
Write to Control Register 30 0 0 1 10000 + 1 byte Instruction to Control Register
Read Status Register 31 0 0 1 10001 + 1 byte Reply from Status Register
Read Rx Tone Frequency 32 0 0 1 10010 + 2 byte Reply from Rx Tone Register
Write to N

OTONE Timer 33 0 0 1 10011 + 1 byte Instruction to NOTONE Register

Write to Tx Tone Gen. 1 34 0 0 1 10100 + 2 byte Instruction to Tx Tone Gen. 1
Write to Tx Tone Gen. 2 35 0 0 1 10101 + 2 byte Instruction to Tx Tone Gen. 2

Write to G/Purpose Timer 36 0 0 1 10110 + 1 byte Instruction to G/Purpose Timer

Table 1 “C-BUS” Address/Commands

Fig.4 FX803 Frequencies

6

Status Bits

Received First

Set to

“0”

Set to

“0”

Set to

“0”

Set to

“0”

Logic Input Status

“1”
“0”

G/Purpose Timer Period

Expired

(IRQ generated if enabled)

(Table 2)

NOTONE Timer Period

Expired

(IRQ generated if enabled)

(Table 2)

Rx Tone Measurement

Complete

(Interrupt Generated)

Reading

MSB
Bit 7

0

6

0

5

0

4

0

3

1
0

2

1

1

1

0

1

“Read Status Register” – A/C 31

H

, followed by 1 byte of Reply Data.

Controlling Protocol ......

Table 3 Status Register

Interrupt Requests (IRQ)

Interrupts on this device are available to draw the attention

of the µController to a change in the condition of the bit in

the Status Register. However Bits are set in the Status

Register irrespective of the setting of interrupt enable bits

(Table 2) and these changes may be recognized by

‘polling’ the register.

General Purpose Timer Period

Set to a logic “1” when the timer period has expired.

Cleared to a logic “0,”

i By a read of the Status Register or,

ii New G/Purpose Timer information or,

iii General Reset Command

N

OTONE Timer Period

Set to a logic “1” when the timer period has expired.

Cleared to a logic “0,”

i By a read of the Status Register or,

ii New N

OTONE Timer information or,

iii General Reset Command

Rx Tone Measurement

Set to a logic “1” when the Rx Tone measurement is

complete.
Cleared to a logic “0,”

i By a read of the Status Register or,

ii General Reset Command

Control Bits

Transmitted First

Audio Switch

Enable

Disable

G/Purpose Timer Interrupt

Enable

Disable

Decoder Interrupts

Enable

Disable

Summing Switch

Enable

Disable

Band Selection

High Band

Mid Band

Extended Band

Do Not use this setting

Set to

“0”

Set to

“0”

Setting

MSB
Bit 7

1
0

6

1
0

5

1
0

4

1
0

32

00
01
10
11

1

0

0

0

Table 2 Control Register

Audio Switch

See the Signal Switching diagram (Figure 3) and DBS 800
Document for application examples.

General Purpose Timer

Should be set up before interrupts are enabled, as a
General Reset command will set the timer period to
00H – 0ms (permanent interrupt).

Interrupt Enable Instructions

Status Bits 0, 1 and 2 are produced regardless of the state
of these settings.

Band Selection

Bits 2 and 3 set the required frequency range (see Figure
4, FX803 Frequencies).

Summing Switch

To break the FX803 drive to the FX806 PLMR Audio
Processor (see Figure 3, Signal Switching).

Interrupt Designation

Decoder Interrupts:

No Tone Timer and Rx Tone Measurement.

Transmitter Interrupt:

G/Purpose Timer Interrupt.

“Write to Control Register” – A/C 30

H

, followed by 1 byte of Command Data.

7

Controlling Protocol ......

Tx Tone Generator Registers 1 and 2

Each Tx Tone Generator is controlled individually by writing a two-byte command to the relevant Tx Tone Generator
Register. The format of this command word, which is different for each tone generator, is shown below with the calculations
required for tone frequency (f

TONE

) generation described in the following text.

“Write to Tx Tone Generator 1 Register” – A/C 34

H

followed by 2 bytes of Command Data.

Tx Tone Frequencies

With reference to Tables 4 and 5 (above), whilst Input Data Words “A” or “B” can be programmed for frequencies outside the
stated limits of 208Hz and 3000Hz, any output frequencies obtained may not be within specified parameters
(see “Specification” page).

Calculations

As can be seen from Tables 4 and 5 (above), a binary number (“A” or “B” – Bits 0 to 12) is loaded to the respective Tx Tone
Generator. The formulas shown below are used to calculate the required output frequency.

Required Tx Tone output frequency = f

TONE

1 or 2

XTAL/clock frequency = f

XTAL

Input Data Word (Bits 0 to 12) = “A” or “B”

Formula

f

TONE

(HZ) =f

XTAL

(HZ)

or

Input “A” (or “B”) =f

XTAL

(HZ)

4 x “A” (or “B”) 4 x f

TONE

(HZ)

MSB Bit Numbers LSB

(loaded first) (loaded last)

1514 13 1211109876543210

“0” “0” V

BIAS

/ These 13 bits (0 to 12) are used to produce a binary number, designated “A.”

Enable “A” is used in the formulas below to set the Tx Tone 1 frequency (f

TONE

1).

MSB Bit Numbers LSB

(loaded first) (loaded last)

1514 13 1211109876543210

“0”

CAL/ V

BIAS

/ These 13 bits (0 to 12) are used to produce a binary number, designated “B.”

CUES Enable “B” is used in the formulas below to set the Tx Tone 2 frequency (f

TONE

2).

“Write to Tx Tone Generator 2 Register” – A/C 35

H

followed by 2 bytes of Command Data.

Table 5 Setting Tx Tone Generator 2

Table 4 Setting Tx Tone Generator 1

Notes

(1) Programming Tone Generator 2 to V

BIAS

(NOTONE) (Bit 13) will place the CAL/CUES Output at V

BIAS

via a 40kΩ

internal resistor.
(2) Programming Tone Generator 2 to Powersave will place the CAL/CUES Output at VSS.
(3) If both Tone Generators (1 and 2) are Powersaved, the Summing Amplifier is also Powersaved.

The binary number produced by bits 0 to 12 (MSB) is
designated "A."
If “A” = all logic “0” then Tx Tone Generator 1 is
Powersaved.

Bit 13 at logic “1” = Tone 1 Output at V

BIAS

(NOTONE).

“0” = Tone 1 Output Enabled.

Bits 14 and 15 (

MSB) must be logic “0.”

Bit 13 at logic “1” = Tone 1 Output at V

BIAS

(NOTONE).

“0” = Tone 1 Output Enabled.

Bit 14 at logic “1” = Squarewave CAL Output.

“0” = Sinewave CUES Output.

Bit 15 (MSB) must be a logic “0.”

The binary number produced by bits 0 to 12 (MSB) is
designated "B."
If “B” = all logic “0” then Tx Tone Generator 2 is
Powersaved.

8

Controlling Protocol ......

“Read Rx Tone Frequency Register” – A/C 32

H

, followed by 2 bytes of Reply Data.

Measurement of Rx Signal Frequency (S

INPUT

)

The measurement details given on Pages 10 and 11 are

for a Xtal/clock frequency (f

XTAL

) of 4.032MHz, a scaling

formula for other values of f

XTAL

is given at the bottom of this

page.

The input audio signal (S

INPUT

) is filtered and measured in
the Frequency Counter over a specified “measurement
period” (9.125 ms or 18.250 ms).

The measuring function counts the number of complete
input cycles occurring within the measurement period and
then the number of measuring-clock cycles necessary to
make up the period.

When the count period of a successful decode is
complete, the Rx Tone Measurement bit in the Status
Register, and the Interrupt bit (if enabled) are set.

The Rx Tone Frequency Register will now indicate the
signal frequency (S

INPUT

) in the form of 2 bytes (1 and 0) as

illustrated in Figure 6 below.

Measurement Period

R

Complete

Input

Cycle

Complete

Input

Cycle

Complete

Input

Cycle

Complete

Input

Cycle

Complete

Input

Cycle

FILTERED AUDIO INPUT SIGNAL

Measuring

Clock

Cycles

N

INPUT

S

2 x

The Remainder (R) – Byte 0

A binary number representing the remainder part, R,
of 2 x Input Signal Frequency (S

INPUT)

.

‘R = number of

specified measuring-clock cycles’

required to complete the

specified measurement period (See N).

The clock-cycle frequencies are:

High Band Decode = 56.00 kHz = “f”

Mid Band Decode = 28.00 kHz = “f”

Extended Band Decode = 56.00 kHz = “f”

Fig.5 Measurement of a Mid or High Band Rx Frequency

The Integer (N) – Byte 1

A binary number representing

‘twice the number of

complete input audio cycle periods’

counted during the

specified measurement period, which is:

High Band Decode = 9.125 ms = “t”
Mid Band Decode = 18.250 ms = “t”
Extended Band Decode = 9.125 ms = “t”

See the bottom of this page for “t” and “f” scaling factors

15 14 13 12 11 10 9 8

Byte 0

(REPLY DATA

)

(LSB) – TRANSMITTED LAS

T

Integer (N)

Byte 1

“0” “0”

Remainder (R)

(REPLY DATA)
(MSB) – TRANSMITTED FIRST

“0” “0”

7654 321 0

Fig.6 Format of the Rx Tone Frequency Register

f

XTAL

Scaling Factors

The calculations above are for an f

XTAL

of 4.032MHz. The
following formulas enable the calculation of these values
using any Xtal value. Note: f

XTAL

values are stated in MHz.

“t”

scaled

= “t” x 4.032

f

XTAL

“f”

scaled

= “f” x f

XTAL

4.032

9

Controlling Protocol ......

Frequency Measurement Formulæ

To assist in the production of ‘look-up’ tables and limit-values in the µController and provide guidance upon the determination
of N and R from a measured frequency, the following formulæ show the derivation of the Rx frequency, S

INPUT

, from the

measured data bytes (N and R), Figure 6.

Nm and Rm – Mid Band

The measurement period = 18.250ms
Clock Frequency = 28.000kHz
The measured frequency = 2 x S

INPUT

c/s

In the measurement period there are:

2 x S

INPUT

x 18.250 x 10-3 cycles

Nm is the lower integer value of this decimal number:

Nm = INT (18.250 x 10

-3

x 2 x S

INPUT

) [6]

Rm is rounded to the nearest integer of this decimal number:

Rm = (18.250 x 10

-3

– Nm ) x 28000 [7]

2 x S

INPUT

S

INPUT

– High Band

In the measurement period of 9.125ms, there are Nh

cycles at 2S

INPUT

and Rh clock cycles at 56.000kHz.

so Nh + Rh = 9.125ms

2 x S

INPUT

56000

From which S

INPUT

= 28000 x Nh Hz [1]

(511 – Rh)

Nh and Rh – High Band

The measurement period = 9.125ms
Clock Frequency = 56.000kHz
The measured frequency = 2 x S

INPUT

c/s

In the measurement period there are:

2 x S

INPUT

x 9.125 x 10-3 cycles

Nh is the lower integer value of this decimal number:

Nh = INT (9.125 x 10

-3

x 2 x S

INPUT

) [4]

Rh is rounded to the nearest integer of this decimal number:

Rh = (9.125 x 10

-3

– Nh ) x 56000 [5]

2 x S

INPUT

High Band Measurement

S

INPUT

– Mid Band

In the measurement period of 18.250ms, there are Nm

cycles at 2S

INPUT

and Rm clock cycles at 28.000kHz.

so Nm + Rm = 18.250ms

2 x S

INPUT

28000

From which S

INPUT

= 14000 x Nm Hz [2]

(511 – Rm)

Mid Band Measurements

Ne and Re – Extended Band

The measurement period = 9.125ms
Clock Frequency = 56.000kHz
The measured frequency = S

INPUT

c/s

In the measurement period there are:

S

INPUT

x 9.125 x 10-3 cycles

Ne is the lower integer value of this decimal number:

Ne = INT (9.125 x 10

-3

x S

INPUT

) [8]

Re is rounded to the nearest integer of this decimal number:

Re = (9.125 x 10

-3

– Ne ) x 56000 [9]

S

INPUT

S

INPUT

– Extended Band

In the measurement period of 9.125ms, there are Ne

cycles at S

INPUT

and Re clock cycles at 56.000kHz.

so Ne + Re = 9.125ms

S

INPUT

56000

From which S

INPUT

= 56000 x Ne Hz [3]

(511 – Re)

Extended Band Measurements

10

Controlling Protocol ......

“Write to the Rx NOTONE Timer Register” – A/C 33

H

followed by 1 byte of Command Data.

Setting

MSB

76 5 4

0000

321 0

000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1
101 0
101 1
110 0
110 1
111 0
111 1

Function/Period

Transmitted Bit 7 First

These 4 bits must be “0”

High/Extended Mid

Band Band

period (ms) 00

"20 ±1% 40 ±1%

40 " 80 "
60 " 120 "

80 " 160 "
100 " 200 "
120 " 240 "
140 " 280 "
160 " 320 "
180 " 360 "
200 " 400 "
220 " 440 "
240 " 480 "
260 " 520 "
280 " 560 "
300 " 600 "

Operation of the Rx NOTONE Timer

An Rx NOTONE period is that period when no signal or a

consistently bad-quality signal is received.

The Rx N

OTONE Timer can be employed to indicate to the

µController that a N

OTONE situation has existed for a

predetermined period.

This timer register can be written-to and set in any

mode of the FX803.

The N

OTONE Timer period is ‘primed’ by writing to the

N

OTONE Timer Register (33

H

) using the settings given in

Table 6.

“Priming” sets the timing period; this period can only

start directly after a frequency (tone) measurement
has been successfully completed.

The NOTONE Timer is a one-shot timer being reset only

by successful tone measurements.

If the quality of the received signal drops to an unusable

level the N

OTONE Timer will start its run-down.

On completion of the preset period, the N

OTONe Timer

Period Expired bit in the Status Register and the Interrupt
(when enabled,

Table 2

) are set.

Upon detection of the Interrupt, the Status Register
should be read by the µController to ascertain the source
of the Interrupt.

The N

OTONe Timer Period Expired bit is cleared:

i By a read of the Status Register or,

ii New NOTONE Timer information or,

iii General Reset command

This timer is set to 00

H

(0ms) by a General Reset command.

No Signal

The NOTONE Timer can only start its run down on
completion of a valid frequency measurement.

No Signal after a Valid Tone Measurement

The timer will start to run down when the last Rx Tone
Measurement complete bit is set. At the end of the
“primed” period the NOTONe Timer Period Expired bit in the
Status Register and the Interrupt will be set.

The following situations may be encountered by the NOTONE Timer circuitry:

Signal Fades after a Valid Tone Measurement

The timer will start to run down when the signal becomes
unreadable to the device. At the end of the “primed” period
the NOTONe Timer Period Expired bit in the Status Register
and the Interrupt will be set.

Signal Appears after the Timer has Started

If the frequency measurement is more than 75% complete
when the timer period expires, neither the N

OTONE bit nor

the Interrupt will be set unless that frequency
measurement is subsequently aborted.

Table 6 Rx N

OTONE

Timer Settings

11

Controlling Protocol ......

“Write to General Purpose Timer Register” – A/C 36

H

followed by 1 byte of Command Data.

Setting

MSB

76 5 4

0000

321 0

000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1
101 0
101 1
110 0
110 1
111 0
111 1

Function/Period

Transmitted Bit 7 First

These 4 bits must be “0”

High/Extended Mid

Band Band

Reset Timer and Start Timing
Period of 0 0

" 10 ms ±1% 20 ms ±1%

20 " 40 "
30 " 60 "
40 " 80 "
50 " 100 "
60 " 120 "
70 " 140 "
80 " 160 "

90 " 180 "
100 " 200 "
110 " 220 "
120 " 240 "
130 " 260 "
140 " 280 "
150 " 300 "

Operation of the General Purpose Timer

This timer, which is not dedicated to any specific
function within the FX803, can be employed within the
DBS 800 system to indicate time-elapsed periods of
between 10ms and 150ms in the High/Extended Band,
20ms and 300ms in the Mid Band, to the µController.

Setting of the timer is by loading a single-byte data word
via the “C-BUS,” as indicated in Table 7 (left), to the
FX803 via the Command Data line.

The timer will be reset and the run-down started on
completion of Timer Data Word loading.

When the programmed time period has expired, the
General Purpose Timer Expired bit (Bit 2) in the Status
Register and the Interrupt (if enabled) are set.

The General Purpose Timer Expired bit is cleared:

i By a read of the Status Register, or
ii New G/P Timer information, or
iii General Reset command.

When the programmed time period has expired, this timer
will reset, restart and continue sequencing until;

i New G/P Timer information is written, or
ii A General Reset command.

The General Purpose Timer Expired bit and the Interrupt will
remain set until cleared.

This timer is set to 00

H

(0ms) by a General Reset command.

Powersaved Section Instruction Source Table

Tone Encoder 1 Tx Tone Gen.1 Reg. (34H) All bits = “0” 4
Tone Encoder 2 Tx Tone Gen.2 Reg. (35H) All bits = “0” 5
Summing Amplifier This action is automatic when both Tone Encoders are in the powersave

condition.

Table 8 FX803 Powersave Functions

Powersave

Various sections of the FX803 can be placed independently into a power economical condition. Table 8 (below) gives a brief

summary of the inactive, power-economical states available to the FX803.

Powersave Conditions

Xtal/Clock and “C-BUS”: This circuitry is always active, on all DBS 800 microcircuits, under any powered/powersaved

conditions.

Table 7 General Purpose Timer Settings

12

Controlling Protocol ......

NOTONE Timer Period

Expired

Enabled: By Control Register Bit 5.
Set: When the preset Notone Flag is

set.

Identified: By Status Register Bit 1.
Cleared: By reading the Status

Register.

G/Purpose Timer

Period Expired

Enabled: By Control Register Bit 6.
Set: When the General Purpose Timer

has timed out.

Identified: By Status Register Bit 2.
Cleared: By reading the Status

Register.

Rx Tone Measurement

Complete

Enabled: By Control Register Bit 5.
Set: When an Rx Frequency

Measurement has been successfully
completed.

Identified: By Status Register Bit 0.
Cleared: By reading the Status

Register.

On recognition of the “Read Status” Command byte, the interrupt output is cleared, the Status Bits are transferred to the

µController via the “C-BUS” Reply Data line and the internal Status Bits are cleared.

Operational Recommendations

It is recommended that, following initial System power-up a General Reset command is sent to the FX803.

Receive Sequence

1. Send Control Command for Rx:

Select Midband/Highband and Digital Filter length.

2. Disable transmitters, if desired by writing to Tone
Frequency registers.

3. Prime the N

OTONE Timer by sending the required

period byte.

4. Enable Decoder interrupts as desired.

5. When a valid tone has been detected by a

successfully completed measurement the Status
Register is set to “Tone Measurement Complete” and
an interrupt sent to the µC.

6. The µC examines the Status Register, if tone
measurement is complete, reads in the Rx Tone
Frequency in the form N + R (Figure 6).

7. Rx Tone Measurement Complete interrupts are
periodically sent to the µC unless N

OTONE is detected,

in which case a NOTONE Interrupt is sent.

Transmit Control Sequence

1. Set Tone Frequency Generators to V

BIAS

(setting
both tone generators (Bit 13 = “1”)) during the
transmitter initialization period.

2. Send Control Command for Tx:
Select Sum/Switched Sum o/p and Audio Switch
states.

3. Send General Purpose (GP) Timer information for the
V

BIAS

(NOTONE) transmitter initialization period (Step 1).

This will initiate the timer.

4. Enable the General Purpose Timer interrupt.

5. µC waits for “GP Timer Expired;” Reads the Status

Register to check interrupt due to timer; Resets the
Status Bit.
If required, the µC sends the next timer period followed
by the next tone(s) frequency information.
A new timer period sent will reset the timer, otherwise
the timer is self-sequencing.

6. The µC monitors the interrupts and repeats 5 & 6 as
required.

7. After last loaded tone the µC turns off the Tone
Generator(s) by setting tone outputs to V

BIAS

(NOTONE)

(Tables 4 and 5).

General Reset

Upon Power-Up the “bits” in the FX803 registers will be
random (either “0” or “1”). A General Reset Command
(01H) will be required to “reset” all microcircuits on the
“C-BUS,” and has the following effect upon the FX803.

Control Reg. Set as 00

H

Status Reg. Bits 0, 1, 2.) Set as 00

H

NOTONE Timer Reg. Set as 00

H

Tone Gen. 1 Reg. (2 bytes) Set as 0000

H

Tone Gen. 2 Reg. (2 bytes) Set as 0000

H

Gen/Purpose Reg. Set as 00

H

Sets the FX803 to:

Encoder High Band (625Hz to 3000Hz) – with interrupts

disabled, both timers set to 00H.

It is recommended that both timers are set-up before

interrupts are enabled, to prevent initial, undesired interrupts.

Glossary of Abbreviations

Below is a list of abbreviations used within this Data
Sheet.

f

XTAL

Xtal/clock frequency

S

INPUT

Audio input signal

f

TONE

Tone frequency

Interrupt Requests

An Interrupt (IRQ), when enabled, is provided by the FX803 to indicate the following conditions to the µController.

13

Timing Information

70% V

DD

30% V

DD

t

CL

t

CH

t

CDS

t

CDH

t

RDS

t

CK

t

RDH

SERIAL CLOCK
(from

µ

C)

COMMAND DATA
(from

µ

C)

REPLY DATA
(to

µ

C)

Parameter Min. Typ. Max. Unit

t

CSE

2.0 – – µs

t

CSH

4.0 – – µs

t

CSOFF

2.0 – – µs

t

NXT

4.0 – – µs

t

CK

2.0 – – µs

t

CH

500 – – ns

t

CL

500 – – ns

t

CDS

250 – – ns

t

CDH

0––ns

t

RDS

250 – – ns

t

RDH

50.0 – – ns

t

HIZ

– – 2.0 µs

Notes

(1) Command Data is transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last.

Reply Data is read from the FX803 MSB (Bit 7) first, LSB (Bit 0) last.
(2) Data is clocked into the FX803 and into the µController on the rising Serial Clock edge.
(3) Loaded data instructions are acted upon at the end of each individual, loaded byte.
(4) To allow for differing µController serial interface formats, the FX803 will work with either polarity Serial

Clock pulses.

Timing Diagrams

Figure 7 shows the timing parameters for two-way communication between the µController and the FX803 on the “C-BUS.”
Figure 8 shows, in detail, the timing relationships for “C-BUS” information transfer.

SERIAL CLOCK

COMMAND DATA

t

CSE

t

NXT

t

CSOFF

t

CSH

t

HIZ

ADDRESS/COMMAND

BYTE

FIRST DATA BYTE LAST DATA BYTE

76543210 76543210 76543210

76543210

MSB LSB

CHIP SELECT

LAST REPLY DATA BYTE

t

NXT

t

CK

REPLY DATA

76543210

MSB LSB

FIRST REPLY DATA BYTE

Logic level is not important

Fig.7 “C-BUS” Timing Information

NOT TO SCALE

Fig.8 “C-BUS” Timing Relationships

NOT TO SCALE

14

Specification

Absolute Maximum Ratings

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied.
Supply voltage -0.3 to 7.0V

Input voltage at any pin (ref V

SS

= 0V) -0.3 to (V

DD

+ 0.3V)

Sink/source current (supply pins) +/- 30mA

(other pins) +/- 20mA

Total device dissipation @ T

AMB

25°C 800mW Max.
Derating 10mW/°C
Operating temperature range: FX803J -40°C to +85°C (cerdip)

FX803DW/LG/LS -40°C to +85°C (plastic)

Storage temperature range: FX803J -55°C to +125°C (cerdip)

FX803DW/LG/LS -40°C to +85°C (plastic)

Operating Limits

All device characteristics are measured under the following conditions unless otherwise specified:
V

DD

= 5.0V. T

AMB

= 25°C. Xtal/Clock (f

XTAL

) = 4.032MHz. Audio Level 0dB ref: = 308mVrms @ 1kHz

(60% deviation, FM)

.

Noise Bandwidth = 5.0kHz Band-Limited Gaussian.

Characteristics See Note Min. Typ. Max. Unit

Static Values

Supply Voltage 4.5 5.0 5.5 V
Supply Current

(Decoder + Both Timers) – 2.0 – mA
(Decoder + Both Timers + One Tx only) – 4.0 – mA
(All Functions Enabled) – 5.0 – mA

Analogue Impedances

(Rx) Audio Input – 20.0 – MΩ
Summing Amp Input – 20.0 – MΩ
Switch – 1.0 – kΩ
Tones 1 and 2 Outputs – 10.0 – kΩ
CAL/CUES Output – 5.0 – kΩ
Summing Outputs – 10.0 – kΩ

Dynamic Values

Digital Interface

Input Logic “1” 1 3.5 – – V
Input Logic “0” 1 – – 1.5 V
Output Logic “1” (IOH = -120µA) 2 4.6 – – V
Output Logic “0” (IOL = 360µA) 3 – – 0.4 V
I

OUT

Tristate (Logic “1” or “0”) 3 – – 4.0 µA
Input Capacitance 1 – – 7.5 pF
IOX (V

OUT

= 5.0V) 4 – – 4.0 µA

Overall Performance

Rx – Decoding
High-Band

Sensitivity – -20.0 – dB
Tone Response Time

Good Signal 5 – – 30.0 ms
Tone-to-Noise Ratio = 0dB 5, 6 – – 40.0 ms

Frequency

Band 625 3000 Hz
Measurement Resolution – 0.2 – %
Measurement Accuracy 9 – 0.5 – %

15

Specification ......

Characteristics See Note Min. Typ. Max. Unit

Rx – Decoding ......

Mid-Band

Sensitivity – -20.0 – dB
Tone Response Time

Good Signal 7 – – 60.0 ms
Tone-to-Noise Ratio = 0dB 6, 7 – – 80.0 ms

Frequency

Band 313 1500 Hz
Measurement Resolution – 0.2 – %
Measurement Accuracy 9 – 0.5 – %

Extended-Band

Sensitivity – -20.0 – dB
Tone Response Time

Good Signal 5 – – 20.0 ms

Frequency

Band 1250 6000 Hz
Measurement Resolution – 0.2 – %
Measurement Accuracy 9 – 0.5 – %

Tx – Encoders 1 and 2

Tone Frequency 208 3000 Hz
Period (1/f

TONE

) Error – – 1.0 µs
Tone Amplitude -1.0 – 1.0 dB
Total Harmonic Distortion – – 5.0 %
Rise Time to 90% – 3/f

TONE

– secs
Fall Time to 10% 8 – – 5.0 ms
Frequency Change Time – 3/f

TONE

– secs

Timers
General Purpose

Timing Period Range

High-Band 10.0 150 ms
Mid-Band 20.0 300 ms

Rx N

OTONE

Timing Period Range

High-Band 20.0 300 ms
Mid-Band 40.0 600 ms

Xtal/Clock Frequency (f

XTAL

) 3.9 – 6.0 MHz

Notes

1. Device control pins; Serial Clock, Command Data, and CS.

2. Reply Data output.

3. Reply Data and IRQ outputs.

4. Leakage current into the “Off” IRQ output.

5. Measurement Period = 9.125ms.

6. Decode Probability = 0.993.

7. Measurement Period = 18.250ms.

8. When set to Powersave.

9. For a good input signal.

10. The use of the FX803 at Xtal/clock frequencies above 4.0MHz will cause a shift in the overall performance
parameters.

Handling Precautions

The FX803 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.

Package Outlines

The FX803 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.

FX803J 24-pin cerdip DIL (J4)FX803DW 24-pin plastic S.O.I.C. (D2)

NOT TO SCALE

Max. Body Length 32.00mm
Max. Body Width 13.36mm

NOT TO SCALE

Max. Body Length 15.57mm
Max. Body Width 7.59mm

CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.

FX803LS 24-lead plastic leaded chip carrier

(L2)

NOT TO SCALE

Max. Body Length 10.40mm
Max. Body Width 10.40mm

FX803LG 24-pin quad plastic encapsulated

bent and cropped (L1)

NOT TO SCALE

Max. Body Length 10.25mm
Max. Body Width 10.25mm

Ordering Information

FX803DW 24 pin plastic S.O.I.C. (D2)
FX803J 24-pin cerdip DIL (J4)

FX803LG 24-pin encapsulated bent and

cropped (L1)

FX803LS 24-lead plastic leaded chip carrier

(L2)