Datasheet FTF3020-C-TG, FTF3020-C-IG, FTF3020-C-HG, FTF3020-C-EG Datasheet (Philips)

IMAGE SENSORS

FTF3020-C

Full Frame CCD Image Sensor

Product specification 1999 November 22
File under Image Sensors

Philips
Semiconductors

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

• 35mm film compatible image format (36 x 24 mm2)

• 6M active pixels (3072H x 2048V)

• RGB Bayer pattern

• Progressive scan

• Excellent anti-blooming

• Variable electronic shuttering

• Square pixel structure

• H and V binning

• 80% optical fill factor

• High linear dynamic range (>72dB)

• High sensitivity

• Low dark current and fixed-pattern noise

• Low read-out noise

• Data rate up to 36 MHz

• Mirrored, split and four quadrant read-out

• Perfectly matched to visual spectrum

Device structure

Optical size: 36.864 mm (H) x 24.576 mm (V)
Chip size: 39.148 mm (H) x 26.508 mm (V)
Pixel size: 12 µm x 12 µm
Active pixels: 3072 (H) x 2048 (V)
Total no. of pixels: 3120 (H) x 2060 (V)
Optical black pixels: Left: 20 Right: 20
Timing pixels: Left: 4 Right: 4
Dummy register cells: Left: 7 Right: 7
Optical black lines: Bottom: 6 Top: 6

Description

The FTF3020-C is a full frame CCD colour image sensor designed
for professional digital photography applications, with very low dark
current and a linear dynamic range of over 12 true bits at room
temperature. The four low-noise output amplifiers , one at each corner
of the chip, make the FTF3020-C suitable for a wide range of high­end visual light applications. With one output amplifier , a progressiv ely
scanned image can be read out at 5 frames per second. By using
multiple outputs the frame rate increases accordingly. The device
structure is shown in figure 1.

Z Y

GBGB
RGRG
GBGB

Image Area

20

3072 active pixels

6 black lines

2048
active
lines

GBGB
RGRG
GBGB

2060
lines

44

20

W X

Output amplifier

Figure 1 - Device structure

1999 November 2

GBGB
RGRG

77

3120 cells

Output register

3134 cells

6 black lines

GBGB
RGRG

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Architecture of the FTF3020-C

The optical centres of all pixels in the image section form a square
grid. The charge is generated and integrated in this section. Output
registers are located below and above the image section for read­out. After the integration time, the image charge is shifted one line
at the time to either the upper or lower register or to both
simultaneously, depending on the read-out mode. The left and the
right half of each register can be controlled independently. This

IMAGE SECTION

Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Geometric fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
Number of black reference lines
Number of dummy black lines
Total number of lines
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line

44.30 mm
3:2

36.864 x 24.576 mm
12x12 µm
80%
16 pins (A1..A4)

7.5nF per pin
2048
4 (=2x2)
8 (=2x4)
2060
3072
8 (2x4)
40 (2x20)
3120

enables either single or multiple read-out. During vertical transport,
the C3 gates separate the pixels in the register . The central C3 gates
of the lower and upper registers are part of the left half of the sensor
(W and Z quadrants respectively). Each register can be used for
vertical binning. Each register contains a summing gate at both ends
that can be used for horizontal binning (see figure 2).

2

2

Output buffers on each corner
Number of registers
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Output register Summing Gates
Capacity of each SG
Reset Gate clock phases
Capacity of each RG

OUTPUT REGISTERS

Three-stage source follower
2
14 (2x7)
3134 (3120+14)
6 pins per register (C1..C3)
200 pF per pin
40pF
4 pins (SG)
15pF
4 pins (RG)
15pF

1999 November 3

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

RGRG

OG

C3 C3 C3 C3 C3 C3 C3 C3 C3C3 C3

7 dummy pixels

RD

OUT_Z

One Pixel

SG: summing gate
OG: output gate
RG: reset gate

RD: reset drain

OUT_W

OG C1 OG

RG

RD

C3 C3 C3C3 C3 C3 C3 C3 C3 C3 C3

SG

20 black &4 timing

columns

C1C1SG C2 C2 C2 C1 C2 C1 C2 C1 C2 C1 C2 C2C1 C1 C2 C1 C2 C1 C2 C1 C2 C1 SG OGC1 C3

A1 A1

A2
A3
A4

A1

A1
A2
A3
A4

A1

A2
A3
A4

A1

A1
A2
A3A3
A4

A1

A2
A3
A4

A1

A1
A2
A3
A4

C1C1C2 C2 C2 C1 C2 C1 C2C1

6 black
lines

2K active
images
lines

6 black
lines

C2 C1 C2 C1 C2 C2C1 C1 C2 C1 C2 C1 C2

column

1

column

24 + 1

3K image

pixels

IMAGE

3K x 2K
FF CCD

C3

column

24 + 3K

20 black & 4 timing

columns

column

24 +3K +24

7 dummy pixels

A2
A3
A4

A1

A1
A2
A3
A4

A1

A2
A3
A4

A1

A1
A2
A3
A4

A1

A2
A3
A4

A1

A1A1
A2
A3
A4

A1A1

A1, A2, A3, A4: clocks of image section C1, C2, C3: clocks of hor izontal registers

C1 SG

RD

OUT_Y

OUT_X

RD

RG

RG

Figure 2 - Detailed internal structure

1999 November 4

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Specifications

ABSOLUTE MAXIMUM RATINGS

GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock phase (absolute value)
OUT current (no short circuit protection)

VOLTAGES IN RELAT ION TO VPS:
VNS, SFD, RD
VCS, SFS
all other pins

VOLTAGES IN RELAT ION TO VNS:
SFD, RD
VCS, SFS, VPS
all other pins

2

VNS
VPS
SFD
SFS
VCS
OG
RD

3

N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain

DC CONDITIONS

1

MIN. MAX. UNIT

-55

-40

-20

-0.2
0

-0.5

-8

-5

-15

-30

-30

+80
+60
+20
+2.0
10

+30
+5
+25

+0.5
+0.5
+0.5

°C
°C
V
µA
mA

V
V
V

V
V
V

MIN. [V] TYPICAL [V] MAX. [V] MAX. [mA]

18
1
16
0

-5
4
13

24
3
20
0
0

6.5

15.5

28
7
24
0
3
8
18

15
15

4.5
1

-

-

-

AC CLOCK LEVEL CONDITIONS

2

MIN. TYPICAL MAX. UNIT

IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical trans port (duty cycle=5/8)
A-clock low level
Charge Reset (CR) level on A-clock

5

4

8
10

-5

10
14
0

-5

V
V
V
V

OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. trans port = 3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level

4.75
2

5

3.5
10

3.5

5.25
10

V
V
V
V

OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub

1

During Charge Reset it is allowed to exceed maximum rating levels (see note 5).

2

All voltages in relation to SFS.

3

To set the VNS voltage for optimal Ver tical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.

4

Three-level cloc k is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration.

A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.

5

Charge Reset can be achieved in two ways:

5

5
0

10
3
10

10
10

V
V
V

• The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required (preferred).

• The typical CR level is applied to all image clocks simultaneously.

1999 November 5

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Timing diagrams (for default operation)

AC CHARACTERISTICS MIN. TYPICAL MAX. UNIT

Horizontal frequency (1/Tp)
Vertical frequency
Charge Reset (CR) time
Rise and fall times: image clocks (A)

1

Tp = 1 clock period

2

Duty cycle = 50% and phase shift of the C clocks is 120 degrees.

1

register clocks (C)
summing gate (SG)
reset gate (RG)

18
50

10

2

10
3
3
3

193.7
20
5
5
5

36
100

1/6 Tp
1/6 Tp
1/6 Tp

MHz
kHz
µs
ns
ns
ns
ns

Frame Timing

Sensor Output

SSC

A1

A2, A3, A4

CR

Ahigh

VD

BLC

EXT. SHUTTER

H
L
H
L
H
L
H
L
H

*

L
H
L
H
L
H
L

Line Timing

SSC

A1

A2

A3

A4

CR

AHigh

VD

BLC

H

L
H
L
H
L
H
L
H
L
H
L
H

*

L
H
L
H
L

Tp30

20472046 2048

Tp20

BlackDummy

D

Tp66

Tp112

BBD123

BBBB BBBB

Integration Time

Tp360

Tp138

Tp204

Tp230

Tp138

Tp138

Tp360

Tp396

Pixel Timing

SSC

C1

C2

C3

SG

RG

Tp = 1 / 18MHz = 55.56ns
Pixel output sequence: 7 dummy, 20 black, 4 timing, 3072 active, 4 timing, 20 black Line Time: 3487 x Tp = 193.7µs
* During AHigh = H the phiA high level is increased from 10V to 14V (This is necessary during readout only)

VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
A1 to A4: Vertical image clocks

1999 November 6

H
L
H
L
H
L
H
L
H
L
H
L

1Tp

Figure 3 - Timing diagrams

3127 pixels

Tp / 6

C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Line timing

SSC

A1

A2

A3

Pixel timing

A4

—> time

Y / Div.: 10V (A1, A2, A3, A 4); 5V (SSC)

Figure 4 - Vertical readout

C1

C2

C3

SG

RG

Y / Div. : 5V (C1, C2, C3); 10V (SG, RG)

Figure 5 - Start horizontal readout

1999 November 7

—> time

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Performance

The test conditions for the perfo rmance characteristics are as follows:

• All values are measured using typical operating conditions.

• VNS is adjusted as low as possible while maintaining proper
Ver tical Anti-Blooming.

• Sensor temperature = 60°C (333K).

• Horizontal transport frequency = 18MHz.

• Integration time = 10ms (unless specified otherwise).

• The light source is a lamp of 3200K in conjunction with neutral
density filters and a 1.7mm thick BG40 infrared cut-off filter. For
Linear Operation measurements, a temperature conversion filter
(Melles Griot type no. 03FCG261, -120 mired, thickness: 2.5mm)
is applied.

• Vertical transport frequency = 50kHz (unless specified otherwise).

LINEAR OPERATION MIN. TYPICAL MAX. UNIT

Linear dynamic range

1

Charge Transfer Efficiency 2 vertical
Charge Transfer Efficiency

2

horizontal
Image lag
Resolution (MTF) @ 42 lp/mm
Responsivity
Quantum efficiency @ 530 nm
Low Pass Shading
Random Non-Uniformity (RNU)

3

4

VNS required for good Vertical Anti-Blooming (VAB)
Power dissipation at 2.5 frames/s

1

Linear dynamic range is defined as the ratio of Q

2

Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer.

3

Low Pass Shading is defined as the ratio of the one-σ value of an 8x8 pixels blurred image (low-pass) to the mean signal value.

4

RNU is defined as the ratio of the one-σ value of the highpass image to the mean signal value at nominal light.

to read-out noise (the latter reduced by Correlated Double Sampling).

lin

4200:1(12bit)

65
60
20

18

0.999995

0.999999

70
26

2.0

0.3
24
610

0

5
5
28

%
%
kel/lux·s
%
%
%
V
mW

Linear Dynamic Range

14,000

35°C

45°C

55°C

LDR

12,000
10,000

8,000
6,000
4,000
2,000

0

0 5 10 15 20 25 30 35 40

Hor. Frequency (MHz)

Figure 6 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature

1999 November 8

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Maximum Read-out Speed

20
18
16
14
12
10

8

Images/sec.

6
4
2
0

0 102030405060708090100

4 outputs

2 outputs

1 output

Integration time (ms)

Figure 7 - Maximum number of images/second versus integration time

Quantum Efficiency

25

R

20

G

15

B

10

Quantum efficiency (%)

5

0

400 450 500 550 600 650 700

Wavelength (nm)

Figure 8 - Quantum efficiency versus wavelength

1999 November 9

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

LINEAR/SATURATION MIN. TYPICAL MAX. UNIT

Full-well capacity saturation level (Qmax )
Full-well capacity shading (Qmax, shading )
Full-well capacity linear operation (Qlin )
Charge handling capacity

4

1

2

3

Overexposure 5 handling

1

Qmax is determined from the lowpass filtered image.

2

Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax.

3

The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity.

4

Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer.

5

Overexposure over entire area while maintaining good Ver tical Anti-Blooming (VAB). It is tested by measuring the dar k line.

240

180

500
10
350
600
200

600
50

kel.
%
kel.
kel.
x Qmax level

Charge Handling vs. Integration/Transport Volta ge

600

10V/14V

500

400

9V/13V

Output Signal (kel.)

300

200

100

8V/12V

0

123456

Exposure (arbitrary units)

Figure 9 - Charge handling versus integration/transport voltage

1999 November 10

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

OUTPUT BUFFERS MIN. TYPICAL MAX. UNIT

Conversion factor
Mutual conversion factor matching (∆ACF)

1

Supply current
Bandwidth
Output impedance buffer (R

1

Matching of the four outputs is specified as ∆ACF with respect to reference measured at the operating point (Q

= 3.3kΩ, C

load

= 2pF)

load

57.5
0

4.5
110
400

DARK CONDITION MIN. TYPICAL MAX. UNIT

Dark current level @ 30° C
Dark current level @ 60° C
Fixed Pattern Noise

1

(FPN) @ 60° C

RMS readout noise @ 9MHz bandwidth after CDS

1

FPN is the one-σ value of the highpass image.

20

0.3
15
25

10
2

30

0.6
25
30

µV/el.
µV/el.
mA
MHz

Ω

/2).

lin

2

pA/cm

2

nA/cm
el.
el.

1000

)

2

100

10

Dark Current (pA/cm

1

0 102030405060

Dark Current

Temp. (oC)

Figure 10 - Dark current versus temperature

1999 November 11

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Application information

Current handling

One of the purposes of VPS is to drain the holes that are generated
during exposure of the sensor to light. Free electrons are either
transported to the VRD connection and, if excessive (from over­exposure), free electrons are drained to VNS. No current should
flow into any VPS connection of the sensor . During high ov erexposure
a total current 10 to 15mA through all VPS connections together
may be expected. The PNP emitter follower in the circuit diagram
(figure 11) serves these current requirements.

VNS drains superfluous electrons as a result of overexposure. In
other words, it only sinks current. During high overexposure a total
current of 10 to 15mA through all VNS connections together ma y be
expected. The NPN emitter follower in the circuit diagram meets
these current requirements. The clamp circuit, consisting of the diode
and electrolytic capacitor, enables the addition of a Charge Reset
(CR) pulse on top of an otherwise stable VNS v oltage . To protect the
CCD, the current resulting from this pulse should be limited. This
can be accomplished by designing a pulse generator with a rather
high output impedance.

Decoupling of DC voltages

All DC voltages (not VNS, which has additional CR pulses as
described above) should be decoupled with a 100nF decoupling
capacitor. This capacitor must be mounted as close as possible to
the sensor pin. Further noise reduction (by bandwidth limiting) is
achieved by the resistors in the connections between the sensor
and its voltage supplies. The electrons that build up the charge
packets that will reach the floating diffusions only add up to a small
current, which will flow through VRD . Theref ore a large series resistor
in the VRD connection may be used.

Outputs

T o limit the on-chip po wer dissipation, the output buff ers are designed
with open source outputs. Outputs to be used should therefore be
loaded with a current source or more simply with a resistance to
GND. In order to prevent the output (which typically has an output
impedance of about 400Ω) from bandwidth limitation as a result of
capacitive loading, load the output with an emitter follo wer b uilt from
a high-frequency transistor. Mount the base of this transistor as close
as possible to the sensor and keep the connection between the
emitter and the next stage short. The CCD output buffer can easily
be destroyed by ESD. By using this emitter follower, this danger is
suppressed; do NOT reintroduce this danger by measuring directly

on the output pin of the sensor with an oscilloscope probe. Instead,
measure on the output of the emitter follower. Slew rate limitation is
avoided by avoiding a too-small quiescent current in the emitter
follower; about 10mA should do the job. The collector of the emitter
follower should be decoupled properly to suppress the Miller effect
from the base-collector capacitance.
A CCD output load resistor of 3.3kΩ typically results in a bandwidth
of 110MHz. The bandwidth can be enlarged to about 130MHz by
using a resistor of 2.2kΩ instead, which, however, also enlarges the
on-chip power dissipation.

Device protection

The output buffers of the FTF3020-C are likely to be damaged if
VPS rises above SFD or RD at any time. This danger is most realistic
during power-on or power-off of the camera. The RD voltage should
always be lower than the SFD voltage.

Never exceed the maximum output current. This may damage the
device permanently. The maximum output current should be limited
to 10mA.
Be especially aware that the output buffers of these image sensors
are very sensitive to ESD damage.

Because of the fact that our CCDs are built on an n-type substrate,
we are dealing with some parasitic npn transistors. To avoid activ ation
of these transistors during switch-on and switch-off of the camera,
we recommend the application diagram of figure 11.

Unused sections

To reduce power consumption the following steps can be taken.
Connect unused output register pins (C1...C3, SG, OG) and unused
SFS pins to zero Volts.

Colour processing

In order to guarantee true colours, always use an external IR filter
type CM500(0)s, 1mm or similar. The cover glass itself is not an IR
filter.

More information

Detailed application information is provided in the application note
AN01 entitled ‘Camera Electronics for the mK x nK CCD Image
Sensor Family’.

1999 November 12

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Device Handling

An image sensor is a MOS device which can be destroy ed by electro­static discharge (ESD). Therefore, the device should be handled
with care.

Always store the de vice with short-circuiting clamps or on conductive
foam. Alwa ys s witch off all electric signals when inserting or removing
the sensor into or from a camera (the ESD protection in the CCD
image sensor process is less effective than the ESD protection of
standard CMOS circuits).

Being a high quality optical device, it is important that the cover
glass remain undamaged. When handling the sensor , use fingercots.

VSFD

CR pulse

0

27

Ω

BAT74
Schottky!

Ω

15
BAT74
Schottky!

10k

Ω

100nF

-

+

BAT74

BAT74

BC
850C

0.5-1mA

BC
850C

0.5-1mA

0.5-1mA

BC
860C

1uF 100nF

2mA

100nF

100nF

When cleaning the glass we recommend using ethanol (or possibly
water). Use of other liquids is strongly discouraged:

• if the cleaning liquid evaporates too quickly, rubbing is likely to
cause ESD damage.

• the cover glass and its coating can be damaged by other liquids.

Rub the window carefully and slowly.
Dry rubbing of the window may cause electro-static charges or

scratches which can destroy the device.

keep short

VNS

SFD

VPS

VRD

<10mm! keep short!

10k

Ω

Ω

BFR
92A

output for
preprocessing

10mA

OUT

VCS

VOG

100 Ω

3.3k

Ω

100nF

10k

100nF

100nF

1k

Ω

<7pF!

Figure 11 - Application diagram to protect the FTF3020-C

1999 November 13

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Pin configuration

The FTF3020-C is mounted in a Pin Grid Array (PGA) package with
96 pins in a 20x15 grid of 52.70 x 40.00 mm2. The position of pin A1
(quadrant W) is marked with a gold dot on top of the package.

Symbol Name Pin # W Pin # X Pin # Y Pin # Z

VNS
VNS
VNS
VNS
VPS
SFD
SFS
VCS
OG
RD
A1
A2
A3
A4
C1
C2
C3
SG
RG
OUT
NC
NC
NC
NC

N substrate
N substrate
N substrate
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
Image Clock (Phase 1)
Image Clock (Phase 2)
Image Clock (Phase 3)
Image Clock (Phase 4)
Register Clock (Phase 1)
Register Clock (Phase 2)
Register Clock (Phase 3)
Summing Gate
Reset Gate
Output
Not Connected
Not Connected
Not Connected
Not Connected

The image clock phases of quadrant W are internally connected to
X, and Y is connected to Z.

A1
A5
C2
G1
A2
B2
D2
C1
B3
D1
B5
A3
A4
B4

F2

F1
G2
E1
E2
B1

I1

I2
H1
H2

U1
U5
S2
M1
U2
T2
R2
S1
T3
R1
T5
U3
U4
T4
N2
N1
M2
P1
P2
T1
K1
K2

L1
L2

U10

U6
S9

M10

U9
T9
R9

S10

T8

R10

T6
U8
U7
T7
N9

N10

M9

E10

P9
T10
K10

K9

L10

L9

A10

A6
C9

G10

A9
B9
D9

C10

B8

D10

B6
A8
A7
B7
F9

F10

G9

P10

E9

B10

I10

I9

H10

H9

ABCDEFGHJ

10

9
8
7
6

5
4
3
2
1

Figure 12 - FTF3020-C pin configuration (top view)

TOP

Z

W

FTF3020-C

KLMNPRSTU

Y
X

1999 November 14

Philips Semiconductors Product specification

Full Frame CCD Image Sensor FTF3020-C

Pack age inf ormation

Top cover glass to top chip 2.4 ±0.25

Chip - bottom package 1.7 ±0.15

INDEX

MARK

PIN 1

SENSOR CRYSTAL

COVER GLASS

±

0.15

26.35

52.7

A

±

0.53

EPOXY GLUE

TOP VIEW

0.15

±

20

0.15

±

1.27

Chip - cover glass 1.3 ±0.20

Cover glass 1.0 ±0.05

Image sensor chip

1.4 / 100

0.40

±

40

COVER GLASS

0.15

±

4.57

STAND-OFF PIN

(2.54)

0.46

BOTTOM VIEW

±

48.26

Figure 13 - Mechanical drawing of the PGA package of the FTF3020-C

1999 November 15

0.27

±

0.05

0.20

±

35.56

A is the center of the image area.
Position of A:

26.35 ± 0.15 to left edge of package

20.00 ± 0.15 to upper edge of package

1.7 ± 0.15 to bottom of package
Angle of rotation: less than ± 1°

Sensor flatness: < 20 µm (P-V)
Cover glass: Cor ning 7059

Thickness of cover glass: 1 ± 0.05
Refractive index: nd = 1.53
Double sided AR coating < 1% (430-660 nm) reflection

All drawing units are in mm

Order codes

The sensors can be ordered using the following codes:

FTF3020-C sensors

Description Quality Grade Order Code

FTF3020-C/TG
FTF3020-C/EG
FTF3020-C/IG
FTF3020-C/HG

You can contact the Image Sensors division of Philips
Semiconductors at the following address:

Philips Semiconductors
Image Sensors
Internal Postbox WAG-05
Prof. Holstlaan 4
5656 AA Eindhoven
The Netherlands

phone +31 - 40 - 27 44 400
fax +31 - 40 - 27 44 090

www.semiconductors.philips.com/imagers/

Test grade
Economy grade
Industrial grade
High grade

9922 157 37431
9922 157 37451
9922 157 37421
9922 157 37411

Philips
Semiconductors

Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. © Philips Electronics N.V. 1999

9922 157 37411