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FSTD162861
20-Bit Bus Switch with Level Shifting
and 25
Ω Series Resistors in Outputs (Preliminary)
Preliminary
FSTD162861 20-Bit Bus Switch with Level Shifting and 25
June 2001
Revised June 2001
General Description
The Fairchild Switch FSTD162861 provides 20-bits of highspeed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground b ounce noise. A diode to V
integrated into the circuit to allow for leve l shifting b etween
5V inputs and 3.3V outputs.
The device is organ ized as a 10-bit or 20-bit b us switch.
When OE
nected to Port 1B. When OE
to Port 2B. When OE
exists between the A an d B Ports. The FSTD16 2861 has
equivalent 25
noise, eliminating the ne ed for external terminating re sistors.
is LOW, the switch is ON and Port 1A is con-
1
Ω series resistors to reduce signal-reflect ion
is LOW, Port 2A is connected
2
is HIGH, a high imped ance state
X
has been
CC
Features
■ 25Ω switch connection between two ports
■ Minimal propagation delay through the switch
■ Low l
CC
■ Zero bounce in flow-through mode
■ Control inputs compatible with TTL level
■ TruTranslation
3.3V outputs
voltage translation from 5.0V inp uts to
Ordering Code:
Order Number Package Number Package Description
FSTD162861MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Ω
Series Resistors in Outputs (Preliminary)
TruTranslation is a trademark of F airc hild Semiconduct or Corporation.
© 2001 Fairchild Semiconductor Corporation DS500063 www.fairchildsemi.com
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Logic Diagram Connection Diagram
FSTD162861
Truth Table Pin Descriptions
Inputs Inputs/Outputs
OE
LL1A
LH1A
HL Z 2A
HH Z Z
OE
1
2
1A, 1B 2A, 2B
= 1B 2A = 2B
= 1B Z
= 2B
Pin Name Description
, OE
OE
1
2
1A, 2A Bus A
1B, 2B Bus B
Preliminary
Bus Switch Enables
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Preliminary
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) (Note 2) −0.5V to +7.0V
S
) (Note 3) −0.5V to +7.0V
IN
) V
< 0V −50 mA
IK
IN
) Current 128 mA
) ±100 mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0 ns/V to 5 ns/V
Switch I/O 0 ns/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the d evice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
is the voltage observe d/ap plied at eith er the A or B Port acro ss
Note 2: V
S
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and ou t put diode curre nt ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
(Note 4)
) 4.5V to 5.5V
CC
) 0V to 5.5V
IN
) 0V to 5.5V
OUT
, tf)
r
)-40 °C to +85 °C
A
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
V
OH
I
I
I
OZ
R
ON
I
CC
∆ I
CC
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by the voltage drop between A and B pins at the indicated c urrent through the switch. On Resistanc e is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18 mA
HIGH Level Input Voltage 4.5 - 5.5 2.0 V
LOW Level Input Voltage 4.5 - 5.5 0.8 V
HIGH Level 4.5 - 5.5 See Figure 3 V
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
Switch On Resistance 4.5 20 26 38 Ω VIN = 0V, IIN = 64 mA
(Note 6) 4.5 20 27 40 Ω V
Quiescent Supply Current
Increase in I
per Input 5.5 2.5 mA One Input at 3.4V
CC
CC
(V)
010µAV
4.5 202848Ω VIN = 2.4V, IIN = 15 mA
5.5
TA = −40 °C to +85 °C
Min Typ
(Note 5)
Units Conditions
Max
1.5 mA
3mA
= 5.5V
IN
CC
= 0V, IIN = 30 mA
IN
OE1 = OE2 = GND
= VCC or GND, I
V
IN
OE1 = OE2 = V
VIN = VCC or GND, I
Other Inputs at VCC or GND
= 0
OUT
CC
= 0
OUT
FSTD162861
3 www.fairchildsemi.com
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Preliminary
AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50 pF, RU = RD = 500Ω
Symbol Parameter
FSTD162861
t
, t
PHL
t
PZH
t
PHZ
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the s witch and the 50pF load capacitance, wh en driven by an ideal volt age source (zero output impedance).
Propagation Delay Bus to Bus 1.25 ns VI = OPEN Figures 1,
PLH
(Note 7)
, t
Output Enable Time 1.0 6.0 ns VI = 7V for t
PZL
, t
Output Disable Time 1.0 7.0 ns VI = 7V for t
PLZ
L
= 4.5 – 5.5V
V
CC
Min Max
Units Conditions
VI = OPEN for t
VI = OPEN for t
PZL
PZH
PLZ
PHZ
Capacitance (Note 8)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 8: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Control Pin Input Capacitance 3.5 pF VCC = 5.0V, VIN = 0V
Input/Output Capacitance “OFF State” 6.0 pF VCC, OE = 5.0V, VIN = 0V
AC Loading and Waveforms
Figure
Number
2
Figures 1,
2
Figures 1,
2
Note: Input driven by 50Ω source terminated in 50Ω
includes load and stra y capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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Output Voltage HIGH vs. Supply Voltage
Preliminary
FSTD162861
FIGURE 3.
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Physical Dimensions inches (millimeters) unless otherwise noted
Series Resistors in Outputs (Preliminary)
Ω
Preliminary
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven s witch technol ogy used for several years i n its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
FSTD162861 20-Bit Bus Switch with Level Shifting and 25
1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
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2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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