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© 2000 Fairchild Semiconductor Corporation DS500313 www.fairchildsemi.com
June 2000
Revised June 2000
FSTD16211 24-Bit Bus Switch with Level Shifting
FSTD16211
24-Bit Bus Switch with Level Shifting
General Description
The Fairchild Sw itch FSTD162 11 provides 24-bits of hi ghspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground b ounce noise. A diode to V
CC
has been
integrated into the circuit to allow for level sh ifting b etween
5V inputs and 3.3V outputs.
The device is organi zed as a 12-bit or 24-bit b us switch.
When OE
1
is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE
2
is LOW, Port 2A is connected
to Port 2B. When OE
1/2
is HIGH, a high impedance state
exists between the A and B Ports.
Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
CC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Diagram
Truth Table
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
FSTD16211MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Inputs Inputs/Outputs
OE
1
OE
2
1A, 1B 2A, 2B
LL1A = 1B 2A = 2B
LH1A
= 1B Z
HLZ2A
= 2B
HHZZ
Pin Name Description
OE
1
, OE
2
Bus Switch Enables
1A, 2A Bus A
1B, 2B Bus B
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FSTD16211
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 4)
Note 1: The “Absolute Maximum Ratings” are those values beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: V
S
is the volt age observed / applied at either A or B Ports across the
switch.
Note 3: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 5: Typi c al values are at VCC = 5.0V and TA= +25°C
Note 6: Measured by the volta ge drop between A and B pi ns at th e indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
S
) (Note 2) −0.5V to +7.0V
DC Input Control Pin Voltage (V
IN
)(Note 3) −0.5V to +7.0V
DC Input Diode Current (l
IK
) V
IN
< 0V −50mA
DC Output (I
OUT
) 128mA
DC V
CC
/GND Current (ICC/I
GND
) +/− 100mA
Storage Temperature Range (T
STG
) −65°C to +150 °C
Power Supply Operating (V
CC)
4.5V to 5.5V
Input Voltage (V
IN
)0V to 5.5V
Output Voltage (V
OUT
)0V to 5.5V
Input Rise and Fall Time (t
r
, tf)
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
A
)-40 °C to +85 °C
Symbol Parameter
V
CC
TA = −40 °C to +85 °C
Units Conditions
(V) Min
Typ
(Note 5)
Max
V
IK
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
V
IH
HIGH Level Input Voltage 4.5–5.5 2.0 V
V
IL
LOW Level Input Voltage 4.5–5.5 0.8 V
V
OH
HIGH Level 4.5–5.5 See Figure 3 V
I
I
Input Leakage Current 5.5 ±1.0 µA0≤ VIN ≤5.5V
010µAV
IN
= 5.5V
I
OZ
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V
CC
R
ON
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 6) 4.5 4 7 Ω V
IN
= 0V, IIN = 30mA
4.5 35 50 Ω VIN = 2.4V, IIN = 15mA
I
CC
Quiescent Supply Current 5.5 1.5 mA OE1 = OE2 = GND
V
IN
= VCC or GND, I
OUT
= 0
10 µAOE1 = OE2 = V
CC
VIN = VCC or GND, I
OUT
= 0
∆ I
CC
Increase in I
CC
per Input 5.5 2.5 mA One input at 3.4V
Other inputs at VCC or GND
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FSTD16211
AC Electrical Characteristics
Note 7: This parameter is guara nteed by design but is not te s t ed. The bus switch contribut es no propagat ion delay oth er than the RC de lay of the typical ON
resistance of the switc h and the 50pF load capac it ance, when driven by an ideal voltage source (zero output impedance ).
Capacitance (Note 8)
Note 8: TA = +25°C, f = 1 MHz, Ca pacitance is characteriz ed but not tested.
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, t
W
= 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
T
A
= −40 °C to +85 °C,
Units Conditions
C
L
= 50pF, RU = RD = 500Ω
Figure
V
CC
= 4.5 – 5.5V
Number
Min Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 7) 0.25 ns VI = OPEN Figures
1, 2
t
PZH
, t
PZL
Output Enable Time 1.5 5.5 ns VI = 7V for t
PZL
Figures
1, 2
VI = OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time 1.5 6.5 ns VI = 7V for t
PLZ
Figures
1, 2
VI = OPEN for t
PHZ
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 3.5 pF VCC = 5.0V
C
I/O
Input/Output Capacitance 5.5 pF VCC, OE = 5.0V
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FSTD16211
Output Voltage HIGH vs. Supply Voltage
FIGURE 3.
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FSTD16211 24-Bit Bus Switch with Level Shifting
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.
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