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MERICAN MICROSYSTEMS, IN
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American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
3.13.01
FS6286-01
Dual PLL Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
1.0 Features
• Dual phase-locked loop (PLL) device with three output clock frequencies
• 3.3V supply voltage
• Small circuit board footprint (8-pin 0.150″ SOIC)
• OE/LAT pin enables/disables CLKC output
(see Table 1)
• SELC is latched on rising edge of OE/LAT input
• Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
1 8
2
3
4
7
6
5
OE/LAT
XIN
XOUT/REFIN
VDD
CLKB
VSS
CLKC/SELC
CLKA
FS6286
8-pin (0.150″) SOIC
2.0 Description
The FS6286 is a monolithic CMOS clock generator IC
designed to m inimize c ost and com ponent c ount in di gital
video/audio systems.
All frequencies are r atiom etr icall y derived f rom the c rystal
oscillator frequency. The locking of all the output frequencies together can e liminate unpredict able artifacts in
video systems and reduce electromagnetic interference
(EMI) due to frequency harmonic stacking.
Table 1: Crystal / Output Frequencies
DEVICE
f
XIN
(MHz)
CLKA **
(MHz)
CLKB **
(MHz)
CLKC
(MHz)
SELC=0
40.000
(f
XIN
* 176 / 63)
FS6286-01
14.31818
25.0000
(f
XIN
* 110 / 63)
25.0000
(f
XIN
* 110 / 63)
SELC=1
80.000
(f
XIN
*352 / 63 )
** - CLKA and CLKB ARE ALWAYS ENABLED (NOT AFFECTED BY OE/LAT
INPUT LEVEL)
NOTE: Contact AMI for custom PLL frequencies, OE, and LAT options
Figure 2: Block Diagram
CRYSTAL
OSC.
FS6286
XOUT/
REFIN
XIN
CLKC/
SELC
CLKA
DIVIDER
ARRAY
v
PLL
PLL
CLKB
OE/LAT
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