AMERICAN MICROSYSTEMS, INC.
August 2000
4
8.17.00
FS6183-04
FS6183-04FS6183-04
FS6183-04
1 PLL
1 PLL1 PLL
1 PLL Clock Generator IC
Clock Generator ICClock Generator IC
Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
f
XTAL
= 13.5MHz; CL = 10pF 20 mA
Crystal Oscillator
Crystal Resonator Frequency f
XTAL
Fundamental Mode - 13.5 - MHz
Crystal Loading Capacitance C
L(xtal)
As seen by a crystal connected to XIN and
XOUT
18 pF
Crystal Oscillator Drive Transconductance gm
OSC
VDD = 3.3V 16
mSiemens
Oscillator Source Current I
OH
VDD = 3.3V
V(XIN) = 0V, V(XOUT) = 0V
-18 mA
Oscillator Sink Current I
OL
VDD = 3.3V
V(XIN) = VDD, V(XOUT) = VDD
23 mA
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current * I
OH
VO = 2.0V 40 m A
Low-Level Output Sink Current * I
OL
VO = 0.4V 17 m A
z
OH
VO = 0.1VDD; output driving high 25
Output Impedance *
z
OL
VO = 0.1VDD; output driving low 25
Ω
Short Circuit Source Current * I
OSH
VO = 0V; shorted for 30s, max. -55 mA
Short Circuit Sink Current * I
OSL
VO = 3.3V; shorted for 30s, max. 55 mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN. TYP. MAX. UNITS
Clock Outputs (CLKx)
Duty Cycle * thi / t
clk
; Measured at VDD/2 45 55 %
Jitter, Absolute Period (pk-pk) *
t
j(∆P)
From rising edge to next rising edge at
V
DD
/2, CL = 10pF
300 ps
Jitter, RMS Long Term (σy(τ)) *
t
j(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
150 ps
Rise Time * t
r
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1 ns
Fall Time * t
f
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1 ns
Output Frequency Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm