Page 1
FQD3N50C / FQU3N50C
500V N-Channel MOSFET
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
March 2008
®
QFET
Features
• 2.5A, 500V, R
• Low gate charge ( typical 10 nC)
• Low Crss ( typical 8.5pF)
•Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS compliant
= 2.5Ω @VGS = 10 V
DS(on)
GS
D-PAK
FQD Series
D
GSD
Absolute Maximum Ratings
Symbol Parameter
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt
P
D
TJ, T
STG
T
L
Drain-Source Voltage 500 V
Drain Current - Continuous (TC = 25°C) 2.5 A
- Continuous (TC = 100°C) 1.5 A
Drain Current - Pulsed
Gate-Source Voltage ± 30 V
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Power Dissipation (TC = 25°C) 35 W
- Derate above 25°C 0.28 W/°C
Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies, active power factor
correction, electronic lamp ballast based on half bridge
topology.
D
I-PAK
FQU Series
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
G
S
FQD3N50C/FQU3N50C
10 A
200 mJ
2.5 A
3.5 mJ
4.5 V/ns
300 °C
Units
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θJA
R
θJA
* When mounted on the minimum pad size recommended (PCB Mount)
©2008 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FQD3N50C / FQU3N50C Rev. B
Thermal Resistance, Junction-to-Case -- 3.5 °C/W
Thermal Resistance, Junction-to-Ambient* -- 50 °C/W
Thermal Resistance, Junction-to-Ambient -- 110 °C/W
Page 2
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FQD3N50C FQD3N50CTM D-PAK 380mm 16mm 2500
FQD3N50C FQD3N50CTF D-PAK 380mm 16mm 2500
FQU3N50C FQU3N50CTU I-PAK - - 70
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
Electrical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BV
∆T
J
I
DSS
I
GSSF
I
GSSR
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Dynamic Characteristics
C
iss
C
oss
C
rss
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
NOTES:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 58mH, IAS =2.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 2.5A, di/dt ≤200A/µs, VDD ≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temp er at ur e
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 500 -- -- V
/
DSS
Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.7 -- V/°C
Zero Gate Voltage Drain Current VDS = 500 V, VGS = 0 V -- -- 1 µA
VDS = 400 V, TC = 125°C -- -- 10 µA
Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA
Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.0 -- 4.0 V
Static Drain-Source On-Resistance VGS = 10 V, ID = 1.25 A -- 2.1 2.5 Ω
Forward Transconductance VDS = 40 V, ID = 1.25 A (Note 4) -- 1.5 -- S
Input Capacitance VDS = 25 V, VGS = 0 V,
Output Capacitance -- 50 65 pF
Reverse Transfer Capacitance -- 8.5 11 pF
f = 1.0 MHz
Turn-On Delay Time VDD = 250 V, ID = 2.5A,
Turn-On Rise Time --
RG = 25 Ω
Turn-Off Delay Time -Turn-Off Fall Time --
(Note 4, 5)
Total Gate Charge VDS = 400 V, ID = 2.5A,
Gate-Source Charge -Gate-Drain Charge --
VGS = 10 V
(Note 4, 5)
-- 280 365 pF
--
10 30
25 60
35 80
25 60
--
10 13
1.5
5.5
Maximum Continuous Drain-Source Diode Forward Current -- -- 2.5 A
Maximum Pulsed Drain-Source Diode Forward Current -- -- 10 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.5 A -- -- 1.4 V
Reverse Recovery Time VGS = 0 V, IS = 3 A,
Reverse Recovery Charge -- 0.7 --
Starting TJ = 25°C
DSS,
dIF / dt = 100 A/µs (Note 4)
-- 170 -- ns
ns
ns
ns
ns
nC
-- nC
-- nC
µC
FQD3N50C / FQU3N50C Rev. B
2 www.fairchildsemi.com
Page 3
Typical Performance Characteristics
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
-55°C
Note
1. V
2. 250
= 40V
DS
µs Pulse Tes t
, Drain Current [A]
D
I
10
10
10
V
Top : 15.0 V
10.0 V
1
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
0
-1
-1
10
GS
0
10
VDS, Drain-Source Voltage [V]
1
10
150°C
Notes :
1. 250
2. T
1
10
µs Pulse Test
= 25°C
C
0
10
, Drain Current [A]
D
I
-1
10
246810
25°C
VGS , Gate-Source Voltage [V]
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperatue
8.0
7.5
7.0
6.5
6.0
5.5
5.0
[Ω],
4.5
DS(ON)
4.0
R
3.5
3.0
Drain-Source On-Resistance
2.5
2.0
1.5
0246810
VGS = 10V
VGS = 20V
Note : TJ = 25°C
ID, Drain Current [A]
0
10
150°C
, Reverse Drain Current [A]
DR
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-Drain voltage [V]
25°C
Notes :
1. V
= 0V
GS
2. 250
µs Pulse Test
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
600
400
200
Capacitances [pF]
0
-1
10
VDS, Drain-Source Voltage [V]
FQD3N50C / FQU3N50C Rev. B
C
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
C
oss
gd
C
= C
rss
gd
C
iss
C
oss
Note ;
10
1
1. V
2. f = 1 MHz
C
rss
0
10
= 0 V
GS
12
10
8
VDS = 100V
VDS = 250V
VDS = 400V
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0510
QG, Total Gate Cha r g e [n C]
3 www.fairchildsemi.com
Note : ID = 3A
Page 4
Typical Performance Characteristics (Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
1.2
3.0
2.5
1.1
2.0
1.0
, (Normalized)
BV
DSS
0.9
Notes :
1. V
2. I
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
TJ, Junction Temperature [°C]
= 0 V
GS
= 250µA
D
1.5
, (Normalized)
1.0
DS(ON)
R
0.5
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
TJ, Junction Temperature [°C]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
, Drain Current [A]
D
I
2
10
1
10
Operation in This Area
is Limited by R
DS(on)
100 µs
3
2
1 ms
0
10
-1
10
-2
10
0
10
Notes :
1. T
2. T
3. Single Pulse
1
10
= 25°C
C
= 150°C
J
VDS, Drain-Source Voltage [V]
10 ms
100 ms
DC
1
, Drain Current [A]
D
I
2
10
3
10
0
25 50 75 100 125 150
TC, Case Temperature [°C]
Notes :
1. V
2. I
GS
= 1.5 A
D
= 10 V
Figure 11. Transient Thermal Response Curve
D=0.5
0
10
0.2
0.1
0.05
0.02
-1
10
0.01
FQD3N50C / FQU3N50C Rev. B
(t), Thermal Response
θJC
Z
10
-2
10
-5
single pulse
-4
10
t1, Square Wave Pulse Duration [sec]
Notes :
1. Z
(t) = 3.5 ° C/W Max.
θJC
2. D uty Facto r, D =t
3. TJM - TC = PDM * Z
P
DM
-3
10
-2
10
-1
10
1/t2
(t)
θJC
t
1
t
2
0
10
1
10
4 www.fairchildsemi.com
Page 5
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
FQD3N50C / FQU3N50C Rev. B
Unclamped Inductive Switching Test Circuit & Waveforms
5 www.fairchildsemi.com
Page 6
Peak Diode Recovery dv/dt Test Circuit & Waveforms
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
FQD3N50C / FQU3N50C Rev. B
6 www.fairchildsemi.com
Page 7
Mechanical Dimensions
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
D-PAK
FQD3N50C / FQU3N50C Rev. B
Dimensions in Millimeters
7 www.fairchildsemi.com
Page 8
Mechanical Dimensions (Continued)
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
I-PAK
FQD3N50C / FQU3N50C Rev. B
Dimensions in Millimeters
8 www.fairchildsemi.com
Page 9
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FQD3N50C / FQU3N50C 500V N-Channel MOSFET
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICEN SE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided
2. A critical component in any component of a life support,
device, or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in a
significant injury of the user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be pub-
Preliminary First Production
lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification Needed Full Production
Obsolete Not In Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve the design.
This datasheet contains specifications on a product that is discontinued by
Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
9 www.fairchildsemi.com
FQD3N50C / FQU3N50C Rev. B
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