Datasheet FQU3N25, FQD3N25 Datasheet (Fairchild Semiconductor)

FQD3N25 / FQU3N25

250V N-Channel MOSFET

November 2000

QFET

QFETQFET

TM

General Description

FQD3N25 / FQU3N25

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supply.

D

S

D-PAK

= 25°C)

C

G

D

S

= 25°C unless otherwise noted

C

= 25°C)

C

= 100°C)

C

FQD Series

- Continuous (T

- Derate above 25°C 0.24 W/°C

G

Absolute Maximum Ratings T

Symbol Parameter FQD3N25 / FQU3N25 Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

, T

T

J

STG

T

L

Drain-Source Voltage 250 V Drain Current

Drain Current - Pulsed Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

Features

• 2.4A, 250V, R

• Low gate charge ( typical 4.0 nC)

• Low Crss ( typical 4.7 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

I-PAK

FQU Series

(Note 1)

(Note 2) (Note 1) (Note 1) (Note 3)

= 2.2Ω @VGS = 10 V

DS(on)

G

2.4 A

1.5 A

9.6 A

40 mJ

2.4 A

3.0 mJ

5.5 V/ns

2.5 W 30 W

300 °C

!

D

!

"

" "

"

!

S

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 4.17 °C/W Thermal Resistance, Junction-to-Ambient * -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W

Rev. A, November 2000

FQD3N25 / FQU3N25

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter T e s t Conditions Min Typ Max Units

Off Characteristics

BV

DSS

∆BV

DSS

/ ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

I

= 250 µA, Referenced to 25°C

D

V

= 250 V, VGS = 0 V

DS

V

= 200 V, TC = 125°C

DS

V

= 30 V, VDS = 0 V

GS

= -30 V, VDS = 0 V

V

GS

250 -- -- V

-- 0.24 -- V/°C

-- -- 1 µA

-- -- 10 µA

-- -- 100 nA

-- -- -100 nA

On Characteristics

V R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage Static Drain-Source

On-Resistance Forward Transconductance

V

= VGS, ID = 250 µA

DS

= 10 V, ID = 1.2 A

V

GS

= 50 V, ID = 1.2 A

V

DS

(Note 4)

3.0 -- 5.0 V

-- 1.75 2.2 Ω

-- 1.43 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance -- 30 40 pF Reverse Transfer Capacitance -- 4.7 6.1 pF

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 130 170 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 25 60 ns Turn-Off Delay Time -- 5.5 21 ns Turn-Off Fall Time -- 20 50 ns Total Gate Charge Gate-Source Charge -- 1.1 -- nC Gate-Drain Charge -- 2.2 -- nC

= 125 V, ID = 2.8 A,

V

DD

= 25 Ω

R

G

V

= 200 V, ID = 2.8 A,

DS

V

GS

= 10 V

(Note 4, 5)

-- 6.6 23 ns

-- 4.0 5.2 nC

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 11mH, IAS = 2.4A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 2.8A, di/dt ≤ 300A/µs, VDD ≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- 2.4 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 9.6 A

= 0 V, IS = 2.4 A

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 0.3 -- µC

Starting TJ = 25°C

DSS,

V

GS

= 0 V, IS = 2.8 A,

V

GS

/ dt = 100 A/µs

dI

F

-- -- 1.5 V

-- 100 -- ns

(Note 4)

Rev. A, November 2000

Typical Characteristics

V

GS

Top : 15.0 V

10.0 V

8.0 V

7.0 V

6.5 V

6.0 V

0

10

Bottom : 5.5 V

FQD3N25 / FQU3N25

, Drain Current [A]

-1

D

10

I

-1

10

VDS, Drain-Source Voltage [V]

0

10

℃

150

℃

-1

10

, Drain Current [A]

D

※

Notes :

1. 250μs Pulse Test

℃

2. T

= 25

C

0

10

1

10

I

-2

10

246810

25

-55

VGS , Gate-Source Voltage [V]

℃

※

Notes :

1. V

= 50V

DS

2. 250μs Pulse Test

Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s

10

8

],

6

Ω

[

DS(on)

R

4

2

Drain-Source On-Resistance

0

0123456

VGS = 10V

VGS = 20V

ID , Drain Curr e n t [A]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

300

250

200

150

100

Capacitance [pF]

50

0

-1

10

VDS, Drain-Source Voltage [V]

C

= Cgs + Cgd (Cds = shorted)

iss

= Cds + C

C

oss

gd

C

= C

rss

gd

C

iss

C

oss

※

Notes :

1. V

GS

10

2. f = 1 MH z

1

C

rss

0

10

= 0 V

0

10

※

, Reverse Drain Current [A]

DR

I

-1

10

0.2 0.4 0.6 0.8 1.0 1.2 1.4

℃

150

℃

25

Notes :

= 0V

1. V

GS

2. 250μs Pulse Test

VSD, Source-Drain voltage [V]

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

VDS = 50V

VDS = 125V

VDS = 200V

※

Note : I

= 2.8 A

D

12

10

8

6

4

, Gate-Source Voltage [V]

2

GS

V

0

012345

QG, Tota l Gate C harge [nC]

Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics

Typical Characteristics (Continued)

FQD3N25 / FQU3N25

1.2

1.1

1.0

, (Normalized)

DSS

BV

0.9

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

※

1. V

2. I

Notes :

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Ope rat io n in T h is Ar e a is Lim ited by R

※

Notes :

1. T

= 25 oC

C

= 150 oC

2. T

J

3. Single Pulse

1

10

DS(on)

1 ms

10 ms

DC

2

10

1

10

0

10

, Drain Current [A]

D

-1

I

10

-2

10

0

10

VDS, Drain-Source Voltage [V]

= 0 V

GS

= 250 μA

D

100 µs

3.0

2.5

2.0

1.5

, (No rmaliz ed)

1.0

DS(ON)

R

Drain-Source On-Resistance

0.5

0.0

-100 -50 0 50 100 150 200

※

Notes :

1. V

= 10 V

GS

2. I

= 1.4 A

D

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs. Temperature

2.5

2.0

1.5

1.0

, Drain Current [A]

D

I

0.5

0.0 25 50 75 100 125 150

TC, Case Temperature [℃]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

D=0.5

0

10

0.2

0.1

0.05

0.02

(t), Thermal Response

0.01

JC

-1

10

θ

Z

-5

10

single pulse

-4

10

t

1

-3

10

-2

10

, S q u a re W av e P u lse D u ra tion [s e c ]

※

N o te s :

1. Z

(t) = 4.17 ℃/W M a x .

θ

JC

2. D u ty F a c to r , D = t

3. TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

1/t2

(t)

θ

JC

0

1

10

Figure 11. Transient Thermal Response Curve

Rev. A, November 2000

Gate Charge Test Circuit & Waveform

V

GS

DS

GS

10V

Q

g

Q

gs

Q

gd

Charge

Same Type

50KΩ

200nF

12V

FQD3N25 / FQU3N25

200nF

3mA

300nF

V

GS

Same Type

as DUT

DUT

V

Resistive Switching Test Circuit & Waveforms

R

L

10V

DUT

L

V

DD

V

DS

V

GS

R

G

V

DS

90%

10%

V

GS

t

d(on)tr

t

on

t

d(off)

t

f

t

off

10V

Unclamped Inductive Switching Test Circuit & Waveforms

BV

DSS

L

LL

V

DS

BV

DSS

V

DSS

I

AS

DD

I

IDI

D

R

G

DUT

t

p

V

DD

1

----

E

=LI

E

=LI

AS

2

AS

ID (t)

t

2

p

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

DUT

I

SD

Driver

R

G

V

GS

+

V

DS

_

L

LL

Same Type

as DUT

• dv/dt controlled by R

•ISDcontroll ed by pulse period

G

FQD3N25 / FQU3N25

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

IFM, Body Diode Forward Current

I

RM

Body Diode Reverse Current

Body Diode Recoverydv/dt

V

SD

Body Diode

Forward Voltage Drop

di/dt

10V

V

DD

Rev. A, November 2000

Package Dimensions

DPAK

6.60 ±0.20

5.34 ±0.30

FQD3N25 / FQU3N25

0.60 ±0.20

0.80 ±0.20

MAX0.96

2.30TYP

[2.30±0.20]

(4.34)(0.50) (0.50)

2.70 ±0.20

0.76 ±0.10

2.30TYP

[2.30±0.20]

0.70 ±0.20

6.10 ±0.20

9.50 ±0.30

±0.10

0.91

0.89 ±0.10

6.60 ±0.20 (5.34)

(5.04) (1.50)

2.30 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

(0.90)

(0.70)

MIN0.55

(1.00)

9.50 ±0.30

(2XR0.25)

6.10 ±0.20

2.70 ±0.20 (0.10) (3.05)

0.76 ±0.10

FQD3N25 / FQU3N25

Package Dimensions

6.60 ±0.20

5.34 ±0.20

(0.50) (0.50)(4.34)

0.60 ±0.20

(Continued)

IPAK

0.70 ±0.20

2.30 ±0.20

0.50 ±0.10

6.10 ±0.20

0.80 ±0.10

MAX0.96

0.76 ±0.10

2.30TYP

[2.30±0.20]

1.80 ±0.20

2.30TYP

[2.30±0.20]

16.10 ±0.30

9.30 ±0.30

0.50 ±0.10

Rev. A, November 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOL T™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna

TM

FACT™ FACT Quiet Series™



FAST FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™

PACMAN™ POP™ PowerTrench



QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART ST ART™ St ar* Power™ Stealth™



SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET



VCX™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN T O IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. H1

Datasheet FQU3N25, FQD3N25 Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual