Datasheet FQU1N50B Datasheet (Fairchild Semiconductor)

FQD1N50B / FQU1N50B

500V N-Channel MOSFET

May 2000

QFET

QFETQFET

TM

General Description

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary,

FQD1N50B / FQU1N50B

planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply, power factor correction, electronic lamp ballast based on half bridge.

D

S

D-PAK

= 25°C)

C

G

D

S

= 25°C unless otherwise noted

C

= 25°C)

C

= 100°C)

C

FQD Series

- Continuous (T

- Derate above 25°C 0.2 W/°C

G

Absolute Maximum Ratings T

Symbol Parameter FQD1N50 / FQU1N50 Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

, T

T

J

STG

T

L

Drain-Source Voltage 500 V Drain Current

Drain Current - Pulsed Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

Features

• 1.1A, 500V, R

• Low gate charge ( typical 4.0 nC)

• Low Crss ( typical 3.0 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

I-PAK

FQU Series

(Note 1)

(Note 2) (Note 1) (Note 1) (Note 3)

= 9.0Ω @VGS = 10 V

DS(on)

G

1.1 A

0.7 A

4.4 A

80 mJ

1.1 A

2.5 mJ

4.5 V/ns

2.5 W 25 W

300 °C

!

D

!

"

" "

"

!

S

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 5.0 °C/W Thermal Resistance, Junction-to-Ambient * -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W

Rev. A, May 2000

FQD1N50B / FQU1N50B

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter T e s t Conditions Min Typ Max Units

Off Characteristics

BV

DSS

∆BV

DSS

/ ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

I

= 250 µA, Referenced to 25°C

D

V

= 500 V, VGS = 0 V

DS

V

= 400 V, TC = 125°C

DS

V

= 30 V, VDS = 0 V

GS

= -30 V, VDS = 0 V

V

GS

500 -- -- V

-- 0.5 -- V/°C

-- -- 1 µA

-- -- 10 µA

-- -- 100 nA

-- -- -100 nA

On Characteristics

V

R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage

Static Drain-Source On-Resistance

Forward Transconductance

V

DS

V

= VGS, ID = 250 mA

DS

= 10 V, ID = 0.55 A

V

GS

= 50 V, ID = 0.55 A

V

DS

(Note 4)

2.3 3.0 3.7 V

3.6 4.3 5.0 V

-- 6.8 9.0 Ω

-- 0.98 -- S

= VGS, ID = 250 µA

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance -- 20 30 pF Reverse Transfer Capacitance -- 3 4 pF

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 115 150 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 25 60 ns Turn-Off Delay Time -- 8 25 ns Turn-Off Fall Time -- 20 50 ns Total Gate Charge Gate-Source Charge -- 1.1 -- nC Gate-Drain Charge -- 2.2 -- nC

= 250 V, ID = 1.4 A,

V

DD

= 25 Ω

R

G

V

= 400 V, ID = 1.4 A,

DS

V

GS

= 10 V

(Note 4, 5)

-- 5 20 ns

-- 4.0 5.5 nC

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 120mH, IAS = 1.1A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 1.4A, di/dt ≤ 200A/µs, VDD≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- 1.4 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 4.4 A

V

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 0.4 -- µC

Starting TJ = 25°C

DSS,

= 0 V, IS = 1.4 A

GS

= 0 V, IS = 1.4 A,

V

GS

dI

/ dt = 100 A/µs

F

-- -- 1.4 V

-- 170 -- ns

(Note 4)

Rev. A, May 2000

Typical Characteristics

V

GS

Top : 1 5 V 10 V

8.0 V

0

7.0 V

10

6.5 V

6.0 V Botto m : 5.5 V

-1

10

, Drain Current [A]

D

I

FQD1N50B / FQU1N50B

-2

10

-1

10

24

20

16

, [Ω]

12

DS(on)

R

8

Drain-Source On-Resistance

4

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

10

VDS , Drain-Source Voltage [V]

VGS = 10V

VGS = 20V

ID , Drai n Curren t [A]

※

Notes :

1. 250μs Pulse Test

℃

2. T

= 25

C

1

10

※

℃

Note : T

= 25

J

0

10

℃

150

-1

10

, Dra in Curre n t [A ]

D

I

-2

10

246810

℃

25

℃

-55

※

Note s :

1. V

= 50V

DS

2. 250μs Pulse Test

VGS , Gate-Source Voltage [V]

Figure 2. Transfer Characteristics.Figure 1. On-Region Char acteristics.

0

10

-1

10

℃

, Reverse Drain Current [A]

DR

I

-2

10

0.2 0.4 0.6 0.8 1.0 1.2

150

℃

25

※

Notes :

1. V

= 0V

GS

2. 250μs Pulse Test

VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs

Drain Current and Ga te Voltage.

200

150

100

Capacitance [pF]

50

0

-1

10

Figure 5. Capacitance Characteristics. Figure 6. Gate -Charge Characteristics.

C C C

C

iss

C

oss

C

rss

0

10

VDS, Drain-Source Voltage [V]

= Cgs + Cgd (Cds = shorted)

iss

= Cds + C

oss

gd

= C

rss

gd

※

Notes :

= 0 V

1. V

GS

2. f = 1 MH z

1

10

Figure 4. Body Diode Forward Voltage

Variation with Source Current

and Temperature.

12

10

8

6

4

, Gate-Source Voltage [V]

2

GS

V

0

012345

VDS = 100V

VDS = 250V

VDS = 400V

QG, Tota l Gate Charge [n C]

※

Notes : I

= 1.4 A

D

Rev. A, May 2000

Typical Characteristics (Continued)

FQD1N50B / FQU1N50B

1.2

1.1

1.0

, (Norm a liz e d )

DSS

BV

0.9

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

※

1. V

2. I

Notes :

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs Temperature.

1

10

0

10

-1

, Drain Current [A]

10

D

I

-2

10

0

10

Ope rat io n in T h is Ar e a is Limited by R

DS(on)

10 ms

DC

※

Notes :

1. T

= 25 oC

C

= 150 oC

2. T

J

3. Single Pulse

1

10

2

10

VDS, Drain-Source Voltage [V]

1 ms

= 0 V

GS

= 250

D

100 µs

3.0

2.5

2.0

μ

A

1.5

, (Normalized)

1.0

DS(ON)

R

Drain-Source On-Resistance

0.5

0.0

-100 -50 0 50 100 150 200

※

Notes :

1. V

= 10 V

GS

2. I

= 0.7 A

D

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs Temperature.

1.2

0.9

3

10

0.6

, Drain Current [A]

D

I

0.3

0.0 25 50 75 100 125 150

TC, Case Temperature [℃]

Figure 9. Maximum Safe Op erating Area. Figure 10. Maximum Dr ai n Cu r re nt

vs Case Temperature.

D=0.5

※

0

0.2

10

0.1

0.05

0.02

(t), Therm al Response

0.01

JC

-1

10

θ

Z

-5

10

single pulse

-4

10

-3

10

-2

10

N o te s :

1. Z

(t) = 5.0 ℃/W Ma x .

θ

JC

2. D u ty F a c to r , D = t

3. TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

1/t2

(t)

θ

JC

0

1

10

t1, S q u a re W a v e P u lse D ura tio n [s e c]

Figure 11. Transient Thermal Response Curve.

Rev. A, May 2000

Gate Charge Test Circuit & Waveform

50KΩ

200nF

12V

200nF

300nF

V

GS

FQD1N50B / FQU1N50B

3mA

Resistive Switching Test Circuit & Waveforms

V

DS

V

GS

R

G

10V

Same Type

as DUT

DUT

R

L

DUT

V

GS

Q

g

10V

V

DS

V

DD

Q

gs

V

DS

90%

10%

V

GS

t

d(on)tr

g

Q

gd

Charge

t

d(off)

t

f

t

on

f

t

off

R

G

10V

t

p

Unclamped Inductive Switching Test Circuit & Waveforms

L

LL

V

DS

BV

DSS

V

DSS

I

AS

DD

I

IDI

D

V

DD

DUT

1

----

E

=LI

E

=LI

AS

2

AS

ID (t)

t

2

p

BV

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Rev. A, May 2000

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

DUT

I

SD

Driver

R

G

V

GS

+

V

DS

_

L

LL

Same Type

as DUT

• dv/dt controlled by R

•ISDcontroll ed by pulse peri od

G

FQD1N50B / FQU1N50B

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

IFM, Body Diode Forward Current

I

RM

Body Diode Reverse Current

Body Diode Recoverydv/dt

V

SD

Body Diode

Forward Voltage Drop

di/dt

10V

V

DD

Rev. A, May 2000

Package Dimensions

DPAK

6.60 ±0.20

5.34 ±0.30 (4.34)(0.50) (0.50)

FQD1N50B / FQU1N50B

0.60 ±0.20

0.80 ±0.20

MAX0.96

2.30TYP

[2.30±0.20]

2.70 ±0.20

0.76 ±0.10

2.30TYP

[2.30±0.20]

0.70 ±0.20

6.10 ±0.20

9.50 ±0.30

±0.10

0.91

0.89 ±0.10

6.60 ±0.20 (5.34)

(5.04) (1.50)

2.30 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

(0.90)

(0.70)

MIN0.55

(1.00)

9.50 ±0.30

(2XR0.25)

6.10 ±0.20

2.70 ±0.20 (0.10) (3.05)

0.76 ±0.10

Rev. A, May 2000

FQD1N50B / FQU1N50B

Package Dimensions

6.60 ±0.20

5.34 ±0.20

(0.50) (0.50)(4.34)

0.60 ±0.20

(Continued)

IPAK

0.70 ±0.20

2.30 ±0.20

0.50 ±0.10

6.10 ±0.20

0.80 ±0.10

MAX0.96

0.76 ±0.10

2.30TYP

[2.30±0.20]

1.80 ±0.20

2.30TYP

[2.30±0.20]

16.10 ±0.30

9.30 ±0.30

0.50 ±0.10

Rev. A, May 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOS EnSigna

TM

FACT™ FACT Quiet Series™

®

FAST

FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench

®

QFET™ QS™ QT Optoelectronics™

Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™

VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. F1

Datasheet FQU1N50B Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual