The FP2189 is a high performance 1-Watt HFET
(Heterostructure FET) in a low-cost SOT-89 surfacemount package. This device works optimally at a drai
ias of +8 V and 250 mA to achieve +45 dBm outpu
IP3 performance and an output power of +31 dBm a
1-dB compression.
The device conforms to WJ Communications’ long
history of producing high reliability and qualit
components. The FP2189 has an associated MTBF o
greater than 100 years at a mounting temperature o
85°C. All devices are 100% RF & DC tested.
The product is targeted for use as driver amplifiers fo
wireless infrastructure where high performance and high
efficiency are required.
Functional Diagram
4
2
1 3
Function Pin No.
Input 1
Ground 2
Output/Bias 3
Ground 4
Specifications
DC Electrical Parameter UnitsMin Typ Max
Saturated Drain Current1, I
Transconductance, Gm mS
Pinch Off Voltage2, Vp V
mA 500
dss
350
-2.0
Parameters3 UnitsMin Typ Max
Frequency Range MHz 50 4000
Small Signal Gain, Gss dB
Output P1dB dBm
Output IP34 dBm
Thermal Resistance °C/W
1. I
is measured with Vgs = 0 V, Vds = 3 V.
dss
2. Pinch-off voltage is measured when Ids = 0.4 mA.
3. Test conditions unless otherwise noted: T = 25ºC, VDS = 8 V, IDQ = 250 mA, frequency = 900 MHz
in an application circuit with ZL = Z
4. 3OIP measured with two tones at an output power of +15 dBm/tone separated by 1 MHz. The
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
LOPT
, ZS = Z
SOPT
.
15
+31
+45
30
Absolute Maximum Ratings
Parameters Rating
Operating Case Temperature
Storage Temperature
Maximum DC Power 4.0 W
RF Input Power (continuous) +20 dBm
Operation of this device above any of there parameters may cause permanent damage
-40 to +85 °C
-40 to +125 °C
Typical Parameters5
Parameter UnitsTypical
Frequency MHz 915 1960 2140
S21 dB
S11 dB
S22 dB
Output P1dB dBm
Output IP3 dBm
Noise Figure dB
Vdd V
6
I
mA
dq
Idd at P1dB mA
5. Typical parameters represent performance in an application circuit.
6. Idq is the quiescent drain current at small signal output levels. The
current may increase as the output power is increased near its
compression point.
Specifications and information are subject to change without notice
• Web site: www.wj.com
May 2002
Page 2
FP2189
1 Watt HFET
Typical Performance Data
S-Parameters (V
3 GHz
2 GHz
Note:
Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines. The S-parameters
that are shown are the de-embedded data down to the device leads and represents typical performance of the device.
The layout of this circuit can be downloaded from the website.
Specifications and information are subject to change without notice
• Web site: www.wj.com
May 2002
Page 6
d
d
f
The Communications Edge TM
FP2189
1 Watt HFET
Application Note
Special attention should be taken to properly bias the FP2189. Power supply sequencing
is required to prevent the device from operating at 100% I
time and possibly causing damage to the device. It is recommended that for the safest
operation, the negative supply be “first on and last off.” With a negative gate voltage
present, the drain voltage can then be applied to the device. The gate voltage can then
be adjusted to have the device be used at the proper quiescent bias condition.
An optional temperature-compensation active-bias circuit is recommended for use with
the application circuit, which requires two standard voltage supplies +8V and -4V, an
is set for an optimal drain bias of +8V @ 250 mA. The circuit schematic, shown on the
right, uses dual PNP transistors to provide a constant drain current into the FP2189 an
also eliminates the effects of pinchoff variation. Temperature compensation is achieved
by tracking the voltage variation with the temperature of the emitter-to-base junction o
the PNP transistors. Thus the transistor emitter voltage adjusts the voltage incident at
the gate of the FP2189 so that the device draws a constant current, regardless of the
temperature. Two fixed voltage supplies are needed for operation. A Rohm dual
transistor, UMT1N, and a dual-chip resistor (8.2 kΩ) are recommended to minimize
board space and help decrease the current variability through R4 with the components
being matched to one another. The active-bias circuit can directly be attached to the
voltage supply ports in the circuit diagram as shown above (V
for a prolonged period of
dss
and Vgg).
dd
Outline Drawing Land Pattern Mounting Configuration
Preliminary Product Information
Vdd = +8 V
R4
R3
220 Ω
R5
8.2 kΩ
Vgg = -4 V
R6
8.2 kΩ
4
5 2
3
Connected to Vgg
1 Ω
1%
0805
1
6
on App Circuit
UMT1N
Connected to Vdd
on App Circuit
This document contains information on a new product.