Datasheet FDW2521C Datasheet (Fairchild Semiconductor)

May 2002

FDW2521C

Complementary PowerTrench



MOSFET

FDW2521C

General Description

This complementary MOSFET device is produced using
Fairchild’s advanced PowerTrench process that has
been especially tailored to minimize the on-state
resistance and yet maintain low gate charge for
superior switching performance.

Applications

• DC/DC conversion

• Power management

• Load switch

G

2

S

2

S

2

D

2

G

1

S

1

S

1

D

1

TSSOP-8

Pin 1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Features

• Q1: N-Channel

5.5 A, 20 V. R
R

= 21 mΩ @ VGS = 4.5 V

DS(ON)

= 35 mΩ @ VGS = 2.5 V

DS(ON)

• Q2: P-Channel
–3.8 A, 20 V. R
R

= 43 mΩ @ VGS = –4.5 V

DS(ON)

= 70 mΩ @ VGS = –2.5 V

DS(ON)

• High performance trench te chnology for extremely

DS(ON)

low R

• Low profile TSSOP-8 package

1
2
3
4

Q1 Q2

8
7
6
5

Symbol Parameter Q1 Q2 Units

V

Drain-Source Voltage 20 –20 V

DSS

V

Gate-Source Voltage

GSS

±12 ±12

V

ID Drain Current - Continuous (Note 1a) 5.5 –3.8 A

- Pulsed 30 –30
PD Power Dissipation (Note 1a) 1.0 W

TJ, T

STG

Operating and Storage Junction Temperature Range -55 to +150

(Note 1b)

0.6
°C

Thermal Characteristics

R

θJA

Thermal Resistance, Junction-to-Ambient

(Note 1a) 125
(Note 1b)

208

°C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

2521C FDW2521C 13’’ 12mm 3000 units

2002 Fairchild Semiconductor Corporation

FDW2521C Rev D( W)

FDW2521C

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

Drain-Source Breakdown

DSS

Voltage

∆BVDSS
∆T

J

I

Zero Gate Voltage Drain

DSS

Breakdown Voltage
Temperature Coefficient

Current

I

Gate-Body Leakage VGS = +12 V, VDS = 0 V

GSS

VGS = 0 V, ID = 250 µA
V

= 0 V, ID = –250 µA

GS

I

= 250 µA, Referenced to 25°C

D

= –250 µA, Referenced to 25°C

I

D

VDS = 16 V, VGS = 0 V
V

= –16 V, VGS = 0 V

DS

= +12 V, VDS = 0 V

V

GS

Q1
Q2

–20
Q1
Q2

Q1
Q2

Q1
Q2

20

V

14

–16

1

–1

+

+

100
100

mV/°C

µA
nA

On Characteristics (Note 2)

Q1

0.6

0.8

V

Gate Threshold Voltage VDS = VGS, ID = 250 µA

GS(th)

∆VGS(th)
∆TJ

R

DS(on)

Gate Threshold Voltage
Temperature Coefficient

Static Drain-Source

On-Resistance

V

I

On-State Drain Current VGS = 4.5 V, VDS = 5 V

D(on)

= VGS, ID = –250 µA

V

DS

= 250 µA, Referenced to 25°C

I

D

= –250 µA, Referenced to 25°C

I

D

VGS = 4.5 V, ID = 5.5 A
V

= 2.5 V, ID = 4.2 A

GS

= 4.5 V, ID = 5.5 A, TJ = 125°C

V

GS

= –4.5 V, ID = –3.8 A

GS

= –2.5 V, ID = –3.0 A

V

GS

= –4.5 V, ID = –3.8 A, TJ = 125°C

V

GS

= –4.5 V, VDS = –5 V

V

GS

gFS Forward Transconductance VDS = 5 V, ID = 5.5 A

V

= –5 V, ID = –3.5 A

DS

Q2

–0.6

Q1

–3.2

Q2
Q1

17

Q2 36

Q1

30

Q2

–15
Q1

26

Q2

1.5

–1.0

–1.5 V

mV/°C

3.0
21

24
23

mΩ
35
34

43

56

70

49

69

A

S

13.2

Dynamic Characteristics

C

Input Capacitance Q1

iss

C

Output Capacitance Q1

oss

C

Reverse Transfer

rss

Capacitance

Q1:
V

= 10 V, VGS = 0 V,

DS

f = 1.0 MHz
Q2:

= –10 V, VGS = 0 V,

V

DS

f = 1.0 MHz

Q2
Q2

Q1
Q2

1082

1030

277

280

130

120

pF
pF
pF

Switching Characteristics

t

Turn-On Delay Time

d(on)

tr Turn-On Rise Time
t

Turn-Off Delay Time

d(off)

tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge

Q1:
VDD = 10 V, ID = 1 A,

= 4.5 V, R

V

GS

GEN

= 6 Ω
Q2:
V

= –5 V, ID = –1 A,

DD

= –4.5V, R

V

GS

GEN

= 6 Ω

Q1:

= 10 V, ID = 5.5 A, VGS = 4.5 V

V

DS

Q2:

= –5 V, ID = –3.8 A,VGS = –4.5 V

V

DS

Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2

8

11

8

18

24

34

8

34

12

9.7

2

2.2

3

2.4

20
20
27
32
38
55
16
55
17

nC

16

nC
nC

ns
ns
ns
ns

FDW2521C Rev D( W)

Electrical Characteristics (continued) T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current Q1
VSD Drain-Source Diode Forward

Voltage

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

θJA

the drain pins. R

a) R

is 125°C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.

θJA

is 208°C/W (steady state) when mounted on a minimum copper pad on FR-4.

b) R

θJA

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

is guaranteed by design while R

θJC

VGS = 0 V, IS = 0.83 A (Note 2)
VGS = 0 V, IS = –0.83 A (Note 2)

is determined by the user's board design.

θCA

0.83
Q2
Q1
Q2

0.7

–0.7

–0.83 A

1.2

–1.2 V

FDW2521C

FDW2521C Rev D( W)

)

E

)

)

Typical Characteristics: Q1

FDW2521C

30

VGS = 4.5V

25

20

15

10

, DRAIN CURRENT (A

D

I

5

0

3.5V

0 0.5 1 1.5 2 2.5 3

3.0V

2.5V

V

, DRAIN-SOURCE VOLTAGE (V)

DS

2.0V

2.5

2

VGS = 2.0V

1.5

, NORMALIZED

DS(ON)

1

R

DRAIN-SOURCE ON-RESISTANCE

0.5
0 5 10 15 20 25 30

2.5V

3.0V

3.5V

, DRAIN CURRENT (A)

I

D

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

1.6
ID = 5.5A

= 4.5V

V

GS

1.4

1.2

, NORMALIZED

1

DS(ON)

R

0.8

DRAIN-SOURCE ON-RESISTANC

0.6

-50 -25 0 25 50 75 100 125 150

, JUNCTION TEMPERATURE (oC)

T

J

0.07

0.06

0.05

0.04

0.03

, ON-RESISTANCE (OHM)

0.02

DS(ON)

R

0.01

0

12345

TA = 25oC

V

, GATE TO SOURCE VOLTAGE (V)

GS

TA =

4.0V

4.5V

ID = 2.8 A

Figure 3. On-Resistance Variation with

Temperature.

30

VDS = 5V

25

20

15

10

, DRAIN CURRENT (A

D

I

5

0

0.511.522.53

V

GS

TA = -55oC

125oC

, GATE TO SOURCE VOLTAGE (V)

25oC

Figure 4. On-Resistance Variation with

Gate-to-Source Voltage.

100

VGS = 0V

10

1

0.1

0.01

0.001

, REVERSE DRAIN CURRENT (A

S

I

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

TA = 125oC

25oC

-55oC

V

, BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

FDW2521C Rev D( W)

)

Typical Characteristics: Q1

FDW2521C

5

ID = 5.5A

4

3

2

1

, GATE-SOURCE VOLTAGE (V)

GS

V

0

02468101214

, GATE CHARGE (nC)

Q

g

VDS = 5V

10V

15V

1800

1500

C

1200

900

600

CAPACITANCE (pF)

300

0

0 4 8 12 16 20

ISS

C

OSS

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

C

RSS

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

100

R

LIMIT

DS(ON)

10

100ms

1s

1

VGS = 4.5V

SINGLE PULSE

, DRAIN CURRENT (A

0.1

D

I

0.01

= 250oC/W

R

θ

JA

T

= 25oC

A

0.1 1 10 100

10s

DC

, DRAIN-SOURCE VOLTAGE (V)

V

DS

1ms

10ms

50

40

30

20

10

P(pk), PEAK TRANSIENT POWER (W)

0

0.001 0.01 0.1 1 10 100 1000

, TIME (sec)

t

1

SINGLE PULSE
R

θ

f = 1MHz
V

= 250°C/W

JA

= 25°C

T

A

GS

= 0 V

Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum

Power Dissipation.

FDW2521C Rev D( W)

Typical Characteristics: Q2

FDW2521C

30

VGS = -4.5V

-4.0V

24

18

12

6

0

012345

-3.5V

-3.0V

-2.5V

, DRAIN-SOURCE VOL TAG E (V)

-V

DS

-2.0V

1.6

VGS = -2.5V

1.4

1.2

1

0.8
0 5 10 15 20 25 30

-3.0V

-3.5V

, DRAIN CURRENT (A)

- I

D

-4.0V

-4.5V

Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with

Drain Current and Gate Voltage.

1.6
ID = -3.8A

V

= -4.5V

GS

1.4

1.2

1

0.8

0.6

-50 -25 0 25 50 75 100 125 150

, JUNCTION TEMPERATURE (oC)

T

J

0.15

0.12

0.09
TA = 125oC

0.06

0.03

0

1.522.533.544.55

TA = 25oC

-V

, GATE TO SOURCE VOLTAGE (V)

GS

ID = -1.9A

Figure 13. On-Resistance Variation with

Temperature.

30

VDS = -5.0V

24

18

12

6

0

0.4 1.3 2.2 3.1 4

, GATE TO SOURCE VOLTAGE (V)

-V

GS

TA = -55oC

25oC

125oC

Figure 14. On-Resistance Variation with

Gate-to-Source Voltage.

100

VGS = 0V

10

1

0.1

0.01

0.001

0.0001

0 0.2 0.4 0.6 0.8 1 1.2 1.4

TA = 125oC

25oC

-55oC

, BODY DIODE FORWARD VOLTAG E (V)

-V

SD

Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation

with Source Current and Temperature.

FDW2521C Rev D( W)

)

)

Typical Characteristics: Q2

FDW2521C

5

ID = -3.8A VDS = -5V

4

3

2

1

0

036912

Q

, GATE CHARGE ( nC)

g

-10V

-15V

1800

1500

1200

900

600

300

0

C

ISS

C

OSS

C

RSS

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

-V

DS

Figure 17. Gate Charge Characteristics. Figure 18. Capacitance Characteristics.

100

100µs

10

R

LIMIT

DS(ON)

1

VGS = -4.5V

SINGLE PULSE

, DRAIN CURRENT (A

0.1

D

I

R

= 250oC/W

θ

JA

T

= 25oC

A

0.01

0.01 0.1 1 10 100

, DRAIN-SOURCE VOLTAGE (V)

V

DS

10s

DC

100ms

1s

10ms

1ms

20

SINGLE PULSE
R

= 250°C/W

θ

15

10

5

P(pk), PEAK TRANSIENT POWER (W)

0

0.01 0.1 1 10 100

, TIME (sec)

t

1

JA

T

= 25°C

A

f = 1MHz

= 0 V

V

GS

Figure 19. Maximum Safe Operating Area. Figure 20. Single Pulse Maximum

Power Dissipation.

1

D = 0.5

0.2

0.1

0.01

r(t), NORMALIZED EFFECTIVE

0.001

TRANSIENT THERMAL RESISTANCE

0.0001 0.001 0.01 0.1 1 10 100 1000

0.1

0.05

0.02

0.01

SINGLE PULSE

t

, TIME (sec)

1

R

(t) = r(t) + R

θJA

R

= 250 °C/W

JA

θ

P(pk

t

1

t

2

T

- TA = P * R

J

Duty Cycle, D = t

θJA

(t)

θJA

/ t

1

2

Figure 21. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.

FDW2521C Rev D( W)

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx
Bottomless
CoolFET
CROSSVOL T
DenseTrench
DOME
EcoSPARK
E2CMOS
EnSigna

TM

TM

FACT
FACT Quiet Series

STAR*POWER is used under license

FAST
FASTr
FRFET
GlobalOptoisolator
GTO
HiSeC

2

I

C
ISOPLANAR
LittleFET
MicroFET
MicroPak

MICROWIRE
OPTOLOGIC

â

OPTOPLANAR
PACMAN
POP
Power247
PowerTrench

â

QFET
QS
QT Optoelectronics
Quiet Series

SILENT SWITCHER
SMART START
SPM
STAR*POWER
Stealth
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
TinyLogic
TruTranslation

ââ

UHC
UltraFET
VCX

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

â

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H5